Table of Contents

• Can't See the Forest for the Trees: State Restoration's Limitations in Post-silicon Trace Signal SelectionSai Ma, Debjit Pal, Rui Jiang, Sandip Ray, Shobha Vasudevan. 1-8 [doi]
• Yield Forecasting in Fab-to-Fab Production Migration Based on Bayesian Model FusionAli Ahmadi, Haralampos-G. D. Stratigopoulos, Amit Nahar, Bob Orr, Michael Pas, Yiorgos Makris. 9-14 [doi]
• Reduced Overhead Error Compensation for Energy Efficient Machine Learning KernelsSai Zhang, Naresh R. Shanbhag. 15-21 [doi]
• A Light-Weighted Software-Controlled Cache for PCM-based Main Memory SystemsHung-Sheng Chang, Yuan-Hao Chang, Tei-Wei Kuo, Hsiang-Pang Li. 22-29 [doi]
• Access Pattern Reshaping for eMMC-enabled SSDsChien-Chung Ho, Yuan-Hao Chang, Tei-Wei Kuo. 30-37 [doi]
• STRAP: Stress-Aware Placement for Aging Mitigation in Runtime Reconfigurable ArchitecturesHongyan Zhang, Michael A. Kochte, Eric Schneider, Lars Bauer, Hans-Joachim Wunderlich, Jörg Henkel. 38-45 [doi]
• Self-Aware Cyber-Physical Systems-on-ChipNikil D. Dutt, Axel Jantsch, Santanu Sarma. 46-50 [doi]
• Fine-Grained Aging Prediction Based on the Monitoring of Run-Time Stress Using DfT InfrastructureAbhishek Koneru, Arunkumar Vijayan, Krishnendu Chakrabarty, Mehdi Baradaran Tahoori. 51-58 [doi]
• Self Learning Analog/Mixed-Signal/RF Systems: Dynamic Adaptation to Workload and Environmental UncertaintiesDebashis Banerjee, Shreyas Sen, Abhijit Chatterjee. 59-64 [doi]
• Formal Methods for Emerging TechnologiesRobert Wille, Rolf Drechsler. 65-70 [doi]
• Code Transformations Based on Speculative SDC SchedulingMarco Lattuada, Fabrizio Ferrandi. 71-77 [doi]
• ElasticFlow: A Complexity-Effective Approach for Pipelining Irregular Loop NestsMingxing Tan, Gai Liu, Ritchie Zhao, Steve Dai, Zhiru Zhang. 78-85 [doi]
• Communication Scheduling and Buslet Synthesis for Low-Interconnect HLS DesignsEnzo Tartaglione, Shantanu Dutt. 86-93 [doi]
• MeMin: SAT-based Exact Minimization of Incompletely Specified Mealy MachinesAndreas Abel 0002, Jan Reineke. 94-101 [doi]
• Global Routing with Inherent Static Timing ConstraintsStephan Held, Dirk Müller 0003, Daniel Rotter, Vera Traub, Jens Vygen. 102-109 [doi]
• TILA: Timing-Driven Incremental Layer AssignmentBei Yu, Derong Liu, Salim Chowdhury, David Z. Pan. 110-117 [doi]
• Accelerate FPGA Routing with Parallel Recursive PartitioningMinghua Shen, Guojie Luo. 118-125 [doi]
• Synthesis for Power-Aware Clock SpinesHyungjung Seo, Juyeon Kim, Minseok Kang, Taewhan Kim. 126-131 [doi]
• A Novel Way to Authenticate Untrusted Integrated CircuitsWei Yan, Fatemeh Tehranipoor, John A. Chandy. 132-138 [doi]
• RRAM Based Lightweight User AuthenticationMd Tanvir Arafin, Gang Qu. 139-145 [doi]
• EM-Based on-Chip Aging Sensor for Detection and Prevention of Counterfeit and Recycled ICsKai He, Xin Huang, Sheldon X.-D. Tan. 146-151 [doi]
• BoardPUF: Physical Unclonable Functions for Printed Circuit Board AuthenticationLingxiao Wei, Chaosheng Song, Yannan Liu, Jie Zhang, Feng Yuan, Qiang Xu. 152-158 [doi]
• Fine-Grain Power Management in Manycore Processor and System-on-Chip (SoC) DesignsVivek De. 159-164 [doi]
• The (Low) Power of Less Wiring: Enabling Energy Efficiency in Many-Core Platforms Through Wireless NoCPartha Pratim Pande, Ryan Gary Kim, Wonje Choi, Zhuo Chen, Diana Marculescu, Radu Marculescu. 165-169 [doi]
• Mathematical Models and Control Algorithms for Dynamic Optimization of Multicore Platforms: A Complex Dynamics ApproachPaul Bogdan, Yuankun Xue. 170-175 [doi]
• Mitigating the Power Density and Temperature Problems in the Nano-EraMuhammad Shafique, Jörg Henkel. 176-177 [doi]
• Optimizing Stochastic Circuits for Accuracy-Energy TradeoffsArmin Alaghi, Wei-Ting Jonas Chan, John P. Hayes, Andrew B. Kahng, Jiajia Li. 178-185 [doi]
• Analytically Modeling Power and Performance of a CNN SystemIndranil Palit, Qiuwen Lou, Nicholas Acampora, Joseph Nahas, Michael T. Niemier, Xiaobo Sharon Hu. 186-193 [doi]
• Mitigating Effects of Non-ideal Synaptic Device Characteristics for On-chip LearningPai-Yu Chen, Binbin Lin, I.-Ting Wang, Tuo-Hung Hou, Jieping Ye, Sarma B. K. Vrudhula, Jae-sun Seo, Yu Cao, Shimeng Yu. 194-199 [doi]
• Robust Communication with IoT Devices using Wearable Brain Machine InterfacesMd Muztoba, Ujjwal Gupta, Tanvir Mustofa, Ümit Y. Ogras. 200-207 [doi]
• Simulation-Guided Parameter Synthesis for Chance-Constrained Optimization of Control SystemsYan Zhang, Sriram Sankaranarayanan, Benjamin M. Gyori. 208-215 [doi]
• A Mixed Discrete-Continuous Optimization Scheme for Cyber-Physical System Architecture ExplorationJohn B. Finn, Pierluigi Nuzzo, Alberto L. Sangiovanni-Vincentelli. 216-223 [doi]
• A User-Centric CPU-GPU Governing Framework for 3D Games on Mobile DevicesWei-Ming Chen, Sheng-Wei Cheng, Pi-Cheng Hsiu, Tei-Wei Kuo. 224-231 [doi]
• SAT Solving using FPGA-based Heterogeneous ComputingJason Thong, Nicola Nicolici. 232-239 [doi]
• Heterogeneous Hardware/Software Acceleration of the BWA-MEM DNA Alignment AlgorithmNauman Ahmed, Vlad Mihai Sima, Ernst Houtgast, Koen Bertels, Zaid Al-Ars. 240-246 [doi]
• Evolving EDA Beyond its E-Roots: An OverviewAndrew B. Kahng, Farinaz Koushanfar. 247-254 [doi]
• DA Systemization of Knowledge: A Catalog of Prior Forward-Looking InitiativesFarinaz Koushanfar, Azalia Mirhoseini, Gang Qu, Zhiru Zhang. 255-262 [doi]
• Toward Metrics of Design Automation Research ImpactAndrew B. Kahng, Mulong Luo, Gi-Joon Nam, Siddhartha Nath, David Z. Pan, Gabriel Robins. 263-270 [doi]
• DA Vision 2015: From Here to EternityMiodrag Potkonjak, Deming Chen, Priyank Kalla, Steven P. Levitan. 271-277 [doi]
• Impact of Loop Transformations on Software ReliabilityJason Cong, Cody Hao Yu. 278-285 [doi]
• Error-Tolerant Processors: Formal Specification and VerificationAmeneh Golnari, Yakir Vizel, Sharad Malik. 286-293 [doi]
• FEMTO: Fast Error Analysis in Multipliers through Topological TraversalDeepashree Sengupta, Sachin S. Sapatnekar. 294-299 [doi]
• Pairwise Proximity-Based Features for Test Escape ScreeningFan Lin, Chun-Kai Hsu, Alberto Giovanni Busetto, Kwang-Ting Cheng. 300-306 [doi]
• Defect Clustering-Aware Spare-TSV Allocation for 3D ICsShengcheng Wang, Mehdi Baradaran Tahoori, Krishnendu Chakrabarty. 307-314 [doi]
• Performance Evaluation of Software-based Error Detection Mechanisms for Localizing Electrical Timing Failures under Dynamic Supply NoiseYutaka Masuda, Masanori Hashimoto, Takao Onoye. 315-322 [doi]
• High Level Synthesis of RDF Queries for Graph AnalyticsVito Giovanni Castellana, Marco Minutoli, Alessandro Morari, Antonino Tumeo, Marco Lattuada, Fabrizio Ferrandi. 323-330 [doi]
• CAMs as Synchronizing Caches for Multithreaded Irregular Applications on FPGAsSkyler Windh, Prerna Budhkar, Walid A. Najjar. 331-336 [doi]
• PUF-Based AuthenticationWenjie Che, Fareena Saqib, Jim Plusquellic. 337-344 [doi]
• Security Policy Enforcement in Modern SoC DesignsSandip Ray, Yier Jin. 345-350 [doi]
• Protecting Endpoint Devices in IoT Supply ChainKun Yang, Domenic Forte, Mark Mohammad Tehranipoor. 351-356 [doi]
• A Polyhedral-based SystemC Modeling and Generation Framework for Effective Low-power Design Space ExplorationWei Zuo, Warren Kemmerer, Jong Bin Lim, Louis-Noël Pouchet, Andrey Ayupov, Taemin Kim, Kyungtae Han, Deming Chen. 357-364 [doi]
• Uncore RPD: Rapid Design Space Exploration of the Uncore via Regression ModelingKarthik Sangaiah, Mark Hempstead, Baris Taskin. 365-372 [doi]
• Multi-Threaded Simics SystemC Virtual PlatformAsad Khan, Weiqiang Ma, Chris Wolf, Bengt Werner. 373-379 [doi]
• PARADE: A Cycle-Accurate Full-System Simulation Platform for Accelerator-Rich Architectural Design and ExplorationJason Cong, Zhenman Fang, Michael Gill, Glenn Reinman. 380-387 [doi]
• Provably Good Max-Min-m-neighbor-TSP-Based Subfield Scheduling for Electron-Beam Photomask FabricationZhi-Wen Lin, Shao-Yun Fang, Yao-Wen Chang, Wei-Cheng Rao, Chieh-Hsiung Kuan. 388-395 [doi]
• Triple Patterning Aware Detailed Placement Toward Zero Cross-Row Middle-of-Line ConflictYibo Lin, Bei Yu, Biying Xu, David Z. Pan. 396-403 [doi]
• Defect Probability of Directed Self-Assembly Lithography: Fast Identification and Post-Placement OptimizationSeongbo Shim, Woohyun Chung, Youngsoo Shin. 404-409 [doi]
• Simultaneous Guiding Template Optimization and Redundant Via Insertion for Directed Self-AssemblyShao-Yun Fang, Yun-Xiang Hong, Yi-Zhen Lu. 410-417 [doi]
• DRUM: A Dynamic Range Unbiased Multiplier for Approximate ApplicationsSoheil Hashemi, R. Iris Bahar, Sherief Reda. 418-425 [doi]
• Fast Lagrangian Relaxation Based Gate Sizing using Multi-ThreadingAnkur Sharma, David Chinnery, Sarvesh Bhardwaj, Chris C. N. Chu. 426-433 [doi]
• Asynchronous QDI Circuit Synthesis from Signal Transition ProtocolsBo-Yuan Huang, Yi-Hsiang Lai, Jie-Hong Roland Jiang. 434-441 [doi]
• SPOCK: Static Performance Analysis and Deadlock Verification for Efficient Asynchronous Circuit SynthesisChun-Hong Shih, Yi-Hsiang Lai, Jie-Hong Roland Jiang. 442-449 [doi]
• Learning Based Compact Thermal Modeling for Energy-Efficient Smart Building Management: (invited)Hengyang Zhao, Daniel Quach, Shujuan Wang, Hai Wang, Hai-Bao Chen, Xin Li, Sheldon X.-D. Tan. 450-456 [doi]
• From Robust Chip to Smart Building: CAD Algorithms and Methodologies for Uncertainty Analysis of Building PerformanceXiaoming Chen, Xin Li, Sheldon X.-D. Tan. 457-464 [doi]
• Security Analysis of Proactive Participation of Smart Buildings in Smart GridTianshu Wei, Bowen Zheng, Qi Zhu, Shiyan Hu. 465-472 [doi]
• Buildings to Grid Integration: A Dynamic Contract ApproachMehdi Maasoumy, Alberto L. Sangiovanni-Vincentelli. 473-478 [doi]
• On Relaxing Page Program Disturbance over 3D MLC Flash MemoryYu-Ming Chang, Yung-Chun Li, Yuan-Hao Chang, Tei-Wei Kuo, Chih-Chang Hsieh, Hsiang-Pang Li. 479-486 [doi]
• Variation-Aware Adaptive Tuning for Nanophotonic InterconnectsRui Wu, Chin-Hui Chen, Cheng Li, Tsung-Ching Huang, Fan Lan, Chong Zhang, Yun Pan, John E. Bowers, Raymond G. Beausoleil, Kwang-Ting Cheng. 487-493 [doi]
• Threshold Logic Synthesis Based on Cut PruningAugusto Neutzling, Jody Maick Matos, André Inácio Reis, Renato P. Ribas, Alan Mishchenko. 494-499 [doi]
• TEI-Turbo: Temperature Effect Inversion-Aware Turbo Boost for FinFET-Based Multi-Core SystemsErmao Cai, Diana Marculescu. 500-507 [doi]
• Detailed-Routability-Driven Analytical Placement for Mixed-Size Designs with Technology and Region ConstraintsChau-Chin Huang, Hsin-Ying Lee, Bo-Qiao Lin, Sheng-Wei Yang, Chin-Hao Chang, Szu-To Chen, Yao-Wen Chang. 508-513 [doi]
• High Performance Global Placement and Legalization Accounting for Fence RegionsNima Karimpour Darav, Andrew A. Kennings, David T. Westwick, Laleh Behjat. 514-519 [doi]
• POLAR 3.0: An Ultrafast Global Placement EngineTao Lin, Chris C. N. Chu, Gang Wu. 520-527 [doi]
• Exploiting Non-Critical Steiner Tree Branches for Post-Placement Timing OptimizationVinicius S. Livramento, Chrystian Guth, Renan Netto, José Luís Almada Güntzel, Luiz C. V. dos Santos. 528-535 [doi]
• A Flexible Architecture for Systematic Implementation of SoC Security PoliciesAbhishek Basak, Swarup Bhunia, Sandip Ray. 536-543 [doi]
• ConFirm: Detecting Firmware Modifications in Embedded Systems using Hardware Performance CountersXueyang Wang, Charalambos Konstantinou, Michail Maniatakos, Ramesh Karri. 544-551 [doi]
• Quantifying Timing-Based Information Flow in Cryptographic HardwareBaolei Mao, Wei Hu, Alric Althoff, Janarbek Matai, Jason Oberg, Dejun Mu, Timothy Sherwood, Ryan Kastner. 552-559 [doi]
• Detecting Hardware Trojans in Unspecified Functionality Using Mutation TestingNicole Fern, Kwang-Ting (Tim) Cheng. 560-566 [doi]
• A Sample Reduction Technique by Aliasing Channel Response for Fast Equalizing Transceiver DesignSooeun Lee, Gunbok Lee, Jae-Yoon Sim, Hong June Park, Wee Sang Park, Byungsub Kim. 567-574 [doi]
• Co-Learning Bayesian Model Fusion: Efficient Performance Modeling of Analog and Mixed-Signal Circuits Using Side InformationFa Wang, Manzil Zaheer, Xin Li, Jean-Olivier Plouchart, Alberto Valdes-Garcia. 575-582 [doi]
• STAVES: Speedy Tensor-Aided Volterra-Based Electronic SimulatorHaotian Liu, Xiaoyan Y. Z. Xiong, Kim Batselier, Lijun Jiang, Luca Daniel, Ngai Wong. 583-588 [doi]
• Simulation of Noise in Neurons and Neuronal CircuitsDeniz Kilinç, Alper Demir. 589-596 [doi]
• Acceleration of Nested Conditionals on CGRAs via Trigger SchemeShouyi Yin, Pengcheng Zhou, Leibo Liu, Shaojun Wei. 597-604 [doi]
• Smartphone Analysis and Optimization based on User Activity RecognitionYeseong Kim, Francesco Parterna, Sameer Tilak, Tajana Simunic Rosing. 605-612 [doi]
• Perception-Aware Power Management for Mobile Games via Dynamic Resolution ScalingArian Maghazeh, Unmesh D. Bordoloi, Mattias Villani, Petru Eles, Zebo Peng. 613-620 [doi]
• A Unified Stochastic Model for Energy Management in Solar-Powered Embedded SystemsNga Dang, Roberto Valentini, Eli Bozorgzadeh, Marco Levorato, Nalini Venkatasubramanian. 621-626 [doi]
• Machine Learning-Based Energy Management in a Hybrid Electric Vehicle to Minimize Total Operating CostXue Lin, Paul Bogdan, Naehyuck Chang, Massoud Pedram. 627-634 [doi]
• A Contract Design Approach for Colocation Data Center Demand ResponseKishwar Ahmed, Mohammad A. Islam, Shaolei Ren. 635-640 [doi]
• Design Methodologies, Models and Tools for Very-Large-Scale Integration of NEM Relay-Based CircuitsTian Qin, Sunil Rana, Dinesh Pamunuwa. 641-648 [doi]
• Full-chip Inter-die Parasitic Extraction in Face-to-Face-Bonded 3D ICsYarui Peng, Taigon Song, Dusan Petranovic, Sung Kyu Lim. 649-655 [doi]
• Power-Down Circuit Synthesis for Analog/Mixed-SignalMichael Zwerger, Maximilian Neuner, Helmut E. Graeb. 656-663 [doi]
• Statistical Learning in Chip (SLIC)Ronald D. Blanton, Xin Li, Ken Mai, Diana Marculescu, Radu Marculescu, Jeyanandh Paramesh, Jeff Schneider, Donald E. Thomas. 664-669 [doi]
• Dynamic Machine Learning Based Matching of Nonvolatile Processor Microarchitecture to Harvested Energy ProfileKaisheng Ma, Xueqing Li, Yongpan Liu, John Sampson, Yuan Xie 0001, Vijaykrishnan Narayanan. 670-675 [doi]
• Architectural Requirements for Energy Efficient Execution of Graph Analytics ApplicationsMuhammet Mustafa Ozdal, Serif Yesil, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk. 676-681 [doi]
• Bit-Write-Reducing and Error-Correcting Code Generation by Clustering Error-Correcting Codewords for Non-Volatile MemoriesTatsuro Kojo, Masashi Tawada, Masao Yanagisawa, Nozomu Togawa. 682-689 [doi]
• CAUSE: Critical Application Usage-Aware Memory System using Non-volatile Memory for Mobile DevicesYeseong Kim, Mohsen Imani, Shruti Patil, Tajana Simunic Rosing. 690-696 [doi]
• A universal ordered NoC design platform for shared-memory MPSoCWoo-Cheol Kwon, Li-Shiuan Peh. 697-704 [doi]
• Optimizing 3D NoC Design for Energy Efficiency: A Machine Learning ApproachSourav Das, Janardhan Rao Doppa, Daehyun Kim, Partha Pratim Pande, Krishnendu Chakrabarty. 705-712 [doi]
• Transient Noise Bounds using Vectorless Power Grid VerificationNaval Gupte, Jia Wang. 713-720 [doi]
• 1-Bit Compressed Sensing Based Framework for Built-in Resonance Frequency Prediction Using On-Chip Noise SensorsTao Wang, Jinglan Liu, Cheng Zhuo, Yiyu Shi. 721-728 [doi]
• Graph-based Dynamic Analysis: Efficient Characterization of Dynamic Timing and Activity DistributionsHari Cherupalli, John Sartori. 729-735 [doi]
• A General Framework for Efficient Performance Analysis of Acyclic Asynchronous PipelinesYi-Hsiang Lai, Chi-Chuan Chuang, Jie-Hong R. Jiang. 736-743 [doi]
• A Novel Entropy Production Based Full-Chip TSV Fatigue AnalysisTianchen Wang, Sandeep Kumar Samal, Sung Kyu Lim, Yiyu Shi. 744-751 [doi]
• Three-Tier 3D ICs for More Power Reduction: Strategies in CAD, Design, and Bonding SelectionTaigon Song, Shreepad Panth, Yoo-Jin Chae, Sung Kyu Lim. 752-757 [doi]
• Optimization of FinFET-based circuits using a dual gate pitch techniqueSravan K. Marella, Amit Ranjan Trivedi, Saibal Mukhopadhyay, Sachin S. Sapatnekar. 758-763 [doi]
• Redundancy based Interconnect Duplication to Mitigate Soft Errors in SRAM-based FPGAsNaifeng Jing, Jiacheng Zhou, Jian-Fei Jiang, Xin Chen, Weifeng He, Zhigang Mao. 764-769 [doi]
• Hardware Accelerator Design for Data CentersSerif Yesil, Muhammet Mustafa Ozdal, Taemin Kim, Andrey Ayupov, Steven M. Burns, Ozcan Ozturk. 770-775 [doi]
• Modern Big Data Analytics for "Old-fashioned" Semiconductor Industry ApplicationsYada Zhu, Jinjun Xiong. 776-780 [doi]
• Effective CAD Research in the Sea of PapersJinglan Liu, Da-Cheng Juan, Yiyu Shi. 781-785 [doi]
• Dynamically Resilient and Agile Fine-Grained Replication ConfigurationYifang Liu. 786-793 [doi]
• Property-Directed Synthesis of Reactive Systems from Safety SpecificationsTing Wei Chiang, Jie-Hong R. Jiang. 794-801 [doi]
• Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit StatesClayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin. 802-807 [doi]
• On-Chip Generation of Uniformly Distributed Constrained-Random Stimuli for Post-Silicon ValidationXiaobing Shi, Nicola Nicolici. 808-815 [doi]
• Reducing Post-Silicon Coverage Monitoring Overhead with Emulation and Bayesian Feature SelectionRicardo Ochoa Gallardo, Alan J. Hu, André Ivanov, Maryam S. Mirian. 816-823 [doi]
• ApproxEigen: An Approximate Computing Technique for Large-Scale Eigen-DecompositionQian Zhang, Ye Tian, Ting Wang, Feng Yuan, Qiang Xu. 824-830 [doi]
• Modeling and Mitigation of Extra-SoC Thermal Coupling Effects and Heat Transfer Variations in Mobile DevicesFrancesco Paterna, Tajana Simunic Rosing. 831-838 [doi]
• Just Enough is More: Achieving Sustainable Performance in Mobile Devices under Thermal LimitationsOnur Sahin, Paul Thomas Varghese, Ayse Kivilcim Coskun. 839-846 [doi]
• Learning-Based Power Modeling of System-Level Black-Box IPsDongwook Lee, Taemin Kim, Kyungtae Han, Yatin Hoskote, Lizy K. John, Andreas Gerstlauer. 847-853 [doi]
• Mixed Cell-Height Implementation for Improved Design Quality in Advanced NodesSorin Dobre, Andrew B. Kahng, Jiajia Li. 854-860 [doi]
• GasStation: Power and Area Efficient Buffering for Multiple Power Domain DesignChien Pang Lu, Iris Hui-Ru Jiang, Chin-Hsiung Hsu. 861-866 [doi]
• Scalable Detailed Placement Legalization for Complex Sub-14nm ConstraintsKwangsoo Han, Andrew B. Kahng, Hyein Lee. 867-873 [doi]
• A General and Exact Routing Methodology for Digital Microfluidic BiochipsOliver Keszocze, Robert Wille, Krishnendu Chakrabarty, Rolf Drechsler. 874-881 [doi]
• TAU 2015 Contest on Incremental Timing Analysis: Incremental Timing and CPPR AnalysisJin Hu, Greg Schaeffer, Vibhor Garg. 882-889 [doi]
• iTimerC 2.0: Fast Incremental Timing and CPPR AnalysisPei-Yu Lee, Iris Hui-Ru Jiang, Cheng-Ruei Li, Wei-Lun Chiu, Yu-Ming Yang. 890-894 [doi]
• OpenTimer: A High-Performance Timing Analysis ToolTsung-Wei Huang, Martin D. F. Wong. 895-902 [doi]
• iitRACE: A Memory Efficient Engine for Fast Incremental Timing Analysis and Clock Pessimism RemovalChaitanya Peddawad, Aman Goel, B. Dheeraj, Nitin Chandrachoodan. 903-909 [doi]
• Overview of the 2015 CAD Contest at ICCADNatarajan Viswanathan, Shih-Hsu Huang, Rung-Bin Lin, Myung-Chul Kim. 910-911 [doi]
• ICCAD 2015 Contest in 3D Interlayer Cooling Optimized NetworkArvind Sridhar, Mohamed M. Sabry, David Atienza. 912-915 [doi]
• ICCAD-2015 CAD Contest in Large-scale Equivalence Checking and Function Correction and Benchmark SuiteChih-Jen Hsu, Chi-An Wu, Wei-Hsun Lin, Kei-Yong Khoo. 916-920 [doi]
• ICCAD-2015 CAD Contest in Incremental Timing-driven Placement and Benchmark SuiteMyung-Chul Kim, Jin Hu, Jiajia Li, Natarajan Viswanathan. 921-926 [doi]
• Rebooting Computing and Low-Power Image Recognition ChallengeYung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte, Erik P. DeBenedictis, Rachit Garg, Ganesh Gingade, Bichlien Hoang, Yongzhen Huang, Boxun Li, Jingyu Liu, Wei Liu, Huizi Mao, Junran Peng, Tianqi Tang, Elie K. Track, Jingqiu Wang, Tao Wang, Yu Wang, Jun Yao. 927-932 [doi]