Clayton B. McDonald, Hsinwei Chou, Vijay Durairaj, Pey-Chang Kent Lin. Efficient Transistor-Level Symbolic Timing Simulation Using Cached Partial Circuit States. In Diana Marculescu, Frank Liu, editors, Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, ICCAD 2015, Austin, TX, USA, November 2-6, 2015. pages 802-807, ACM, 2015. [doi]
Abstract is missing.