Table of Contents

• University LSI design contestChun-Huat Heng. 1 [doi]
• Normally-off computing project: Challenges and opportunitiesHiroshi Nakamura, Takashi Nakada, Shinobu Miwa. 1-5 [doi]
• "All Programmable SOC FPGA for networking and computing in big data infrastructure"Ivo Bolsens, Georges G. E. Gielen, Kaushik Roy, Ulf Schneider. 1-3 [doi]
• Novel nonvolatile memory hierarchies to realize "normally-off mobile processors"Shinobu Fujita, Kumiko Nomura, Hiroki Noguchi, Susumu Takeda, Keiko Abe. 6-11 [doi]
• Normally-off MCU architecture for low-power sensor nodeMasanori Hayashikoshi, Yohei Sato, Hiroshi Ueki, Hiroyuki Kawai, Toru Shimizu. 12-16 [doi]
• Normally-off technologies for healthcare applianceShintaro Izumi, Hiroshi Kawaguchi, Masahiko Yoshimoto, Yoshikazu Fujimori. 17-20 [doi]
• A dual-loop injection-locked PLL with all-digital background calibration system for on-chip clock generationWei Deng, Ahmed Musa, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 21-22 [doi]
• A 950μW 5.5-GHz low voltage PLL with digitally-calibrated ILFD and linearized varactorSho Ikeda, Tatsuya Kamimura, Sang-yeop Lee, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu. 23-24 [doi]
• A swing-enhanced current-reuse class-C VCO with dynamic bias control circuitsTeerachot Siriburanon, Wei Deng, Kenichi Okada, Akira Matsuzawa. 25-26 [doi]
• Design of a high-performance Millimeter-wave amplifier using specific modelingXiaojun Bi, Yongxin Guo, Muthukumaraswamy Annamalai Arasu, M. S. Zhang, Yong-Zhong Xiong, Minkyu Je. 27-28 [doi]
• A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receiversZheng Song, Nan Qi, Baoyong Chi, Zhihua Wang. 29-30 [doi]
• An 8b extremely area efficient threshold configuring SAR ADC with source voltage shifting techniqueKentaro Yoshioka, Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro. 31-32 [doi]
• A single-inductor 8-channel output DC-DC boost converter with time-limited power distribution control and single shared hysteresis comparatorJungmoon Kim, Chulwoo Kim. 33-34 [doi]
• A DC-DC boost converter with variation tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applicationsJungmoon Kim, Minseob Shim, Junwon Jung, Heejun Kim, Chulwoo Kim. 35-36 [doi]
• 7.3 Gb/s universal BCH encoder and decoder for SSD controllersHoyoung Yoo, Youngjoo Lee, In-Cheol Park. 37-38 [doi]
• A high-speed and low-complexity lens distortion correction processor for wide-angle camerasWon-Tae Kim, Hui-Sung Jeong, Gwang-Ho Lee, Tae-Hwan Kim. 39-40 [doi]
• Analytical placement of mixed-size circuits for better detailed-routabilityShuai Li, Cheng-Kok Koh. 41-46 [doi]
• Lithographic defect aware placement using compact standard Cells without inter-cell marginSeongbo Shim, Yoojong Lee, Youngsoo Shin. 47-52 [doi]
• Structural planning of 3D-IC interconnects by block alignmentJohann Knechtel, Evangeline F. Y. Young, Jens Lienig. 53-60 [doi]
• Comprehensive die-level assessment of design rules and layoutsRani S. Ghaida, Yasmine Badr, Mukul Gupta, Ning Jin, Puneet Gupta. 61-66 [doi]
• Prefetching techniques for STT-RAM based last-level cache in CMP systemsMengjie Mao, Guangyu Sun, Yong Li 0009, Alex K. Jones, Yiran Chen. 67-72 [doi]
• CNPUF: A Carbon Nanotube-based Physically Unclonable Function for secure low-energy hardware designS. T. Choden Konigsmark, Leslie Hwang, Deming Chen, Martin D. F. Wong. 73-78 [doi]
• 3DCoB: A new design approach for Monolithic 3D Integrated circuitsHossam Sarhan, Sebastien Thuries, Olivier Billoint, Fabien Clermidy. 79-84 [doi]
• Emulator-oriented tiny processors for unreliable post-silicon devices: A case studyYuko Hara-Azumi, Masaya Kunimoto, Yasuhiko Nakashima. 85-90 [doi]
• Applying VLSI EDA to energy distribution system designSani R. Nassif, Gi-Joon Nam, Jerry Hayes, Sani Fakhouri. 91-96 [doi]
• A model-based design of Cyber-Physical Energy SystemsMohammad Abdullah Al Faruque, Fereidoun Ahourai. 97-104 [doi]
• The data center as a grid load stabilizerHao Chen, Michael C. Caramanis, Ayse Kivilcim Coskun. 105-112 [doi]
• Bounding buffer space requirements for real-time priority-aware networksHany Kashif, Hiren D. Patel. 113-118 [doi]
• Task- and network-level schedule co-synthesis of Ethernet-based time-triggered systemsLicong Zhang, Dip Goswami, Reinhard Schneider 0001, Samarjit Chakraborty. 119-124 [doi]
• Service adaptions for mixed-criticality systemsPengcheng Huang, Georgia Giannopoulou, Nikolay Stoimenov, Lothar Thiele. 125-130 [doi]
• Efficient feasibility analysis of DAG scheduling with real-time constraints in the presence of faultsXiaotong Cui, Jun Zhang, Kaijie Wu, Edwin Hsing-Mean Sha. 131-136 [doi]
• Flexible packed stencil design with multiple shaping apertures for e-beam lithographyChris Chu, Wai-Kei Mak. 137-142 [doi]
• Self-aligned double patterning layout decomposition with complementary e-beam lithographyJhih-Rong Gao, Bei Yu, David Z. Pan. 143-148 [doi]
• Fixing Double Patterning violations with look-aheadSambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala. 149-154 [doi]
• EUV-CDA: Pattern shift aware critical density analysis for EUV mask layoutsAbde Ali Kagalwalla, Michale Lam, Kostas Adam, Puneet Gupta. 155-160 [doi]
• Statistical analysis of random telegraph noise in digital circuitsXiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang. 161-166 [doi]
• Semi-analytical current source modeling of FinFET devices operating in near/sub-threshold regime with independent gate control and considering process variationTiansong Cui, Yanzhi Wang, Xue Lin, Shahin Nazarian, Massoud Pedram. 167-172 [doi]
• 2-SAT based linear time optimum two-domain clock skew schedulingYukihide Kohira, Atsushi Takahashi. 173-178 [doi]
• Power minimization of pipeline architecture through 1-cycle error correction and voltage scalingInsup Shin, Jae-Joon Kim, Youngsoo Shin. 179-184 [doi]
• A silicon nanodisk array structure realizing synaptic response of spiking neuron models with noiseTakashi Morie, Haichao Liang, Yilai Sun, Takashi Tohara, Makoto Igarashi, Seiji Samukawa. 185-190 [doi]
• Energy efficient in-memory machine learning for data intensive image-processing by non-volatile domain-wall memoryHao Yu, Yuhao Wang, Shuai Chen, Wei Fei, Chuliang Weng, Junfeng Zhao, Zhulin Wei. 191-196 [doi]
• Lessons from the neurons themselvesLouis Scheffer. 197-200 [doi]
• Leveraging the error resilience of machine-learning applications for designing highly energy efficient acceleratorsZidong Du, Krishna V. Palem, Lingamneni Avinash, Olivier Temam, Yunji Chen, Chengyong Wu. 201-206 [doi]
• ArISE: Aging-aware instruction set encoding for lifetime improvementFabian Oboril, Mehdi Baradaran Tahoori. 207-212 [doi]
• DRuiD: Designing reconfigurable architectures with decision-making supportGiovanni Mariani, Gianluca Palermo, Roel Meeuws, Vlad Mihai Sima, Cristina Silvano, Koen Bertels. 213-218 [doi]
• Edit distance based instruction merging technique to improve flexibility of custom instructions toward flexible accelerator designHui Huang, Taemin Kim, Yatin Hoskote. 219-224 [doi]
• A network-flow-based optimal sample preparation algorithm for digital microfluidic biochipsTrung Anh Dinh, Shigeru Yamashita, Tsung-Yi Ho. 225-230 [doi]
• Exploring speed and energy tradeoffs in droplet transport for digital microfluidic biochipsJohnathan Fiske, Daniel Grissom, Philip Brisk. 231-237 [doi]
• General purpose cross-referencing Microfluidic Biochip with reduced pin-countJackson H. C. Yeung, Evangeline F. Y. Young. 238-243 [doi]
• Wash optimization for cross-contamination removal in flow-based microfluidic biochipsKai Hu, Tsung-Yi Ho, Krishnendu Chakrabarty. 244-249 [doi]
• ABCD-NL: Approximating Continuous non-linear dynamical systems using purely Boolean models for analog/mixed-signal verificationAadithya V. Karthik, Sayak Ray, Pierluigi Nuzzo, Alan Mishchenko, Robert K. Brayton, Jaijeet Roychowdhury. 250-255 [doi]
• Toward efficient programming of reconfigurable radio frequency (RF) receiversJun Tao, Ying-Chih Wang, Minhee Jun, Xin Li, Rohit Negi, Tamal Mukherjee, Lawrence T. Pileggi. 256-261 [doi]
• Efficient matrix exponential method based on extended Krylov subspace for transient simulation of large-scale linear circuitsQuan Chen, Wenhui Zhao, Ngai Wong. 262-266 [doi]
• SDG2KPN: System Dependency Graph to function-level KPN generation of legacy code for MPSoCsJude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Alvin Labios, Yusuke Yachide. 267-273 [doi]
• Low power design of the next-generation High Efficiency Video CodingMuhammad Shafique, Jörg Henkel. 274-281 [doi]
• Mapping complex algorithm into FPGA with High Level Synthesis reconfigurable chips with High Level Synthesis compared with CPU, GPGPUKazutoshi Wakabayashi, Takashi Takenaka, Hiroaki Inoue. 282-284 [doi]
• Leveraging parallelism in the presence of control flow on CGRAsJihyun Ryoo, Kyuseung Han, Kiyoung Choi. 285-291 [doi]
• Physical-aware task migration algorithm for dynamic thermal management of SMT multi-core processorsBagher Salami, Mohammadreza Baharani, Hamid Noori, Farhad Mehdipour. 292-297 [doi]
• Agile frequency scaling for adaptive power allocation in many-core systems powered by renewable energy sourcesXiaohang Wang, Zhiming Li, Mei Yang, Yingtao Jiang, Masoud Daneshtalab, Terrence S. T. Mak. 298-303 [doi]
• Variation-aware voltage island formation for power efficient near-threshold manycore architecturesIoannis S. Stamelakos, Sotirios Xydis, Gianluca Palermo, Cristina Silvano. 304-310 [doi]
• An evaluation of an energy efficient many-core SoC with parallelized face detectionHiroyuki Usui, Jun Tanabe, Toru Sano, Hui Xu, Takashi Miyamori. 311-316 [doi]
• Energy aware real-time scheduling policy with guaranteed security protectionWei Jiang, Ke Jiang, Xia Zhang, Yue Ma. 317-322 [doi]
• A comprehensive and accurate latency model for Network-on-Chip performance analysisZhiliang Qian, Da-Cheng Juan, Paul Bogdan, Chi-Ying Tsui, Diana Marculescu, Radu Marculescu. 323-328 [doi]
• A low-latency asynchronous interconnection network with early arbitration resolutionGeorgios Faldamis, WeiWei Jiang, Gennette Gill, Steven M. Nowick. 329-336 [doi]
• A vertically integrated and interoperable multi-vendor synthesis flow for predictable noc design in nanoscale technologiesAlberto Ghiribaldi, Hervé Tatenguem Fankem, Federico Angiolini, Mikkel Bystrup Stensgaard, Tobias Bjerregaard, Davide Bertozzi. 337-342 [doi]
• Fuzzy flow regulation for Network-on-Chip based chip multiprocessors systemsYuan Yao, Zhonghai Lu. 343-348 [doi]
• Adjustable contiguity of run-time task allocation in networked many-core systemsMohammad Fattah, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen. 349-354 [doi]
• STD-TLB: A STT-RAM-based dynamically-configurable translation lookaside buffer for GPU architecturesXiaoxiao Liu, Yong Li 0009, Yaojun Zhang, Alex K. Jones, Yiran Chen. 355-360 [doi]
• Training itself: Mixed-signal training acceleration for memristor-based neural networkBoxun Li, Yuzhi Wang, Yu Wang, Yiran Chen, Huazhong Yang. 361-366 [doi]
• HDTV1080p HEVC Intra encoder with source texture based CU/PU mode pre-decisionJia Zhu, Zhenyu Liu, Dongsheng Wang, Qingrui Han, Yang Song. 367-372 [doi]
• Fast large-scale optimal power flow analysis for smart grid through network reductionYi Liang, Deming Chen. 373-378 [doi]
• Storage-less and converter-less maximum power point tracking of photovoltaic cells for a nonvolatile microprocessorCong Wang, Naehyuck Chang, Younghyun Kim, Sangyoung Park, Yongpan Liu, Hyung Gyu Lee, Rong Luo, Huazhong Yang. 379-384 [doi]
• Soft Error Resiliency Characterization on IBM BlueGene/Q ProcessorChen-Yong Cher, K. Paul Muller, Ruud A. Haring, David L. Satterfield, Thomas E. Musta, Thomas Gooding, Kristan D. Davis, Marc Boris Dombrowa, Gerard V. Kopcsay, Robert M. Senger, Yutaka Sugawara, Krishnan Sugavanam. 385-387 [doi]
• Resiliency for many-core system on a chipTanay Karnik, James Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar. 388-389 [doi]
• Rethinking error injection for effective resilienceShahrzad Mirkhani, Hyungmin Cho, Subhasish Mitra, Jacob A. Abraham. 390-393 [doi]
• Amphisbaena: Modeling two orthogonal ways to hunt on heterogeneous many-coresJun Ma, Guihai Yan, Yinhe Han, Xiaowei Li 0001. 394-399 [doi]
• Co-simulation framework for streamlining microprocessor development on standard ASIC design flowTomoyuki Nakabayashi, Tomoyuki Sugiyama, Takahiro Sasaki, Eric Rotenberg, Toshio Kondo. 400-405 [doi]
• Annotation and analysis combined cache modeling for native simulationRongjie Yan, De Ma, Kai Huang, Xiaoxu Zhang, Siwen Xiu. 406-411 [doi]
• A scorchingly fast FPGA-based Precise L1 LRU cache simulatorJosef Schneider, Jorgen Peddersen, Sri Parameswaran. 412-417 [doi]
• Redundant-via-aware ECO routingHsi-An Chien, Ting-Chi Wang. 418-423 [doi]
• A fast and provably bounded failure analysis of memory circuits in high dimensionsWei Wu, Fang Gong, Gengsheng Chen, Lei He. 424-429 [doi]
• Predicting circuit aging using ring oscillatorsDeepashree Sengupta, Sachin S. Sapatnekar. 430-435 [doi]
• Statistical analysis of process variation based on indirect measurements for electronic system designIvan Ukhov, Mattias Villani, Petru Eles, Zebo Peng. 436-442 [doi]
• Symbolic computation of SNR for variational analysis of sigma-delta modulatorJiandong Cheng, Guoyong Shi. 443-448 [doi]
• Sparse statistical model inference for analog circuits under process variationsYan Zhang, Sriram Sankaranarayanan, Fabio Somenzi. 449-454 [doi]
• Time-domain performance bound analysis for analog and interconnect circuits considering process variationsTan Yu, Sheldon X.-D. Tan, Yici Cai, Puying Tang. 455-460 [doi]
• A robustness optimization of SRAM dynamic stability by sensitivity-based reachability analysisYang Song, Sai Manoj Pudukotai Dinakarrao, Hao Yu. 461-466 [doi]
• Accurate and inexpensive performance monitoring for variability-aware systemsLiangzhen Lai, Puneet Gupta. 467-473 [doi]
• Quantifying workload dependent reliability in embedded processorsVikas Chandra. 474-477 [doi]
• QED post-silicon validation and debug: Frequently asked questionsDavid Lin, Subhasish Mitra. 478-482 [doi]
• Efficient synthesis of quantum circuits implementing clifford group operationsPhilipp Niemann, Robert Wille, Rolf Drechsler. 483-488 [doi]
• Optimal SWAP gate insertion for nearest neighbor quantum circuitsRobert Wille, Aaron Lye, Rolf Drechsler. 489-494 [doi]
• Qubit placement to minimize communication overhead in 2D quantum architecturesAlireza Shafaei, Mehdi Saeedi, Massoud Pedram. 495-500 [doi]
• A novel wirelength-driven packing algorithm for FPGAs with adaptive logic modulesSheng-Kai Wu, Po-Yi Hsu, Wai-Kei Mak. 501-506 [doi]
• A topology-based ECO routing methodology for mask cost minimizationPo-Hsun Wu, Shang-Ya Bai, Tsung-Yi Ho. 507-512 [doi]
• BOB-router: A new buffering-aware global router with over-the-block routing resources optimizationYilin Zhang, Salim Chowdhury, David Z. Pan. 513-518 [doi]
• Routability-driven bump assignment for chip-package co-designMeng-Ling Chen, Tu-Hsiung Tsai, Hung-Ming Chen, Shi-Hao Chen. 519-524 [doi]
• VFGR: A very fast parallel global router with accurate congestion modelingZhongdong Qi, Yici Cai, Qiang Zhou, Zhuoyuan Li, Mike Chen. 525-530 [doi]
• Efficient simulation-based optimization of power grid with on-chip voltage regulatorTing Yu, Martin D. F. Wong. 531-536 [doi]
• Walking pads: Fast power-supply pad-placement optimizationKe Wang, Brett H. Meyer, Runjie Zhang, Kevin Skadron, Mircea R. Stan. 537-543 [doi]
• Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal considerationYuanqing Cheng, Aida Todri-Sanial, Alberto Bosio, Luigi Dilillo, Patrick Girard, Arnaud Virazel. 544-549 [doi]
• SwimmingLane: A composite approach to mitigate voltage droop effects in 3D power delivery networkXing Hu, Yi Xu, Yu Hu, Yuan Xie. 550-555 [doi]
• Spiking brain models: Computation, memory and communication constraints for custom hardware implementationAnders Lansner, Ahmed Hemani, Nasim Farahini. 556-562 [doi]
• Advanced technologies for brain-inspired computingFabien Clermidy, Rodolphe Héliot, Alexandre Valentian, Christian Gamrat, Olivier Bichler, Marc Duranton, Bilel Belhadj, Olivier Temam. 563-569 [doi]
• GPGPU accelerated simulation and parameter tuning for neuromorphic applicationsKristofor D. Carlson, Michael Beyeler, Nikil Dutt, Jeffrey L. Krichmar. 570-577 [doi]
• A scalable custom simulation machine for the Bayesian Confidence Propagation Neural Network model of the brainNasim Farahini, Ahmed Hemani, Anders Lansner, Fabien Clermidy, Christer Svensson. 578-585 [doi]
• NoΔ: Leveraging delta compression for end-to-end memory access in NoC based multicoresJia Zhan, Matthew Poremba, Yi Xu, Yuan Xie. 586-591 [doi]
• DPA: A data pattern aware error prevention technique for NAND flash lifetime extensionJie Guo, Zhijie Chen, Danghui Wang, Zili Shao, Yiran Chen. 592-597 [doi]
• Scattered refresh: An alternative refresh mechanism to reduce refresh cycle timeT. Venkata Kalyan, Kasha Ravi, Madhu Mutyam. 598-603 [doi]
• A read-write aware DRAM scheduling for power reduction in multi-core systemsChih-Yen Lai, Gung-Yu Pan, Hsien-Kai Kuo, Jing-Yang Jou. 604-609 [doi]
• A coherent hybrid SRAM and STT-RAM L1 cache architecture for shared memory multicoresJianxing Wang, Yenni Tim, Weng-Fai Wong, Zhong-Liang Ong, Zhenyu Sun, Hai Helen Li. 610-615 [doi]
• Allocation of FPGA DSP-macros in multi-process high-level synthesis systemsBenjamin Carrión Schäfer. 616-621 [doi]
• Array scalarization in high level synthesisPreeti Ranjan Panda, Namita Sharma, Arun Kumar Pilania, Gummidipudi Krishnaiah, Sreenivas Subramoney, Ashok Jagannathan. 622-627 [doi]
• Data compression via logic synthesisLuca Gaetano Amarù, Pierre-Emmanuel Gaillardon, Andreas Burg, Giovanni De Micheli. 628-633 [doi]
• Synthesis of power- and area-efficient binary machines for incompletely specified sequencesNan Li, Elena Dubrova. 634-639 [doi]
• Multi-mode trace signal selection for post-silicon debugMin Li, Azadeh Davoodi. 640-645 [doi]
• Implicit intermittent fault detection in distributed systemsPeter Waszecki, Matthias Kauer, Martin Lukasiewycz, Samarjit Chakraborty. 646-651 [doi]
• A segmentation-based BISR schemeGeorgios Zervakis, Nikolaos Eftaxiopoulos-Sarris, Kostas Tsoumanis, Nicholas Axelos, Kiamal Z. Pekmestzi. 652-657 [doi]
• Fault-tolerant TSV by using scan-chain test TSVFu-Wei Chen, Hui-Ling Ting, TingTing Hwang. 658-663 [doi]
• Suppressing test inflation in shared-memory parallel Automatic Test Pattern GenerationJerry C. Y. Ku, Ryan H.-M. Huang, Louis Y.-Z. Lin, Charles H.-P. Wen. 664-669 [doi]
• A volume diagnosis method for identifying systematic faults in lower-yield wafer occurring during mass productionTsutomu Ishida, Izumi Nitta, Koji Banno, Yuzi Kanazawa. 670-675 [doi]
• An overview of spin-based integrated circuitsWang Kang, Weisheng Zhao, Zhaohao Wang, Jacques-Olivier Klein, Yue Zhang, Djaafar Chabi, Youguang Zhang, Dafine Ravelosona, Claude Chappert. 676-683 [doi]
• Advances in spintronics devices for microelectronics - From spin-transfer torque to spin-orbit torqueShunsuke Fukami, H. Sato, Michihiko Yamanouchi, S. Ikeda, Fumihiro Matsukura, Hideo Ohno. 684-691 [doi]
• Hybrid CMOS/magnetic Process Design Kit and SOT-based non-volatile standard cell architecturesGregory di Pendina, Kotb Jabeur, Guillaume Prenat. 692-699 [doi]
• Architectural aspects in design and analysis of SOT-based memoriesRajendra Bishnoi, Mojtaba Ebrahimi, Fabian Oboril, Mehdi Baradaran Tahoori. 700-707 [doi]
• Timing anomalies in multi-core architectures due to the interference on the shared resourcesHardik Shah, Kai Huang, Alois Knoll. 708-713 [doi]
• A unified online directed acyclic graph flow manager for multicore schedulersKarim Kanoun, David Atienza, Nicholas Mastronarde, Mihaela van der Schaar. 714-719 [doi]
• Variation-aware statistical energy optimization on voltage-frequency island based MPSoCs under performance yield constraintsSong Jin, Yinhe Han, Songwei Pei. 720-725 [doi]
• QoS-aware dynamic resource allocation for spatial-multitasking GPUsPaula Aguilera, Katherine Morrow, Nam Sung Kim. 726-731 [doi]
• Automated debugging of missing assumptionsBrian Keng, Evean Qin, Andreas G. Veneris, Bao Le. 732-737 [doi]
• Property Directed Reachability for QF_BV with mixed type atomic reasoning unitsTobias Welp, Andreas Kuehlmann. 738-743 [doi]
• Adaptive interpolation-based model checkingChien-Yu Lai, Cheng-Yin Wu, Chung-Yang (Ric) Huang. 744-749 [doi]
• Efficient parallel GPU algorithms for BDD manipulationMiroslav N. Velev, Ping Gao 0002. 750-755 [doi]
• Efficient techniques for the capacitance extraction of chip-scale VLSI interconnects using floating random walk algorithmChao Zhang, Wenjian Yu. 756-761 [doi]
• 3DLAT: TSV-based 3D ICs crosstalk minimization utilizing Less Adjacent Transition codeQiaosha Zou, Dimin Niu, Yan Cao, Yuan Xie. 762-767 [doi]
• Tackling close-to-band passivity violations in passive macro-modelingMoning Zhang, Zuochang Ye. 768-773 [doi]
• HIE-block latency insertion method for fast transient simulation of nonuniform multiconductor transmission linesTakahiro Takasaki, Tadatoshi Sekine, Hideki Asai. 774-779 [doi]
• The role of photons in cryptanalysisJuliane Krämer, Michael Kasper, Jean-Pierre Seifert. 780-787 [doi]
• SPADs for quantum random number generators and beyondSamuel Burri, Damien Stucki, Yuki Maruyama, Claudio Bruschini, Edoardo Charbon, Francesco Regazzoni. 788-794 [doi]
• Quantum key distribution with integrated opticsMirko Lobino, Pei Zhang, Enrique Martin-Lopez, Richard W. Nock, Damien Bonneau, Hong-wei Li, Antti O. Niskanen, Jeremy Lloyd O'Brien, Anthony Laing, Kanin Aungskunsiri, Joachim Wabnig, Jack Munns, Pisu Jiang, John G. Rarity, Mark G. Thompson. 795-799 [doi]
• Constraint-based platform variants specification for early system verificationAndreas Burger, Alexander Viehl, Andreas Braun, Finn Haedicke, Daniel Große, Oliver Bringmann, Wolfgang Rosenstiel. 800-805 [doi]
• A transaction-oriented UVM-based library for verification of analog behaviorAlexander W. Rath, Volkan Esen, Wolfgang Ecker. 806-811 [doi]
• Automata-theoretic modeling of fixed-priority non-preemptive scheduling for formal timing verificationMatthias Kauer, Sebastian Steinhorst, Reinhard Schneider 0001, Martin Lukasiewycz, Samarjit Chakraborty. 812-817 [doi]
• PROCEED: A pareto optimization-based circuit-level evaluator for emerging devicesShaodi Wang, Andrew Pan, Chi On Chui, Puneet Gupta. 818-824 [doi]
• Modeling and design analysis of 3D vertical resistive memory - A low cost cross-point architectureCong Xu, Dimin Niu, Shimeng Yu, Yuan Xie. 825-830 [doi]
• The stochastic modeling of TiO2 memristor and its usage in neuromorphic system designMiao Hu, Yu Wang, Qinru Qiu, Yiran Chen, Hai Li. 831-836 [doi]
• Through-silicon-via inductor: Is it real or just a fantasy?Umamaheswara Rao Tida, Cheng Zhuo, Yiyu Shi. 837-842 [doi]
• Design and control methodology for fine grain power gating based on energy characterization and code profiling of microprocessorsKimiyoshi Usami, Masaru Kudo, Kensaku Matsunaga, Tsubasa Kosaka, Yoshihiro Tsurui, Weihan Wang, Hideharu Amano, Hiroaki Kobayashi, Ryuichi Sakamoto, Mitaro Namiki, Masaaki Kondo, Hiroshi Nakamura. 843-848 [doi]
• A hybrid random walk algorithm for 3-D thermal analysis of integrated circuitsYuan Liang, Wenjian Yu, Haifeng Qian. 849-854 [doi]
• LightSim: A leakage aware ultrafast temperature simulatorSmruti R. Sarangi, Gayathri Ananthanarayanan, M. Balakrishnan. 855-860 [doi]
• Fast vectorless power grid verification using maximum voltage drop location estimationWei Zhao, Yici Cai, Jianlei Yang. 861-866 [doi]