Subramanian Rajagopalan - researchr alias

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Viewing Publication 1 - 15 from 15

2015

2SAT Based Infeasibility Resolution during Design Rule Correction on Layouts with Multiple GridsNitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. vlsid 2015: 186-191 [doi]

2014

Fixing Double Patterning violations with look-aheadSambuddha Bhattacharya, Subramanian Rajagopalan, Shabbir H. Batterywala. aspdac 2014: 149-154 [doi]

2013

Automatic design rule correction in presence of multiple grids and track patternsNitin Salodkar, Subramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. dac 2013: 26 [doi]

2009

Efficient Analog/RF Layout Closure with Compaction Based LegalizationSubramanian Rajagopalan, Sambuddha Bhattacharya, Shabbir H. Batterywala. vlsid 2009: 137-142 [doi]

2008

Cell Swapping Based Migration Methodology for Analog and Custom LayoutsShabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy. isqed 2008: 450-455 [doi]

On Efficient and Robust Constraint Generation for Practical Layout LegalizationSambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy. isqed 2008: 379-384 [doi]

2007

A 3-dimensional FEM Based Resistance ExtractionSubramanian Rajagopalan, Shabbir H. Batterywala. vlsid 2007: 565-570 [doi]

A Retargetable Very Long Instruction Word Compiler Framework for Digital Signal ProcessorsSubramanian Rajagopalan, Sharad Malik. In The Compiler Design Handbook, 2nd ed.. pages 18, 2007.

Impact of Modern Process Technologies on the Electrical Parameters of InterconnectsDebjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou. vlsid 2007: 875-880 [doi]

2004

A formal concurrency model based architecture description language for synthesis of software development toolsWei Qin, Subramanian Rajagopalan, Sharad Malik. lctrts 2004: 47-56 [doi]

2002

Design Tools for Application Specific Embedded ProcessorsWei Qin, Subramanian Rajagopalan, Manish Vachharajani, Hangsheng Wang, Xinping Zhu, David I. August, Kurt Keutzer, Sharad Malik, Li-Shiuan Peh. emsoft 2002: 319-333 [doi]

Retargetable Very Long Instuction Word Compiler Framework for Digital Signal ProcessorsSubramanian Rajagopalan, Sharad Malik. In The Compiler Design Handbook. pages 603-630, 2002.

2001

Optimal Live Range Merge for Address Register Allocation in Embedded ProgramsGuilherme Ottoni, Sandro Rigo, Guido Araujo, Subramanian Rajagopalan, Sharad Malik. CC 2001: 274-288 [doi]

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelismSubramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama. tcad, 20(11):1319-1328, 2001. [doi]

2000

Handling irregular ILP within conventional VLIW schedulers using artificial resource constraintsSubramanian Rajagopalan, Manish Vachharajani, Sharad Malik. cases 2000: 157-164 [doi]

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