Abstract is missing.
- GraalBench: a 3D graphics benchmark suite for mobile phonesIosif Antochi, Ben H. H. Juurlink, Stamatis Vassiliadis, Petri Liuha. 1-9 [doi]
- Modeling and simulating electronic textile applicationsThomas Martin, Mark T. Jones, Joshua Edmison, Tanwir Sheikh, Zahi Nakad. 10-19 [doi]
- Spinach: a liberty-based simulator for programmable network interface architecturesPaul Willmann, Michael Brogioli, Vijay S. Pai. 20-29 [doi]
- NDL: a domain-specific language for device driversChristopher L. Conway, Stephen A. Edwards. 30-36 [doi]
- Asynchronous software thread integration for efficient softwareNagendra J. Kumar, Siddhartha Shivshankar, Alexander G. Dean. 37-46 [doi]
- A formal concurrency model based architecture description language for synthesis of software development toolsWei Qin, Subramanian Rajagopalan, Sharad Malik. 47-56 [doi]
- Procrastination scheduling in fixed priority real-time systemsRavindra Jejurikar, Rajesh K. Gupta. 57-66 [doi]
- Power-efficient prefetching via bit-differential offset assignment on embedded processorsXiaotong Zhuang, Santosh Pande. 67-77 [doi]
- Speculative software management of datapath-width for energy optimizationGilles Pokam, Olivier Rochecouste, André Seznec, François Bodin. 78-87 [doi]
- Dynamic voltage scaling for real-time multi-task scheduling using buffersChaeseok Im, Soonhoi Ha. 88-94 [doi]
- A trace-based binary compilation framework for energy-aware computingLian Li 0002, Jingling Xue. 95-106 [doi]
- ESys.Net: a new solution for embedded systems modeling and simulationJames Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu, Luc Charest, François R. Boyer, J. P. David, Guy Bois. 107-114 [doi]
- XTREM: a power simulator for the Intel XScale® coreGilberto Contreras, Margaret Martonosi, Jinzhan Peng, Roy Ju, Guei-Yuan Lueh. 115-125 [doi]
- Feedback driven instruction-set extensionUwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies. 126-135 [doi]
- Compositional static instruction cache simulationKaustubh Patil, Kiran Seth, Frank Mueller. 136-145 [doi]
- Measuring the cache interference cost in preemptive real-time systemsJohan Stärner, Lars Asplund. 146-154 [doi]
- Adaptive code unloading for resource-constrained JVMsLingli Zhang, Chandra Krintz. 155-164 [doi]
- Advanced control flow in Java card programmingPeng Li, Steve Zdancewic. 165-174 [doi]
- Generating fast code from concurrent program dependence graphsJia Zeng, Cristian Soviani, Stephen A. Edwards. 175-181 [doi]
- EMBARC: an efficient memory bank assignment algorithm for retargetable compilersJason Hiser, Jack W. Davidson. 182-191 [doi]
- Hardware-managed register allocation for embedded processorsXiaotong Zhuang, Tao Zhang, Santosh Pande. 192-201 [doi]
- A retargetable register allocation framework for embedded processorsJean-Marc Daveau, Thomas Thery, Thierry Lepley, Miguel Santana. 202-210 [doi]
- Link-time optimization of ARM binariesBruno De Bus, Bjorn De Sutter, Ludo Van Put, Dominique Chanet, Koen De Bosschere. 211-220 [doi]
- Optimizing for space and time usage with speculative partial redundancy eliminationBernhard Scholz, R. Nigel Horspool, Jens Knoop. 221-230 [doi]
- Finding effective compilation sequencesL. Almagor, Keith D. Cooper, Alexander Grosul, Timothy J. Harvey, Steven W. Reeves, Devika Subramanian, Linda Torczon, Todd Waterman. 231-239 [doi]
- Code protection for resource-constrained embedded devicesHendra Saputra, Guangyu Chen, Richard R. Brooks, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin. 240-248 [doi]
- Input data reuse in compiling window operations onto reconfigurable hardwareZhi Guo, Betul Buyukkurt, Walid A. Najjar. 249-256 [doi]
- Flattening statecharts without explosionsAndrzej Wasowski. 257-266 [doi]