Koichiro Takayama - researchr alias

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Viewing Publication 1 - 13 from 13

2014

Software Defect Prediction for LSI DesignsMatthieu Parizy, Koichiro Takayama, Yuji Kanazawa. ICSM 2014: 565-568 [doi]

2004

High level hardware validation using hierarchical message sequence chartsPraveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama. hldvt 2004: 167-172 [doi]

2002

Efficient Combinational Verification Using Overlapping Local BDDs and a Hash TableRajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Jacob A. Abraham, Donald S. Fussell, Masahiro Fujita. fmsd, 21(1):95-101, 2002.

Effective safety property checking using simulation-based sequential ATPGShuo Sheng, Koichiro Takayama, Michael S. Hsiao. dac 2002: 813-818 [doi]

2001

A New Functional Test Program Generation MethodologyFarzan Fallah, Koichiro Takayama. iccd 2001: 76-81

A retargetable VLIW compiler framework for DSPs withinstruction-level parallelismSubramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama. tcad, 20(11):1319-1328, 2001. [doi]

2000

Automatic partitioning for efficient combinatorial verificationRajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita. aspdac 2000: 67-72 [doi]

1999

1998

An approach to verify a large scale system-on-a-chip using symbolic model checkingKoichiro Takayama, Taizo Satoh, Tsuneo Nakata, Fumiyasu Hirose. In ICCD. 1998: 308-313 [doi]

1990

A high-speed test-generation method using a test generation circuitFumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato. scjapan, 21(11):12-20, 1990. [doi]

1988

A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic SimulatorFumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato. itc 1988: 102-107

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