Table of Contents

• Managing Quality : Today s Opportunities, Tomorrow s ChallengesA. Blanton Godfrey. 1
• Scan Path and Beyond : The Road to Improved ASIC TestabilityLutz P. Henckels. 2
• Optimal Logic Synthesis and Testability : Two Sides of the Same CoinAlberto L. Sangiovanni-Vincentelli. 3-12
• GaAs Driver and Sensor for a High-Speed Test SystemSheng-Jen Tsai, Charles D. Hechtman. 13-22
• Integrated Pin Electronics for a VLSI Test SystemChristopher W. Branson, Don Murray, Steve Sullivan. 23-27
• Characteristic Impedance and Coupling Coefficients for Multilayer PC BoardsJ. R. Birchak, H. K. Haill. 28-38
• Practical Production Testing of ISDN Circuit BoardsRobert E. McAuliffe. 39-46
• Board-Level Diagnosis by Signature AnalysisMark G. Karpovsky, Prawat Nagvajara. 47-53
• Fault Isolation in Grey SystemsStephen Y. H. Su, Hede Ma. 54-63
• Analysis of Experimental Results on Functional Testing and Diagnosis of Complex CircuitsC. Bellon, Raoul Velazco, Haissam Ziade. 64-72
• Microprocessor Testing by Instruction Sequences Derived from Random PatternsHans Peter Klug. 73-80
• Detection of Control Flow Errors Using Signature and Checking InstructionsJanusz Sosnowski. 81-88
• : A Parallel Algorithm for Fault Simulation on the Connection MachineVinod Narayanan, Vijay Pitchumani. 89-93
• Fault Simulation and Test Pattern Generation at the Multiple-Valued Switch LevelJean Paul Caisso, Bernard Courtois. 94-101
• A Method to Generate Tests for Combinational Logic Circuits Using an Ultra-High-Speed Logic SimulatorFumiyasu Hirose, Koichiro Takayama, Nobuaki Kawato. 102-107
• Key Technologies for 500 MHz VLSI Test System ULTIMATE Teruo Tamama, Naoaki Narumi, Taiichi Otsuji, Masao Suzuki, Tsuneta Sudo. 108-113
• Software Environment for 500 MHz VLSI Test System ULTIMATE T. Adachi, M. Tanno, Tsuneta Sudo. 114-119
• Packaging Technologies for the 500 MHz VLSI Test System ULTIMATE Yoshimitsu Sakagawa, Yusio Akazawa, Naoaki Narumi, Akira Yoshii, Tsuneta Sudo. 120-125
• Testing and Diagnosis of Interconnects Using Boundary Scan ArchitectureAbu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski. 126-137
• Boundary Scan with Cellular-Based Built-In Self-TestClay Gloster, Franc Brglez. 138-145
• Design for Testability for Wafer-Scale Integration Interconnect Systems Design and Test MethodologyMatthias Gruetzner. 146-152
• Testability Features in the TMS370 Family of MicrocomputersTheo J. Powell, Fred Hwang, Bill Johnson. 153-160
• Testability Features of a 32 Kbps ADPCM TranscoderLuis A. Bonet. 161-171
• Design for Testability of a 32-Bit Microprocessor, the TX1Y. Nozuyama, A. Nishimura, J. Iwamura. 172-182
• What is the Path to Fast Fault Simulation?Miron Abramovici, B. Krishnamurthy, A. Mathews, B. Rogers, M. Schulz, S. Seth, John A. Waicukauski. 183-192
• Standardization of ATE Timing Accuracy SpecificationsMarc Mydill. 193-194
• Boundary Scan: The ATE Vendors ViewPhil Collins. 195-196
• Semiconductor Perspective on Test StandardsPete Fleming. 197-198
• Impact of Testability Standards on University Research and InstructionCharles R. Kime. 199-200
• Value of Testability Standards in Testing Commercial ProductsDavid J. Richards. 201-202
• Practice and TheoryEdward J. McCluskey. 203-204
• Digital Testing, Theory and PracticeSamiha Mourad. 205-206
• Do the Designs Work ?Kenneth Rose. 207-208
• Expert System for the Functional Test Program Generation of Digital Electronic Circuit BoardsStephen M. Lea, Nigel Brown, Tim Katz, Phil Collins. 209-220
• Hierarchical Test Generation Using Precomputed Tests for ModulesBrian T. Murray, John P. Hayes. 221-229
• The KARL/KARATE System: Automatic Test Pattern Generation Based on RT Level DescriptionsGerold Affs, Reiner W. Hartenstein, Andrea Wodtko. 230-235
• Multiple Distributions for Biased Random Test PatternsHans-Joachim Wunderlich. 236-244
• Fault Detection Effectiveness of Weighted Random PatternsJohn A. Waicukauski, Eric Lindbloom. 245-255
• WTPGA : A Novel Weighted Test Pattern Generation Approach for VLSI Built-In Self-TestFardad Siavoshi. 256-262
• RTRAM: Reconfigurable and Testable Multi-Bit RAM DesignDhiraj K. Pradhan, Nirmala R. Kamath. 263-278
• An On-Chip Double-Bit Error-Correcting Code for Three-Dimensional Dynamic Random-Access MemoryPinaki Mazumder. 279-288
• Application of a Commercial Data Base Management System to Memory Device Test Program Generation and DebuggingSteve Grennan. 289-294
• IC Quality and Test TransparencyEdward J. McCluskey, Fred Buelow. 295-301
• Design for Test and the Cost of QualityChris Salzmann, Martin Funcell, Richard Taylor. 302-307
• Elimination of Incoming Test Based Upon In-Process Failure and Repair CostsW. David Ballew, Lauren M. Streb. 308-313
• On Multiple Fault Coverage and Aliasing Probability MeasuresHenry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski. 314-321
• Identification of Failing Tests with Cycling RegistersJacob Savir, William H. McAnney. 322-328
• A New Framework for Designing and Analyzing BIST Techniques: Computation of Exact Aliasing ProbabilitySandeep K. Gupta, Dhiraj K. Pradhan. 329-342
• Fault Modeling and Test Algorithm DevelopmentFrans P. M. Beenker, Rob Dekker, Loek Thijssen. 343-352
• A Realistic Self-Test Machine for Static Random Access MemoriesFrans P. M. Beenker, Rob Dekker, Loek Thijssen. 353-361
• Dual Port Static RAM TestingManuel J. Raposa. 362-368
• Reliability Testing by Precise Electrical MeasurementA. P. Dorey, B. K. Jones, Andrew M. D. Richardson, P. C. Russell, Y. Z. Xu. 369-373
• Fault Detection of Combinational Circuits Based on Supply CurrentMasaki Hashizume, Takeomi Tamesada, Kazuhiro Yamada, Masaaki Kawakami. 374-380
• An Advanced Data Compaction Approach for Test During Burn-InBirger Schneider, Peter Oestergaard. 381-390
• In-Circuit Test FixtureCharles D. Hechtman. 391-400
• New Testing Equipment for SMT PC BoardsLuis Balme, Anne Mignotte, Jean-Yves Monari, Patrick Pondaven, Christophe Vaucher. 401-410
• Evaluating the Limitations of High-Speed Board TestersJohn Arena. 411-420
• : Test Scheduling for High Performance VLSI System ImplementationsJohn Y. Sayah, Charles R. Kime. 421-430
• Concurrent Control of Multiple BIT StructuresSandeep K. Gupta, Melvin A. Breuer, Jung-Cheun Lien. 431-442
• Optimal Scheduling of Signature Analysis for VLSI TestingC. Mani Krishna, Yann-Hang Lee. 443-451
• A High Level Approach to Integrating Design and TestJohn Ivie. 452-459
• Optimal Use of Timing Resources: A Crucial Step in Test Program GenerationJi-en Morris Chang, William T. Krakow. 460-465
• A Strategy for Generating Functional Tests from Device SimulationsCristopher Merritt. 466-474
• Extraction and Simulation of Realistic CMOS Faults Using Inductive Fault AnalysisJohn Paul Shen, F. Joel Ferguson. 475-484
• Dynamic Techniques for Yield Enhancement of Field Programmable Logic ArraysMichael Demjanenko, Shambhu J. Upadhyaya. 485-491
• Statistical Delay Fault Coverage and Defect Level for Delay FaultsEun Sei Park, Thomas W. Williams, M. Ray Mercer. 492-499
• Contactors for Testing at High FrequenciesBernd Reichelmann. 500-501
• A Test and Maintenance Controller for a Module Containing Testable ChipsMelvin A. Breuer, Jung-Cheun Lien. 502-513
• A BIST Design of Structured Arrays with Fault-Tolerant LayoutMehdi Katoozi, Mani Soma. 514-521
• Reconfigurable Hardware for Pseudo-Exhaustive TestJon G. Udeli Jr.. 522-530
• Evaluation of System BIST Using Computational Performance MeasuresDavid L. Landis, Daniel C. Muha. 531-536
• Some New Techniques in Waveshape Capture and AnalysisArthur E. Downey, Kazuhiko Matsuda. 537-546
• A High-Resolution Waveform Analysis ToolPatrick M. Powers. 547-550
• Functional Test Program Generation Through interactive GraphicsCihan Tinaztepe, Bülent Özgüç. 551-558
• PGTOOL: An Automatic Interactive Program Generation Tool for Testing New-Generation Memory DevicesYuichi Kawabata, Masami Maruyama, Al Tejeda. 559-568
• Fault Bundling: Reducing Machine Evaluation Activity in Hierarchical Concurrent Fault SimulationWilliam H. Nicholls, Mani Soma. 569-573
• Switch-Level Concurrent Fault Simulation Based on a General Purpose List Traversal MechanismDeborah Machlin, David Gross, Sudhir Kadkade, Ernst Ulrich. 574-581
• D^3FS: A Demand Driven Deductive Fault SimulatorSteven P. Smith, Bill Underwood, M. Ray Mercer. 582-592
• On Behavior Fault Modeling for Combinational Digital DesignsTapan J. Chakraborty, Sumit Ghosh. 593-600
• Membrane Probe Card Technology (the Future for High Performance Wafer Test)Brian Leslie, Farid Matta. 601-607
• Very High Density ProbingC. Barsotti, S. Tremaine, M. Bonham. 608-614
• New Automated Prober Support for High Pincount Test HeadsT. Roland Fredriksen, David Grano. 615-620
• Synthesis and Optimization Procedures for Fully and Easily Testable Sequential MachinesSrinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli. 621-630
• A Knowledge Representation Scheme for DFTDesmond F. D Souza. 631-641
• Enhancing Random-Pattern Coverage of Programmable Logic Arrays via Masking TechniqueHideo Fujiwara, Osamu Fujisawa, Kazunori Hikone. 642-648
• Managing the ASIC Design to Test ProcessGary D. Culbertson. 649-656
• Built-In Test Compiler in an ASIC EnvironmentEric Archambeau, Ken Van Egmond. 657-664
• An Expert Test Program Generation System for Per-Pin TestersA. Walter, Y. Kleinman, L. Edelshteyn, J. Gartner. 665-668
• On the Testing of MultiplexersSamy Makar, Edward J. McCluskey. 669-679
• Robust Tests for Parity TreesSandip Kundu, Sudhakar M. Reddy. 680-687
• Stuck-Open and Transition Fault Testing in CMOS Complex GatesHenry Cox, Janusz Rajski. 688-694
• Optical Testing of Printed Circuit BoardsG. Tremblay, P. Meyrueix, J. C. Peuzin. 695-699
• Test Head Design Using Electro-Optic Receivers and GaAs Pin Electronics for a Gigahertz Production Test SystemFrancois J. Henley, Hee-June Choi. 700-709
• High-Speed Pattern Generator and GaAs Pin : Electronics for a Gigahertz Production Test SystemDean J. Kratzer, Steve Barton, Francois J. Henley, David A. Plomgrem. 710-718
• Circular BIST with Partial ScanM. M. Pradhan, E. J. O Brien, S. L. Lam, James Beausang. 719-729
• An Incomplete Scan Design Approach to Test Generation for Sequential MachinesHi-Keung Tony Ma, A. Richard Newton, Srinivas Devadas, Alberto L. Sangiovanni-Vincentelli. 730-734
• Threading of Multiple Scan Paths in a VLSI CircuitS. Bhawmick, M. S. Khaira, P. P. Mishra, A. Das, A. Dasgupta, P. Palchaudhury. 735-743
• Integrated Test Logic for Video ICsJohn Beck, James Pappas, Robert Rose, Larry Seiler. 744-751
• Flexible Deep Memory Architecture Aids Program DevelopmentJohn L. Russo. 752-754
• Timing Generation for DSP TestingEric Rosenfeld. 755-763
• G-RIDDLE : A Formal Analysis of Logic Designs Condiucive to the Acceleration of BacktracingGabriel M. Silberman, Ilan Y. Spillinger. 764-772
• Detecting Bridging Faults with Stuck-at Test SetsSteven D. Millman, Edward J. McCluskey. 773-783
• An Algorithmic Branch and Bound Method for PLA Test Pattern GenerationMarkus Robinson, Janusz Rajski. 784-795
• Trouble-Shooting: A Key to Process ImprovementChi W. Yau, Song-Lin Chang, Bruce F. Jordan, Joe J. Schwermann, Joan A. Wellman. 796-803
• Predicting and Obtaining High Final Test YieldsRaymond J. Balzer, Greg A. Larsen. 804-815
• CIM , Electronics Manufacturing and ATENeil Hutchinson. 816-822
• Design for Testability of Mixed Signal Integrated CircuitsKenneth D. Wagner, Thomas W. Williams. 823-828
• TASTE: A Tool for Analog System Testability EvaluationGertjan J. Hemink, Berend W. Meijer, Hans G. Kerkhoff. 829-838
• DC_IATP : An Iterative Analog Circuit Test Generation Program for Generating DC Single Pattern TestsM. J. Marlett, Jacob A. Abraham. 839-844
• On the Detection of Delay FaultsAnkan K. Pramanick, Sudhakar M. Reddy. 845-856
• Delay Test Generation 1: Concepts and Coverage MetricsVijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger. 857-866
• Delay Test Generation 2: Algebra and AlgorithmsVijay S. Iyengar, Barry K. Rosen, Ilan Y. Spillinger. 867-876
• Experiences with Concurrent Fault Simulation of Diagnostic ProgramsStephen R. Demba, Ernst Ulrich, Karen Panetta, David Giramma. 877-883
• System Level Fault Dictionary GenerationHidetoshi Tanaka, Masato Kawai, Izumi Sugasaki, Tadanobu Hakuba. 884-887
• Designs for Diagnosability and Reliability in VLSI SystemsStephen Y. H. Su, Hede Ma. 888-897
• Automatic Location of IC Design Errors Using Beam SystemM. Melgara, M. Battu, P. Garino, J. Dowe, Y. J. Vernay, M. Marzouki, F. Boland. 898-907
• Electron Beam Tester Integrated into a VLSI TesterHironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum. 908-913
• Continuous Signature Monitoring: Efficient Concurrent-Detection of Processor Control ErrorsKent D. Wilken, John Paul Shen. 914-925
• Error Detection with Latency in Sequential CircuitsLawrence P. Holmquist, Larry L. Kinney. 926-933
• Concurrent Off-Phase Built-in Self-Test of Dormant LogicLeon J. Sigal, Charles R. Kime. 934-941
• Techniques for User Testing of the 68882Mark Marshall. 942-947
• Simultaneous Switching Noise Evaluation of Advanced CMOS Logic (ACL)Kenneth R. Stuchlik. 948-957
• Emulative Testing at the Bus Speed LimitDouglas B. Arnett, K. S. Bhaskar. 958-968
• Built-In Test Strategy for Next Generation Military Avionic HardwareDonald H. Merliho, John Hadjilogiou. 969-975
• Using Scan Technology for Debug and Diagnostics in a Workstation EnvironmentBulent I. Dervisoglu. 976-986
• Scan Diagnostic Strategy for the Series 10000 Prism WorkstationMike Ricchetti, John Hoglund. 987-992
• CAD Tools for Supporting System Design for TestabilityJill J. Hallenbeck, Nick Kanopoulos, Nagesh Vasanthavada, James W. Watterson. 993
• Testability Using Random Access Test RegisterCuong Bui. 994-995
• Designing State Machines for TestabilityMichael Treseler. 996
• On Benchmarking Digital Testing SystemsSamiha Mourad, Edward J. McCluskey. 997
• The Non-Linear Feedback Shift-Register as a Built-In Self-Test (BIST) ResourcePeter N. Marinos. 998
• Detection of Hard Faults in a Combinational Circuit Using Budget ConstraintsDavid Stannard, Bozena Kaminska. 999
• Partial Hardware Partitioning: A New Pseudo-Exhaustive Test ImplementationJon G. Udeli Jr., Edward J. McCluskey. 1000
• Defining a Standard for Fault Simulator EvaluationSami A. Al-Arian, Kevin A. Kwiat. 1001
• Determination of Safe Back-Driving Currents in Bond Wires and DiceG. J. Hill, B. C. Roberts, C. P. Strudwick. 1002