Bill Underwood - researchr alias

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Viewing Publication 1 - 11 from 11

2003

Speed Binning with Path Delay Test in 150-nm TechnologyBruce D. Cory, Rohit Kapur, Bill Underwood. dt, 20(5):41-45, 2003. [doi]

1994

Path-Delay Fault Simulation for a Standard Scan Design MethodologySungho Kang, Wai-On Law, Bill Underwood. iccd 1994: 359-362

Fastpath: A Path-Delay Test Generator for Standard Scan DesignsBill Underwood, Wai-On Law, Sungho Kang, Haluk Konuk. itc 1994: 154-163

1991

Delay Testing Quality in Timing-Optimized DesignsEun Sei Park, Bill Underwood, Thomas W. Williams, M. Ray Mercer. itc 1991: 897-905

The Interdependence Between Delay-Optimization of Synthesized Networks and TestingThomas W. Williams, Bill Underwood, M. Ray Mercer. dac 1991: 87-92 [doi]

1989

The Parallel-Test-Detect Fault Simulation AlgorithmBill Underwood, Jack Ferguson. itc 1989: 712-717

1988

An Analysis of Parallel Logic Simulation on Several ArchitecturesSteven P. Smith, Bill Underwood, Joe Newman. icpp 1988: 65-68

D^3FS: A Demand Driven Deductive Fault SimulatorSteven P. Smith, Bill Underwood, M. Ray Mercer. itc 1988: 582-592

1986

Calculation of Greatest Lower Bounds Obtainable by the Cutting AlgorithmRhonda Kay Gaede, M. Ray Mercer, Bill Underwood. itc 1986: 498-505

1985

Built-In Self Test Input Generator for Programmable Logic ArraysJohn Salick, Bill Underwood, M. Ray Mercer. itc 1985: 115-125

1984

Correlating Testability with Fault DetectionBill Underwood, M. Ray Mercer. itc 1984: 697-704

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