Abstract is missing.
- Reuse of IP and virtual componentsRalf Seepold. [doi]
- Higher Product Complexity and Shorter Development Time - Continuous Challenge to Design and Test EnvironmentJouko Junkkari. 2-3 [doi]
- Automotive Electronics - A Challenge For Systems EngineeringPeter Thoma. 4 [doi]
- Testing in Nanometer TechnologiesT. W. Williams. 5 [doi]
- Computing Timed Transition Relations for Sequential Cycle-Based SimulationGianpiero Cabodi, Paolo Camurati, Claudio Passerone, Stefano Quer. 8-12 [doi]
- Symbolic Reachability Analysis of Large Finite State Machines Using Don t CaresYoupyo Hong, Peter A. Beerel. 13 [doi]
- FSMD Functional Partitioning for Low PowerEnoch Hwang, Frank Vahid, Yu-Chin Hsu. 22-27 [doi]
- A New Parameterizable Power Macro-Model for Datapath ComponentsGerd Jochens, Lars Kruse, Eike Schmidt, Wolfgang Nebel. 29 [doi]
- An Efficient Reuse System for Digital Circuit DesignAnnette Reutter, Wolfgang Rosenstiel. 38-43 [doi]
- An MPEG-2 Video Encoder LSI with Scalability for HDTV based on Three-layer Cooperative ArchitectureMitsuo Ikeda, Toshio Kondo, Koyo Nitta, Kazuhito Suguri, Takeshi Yoshitome, Toshihiro Minami, Jiro Naganuma, Takeshi Ogura. 44 [doi]
- Formal Verification of Word-Level SpecificationsStefan Höreth, Rolf Drechsler. 52-57 [doi]
- Automatic Verification of Scheduling Results in High-Level SynthesisHans Eveking, Holger Hinrichsen, Gerd Ritter. 59-64 [doi]
- Verifying Imprecisely Working Arithmetic CircuitsMichaela Huhn, Klaus Schneider, Thomas Kropf, George Logothetis. 65 [doi]
- Battery-Powered Digital CMOS DesignMassoud Pedram, Qing Wu. 72-76 [doi]
- Dynamic Power Management for non-stationary service requestsEui-Young Chung, Luca Benini, Alessandro Bogliolo, Giovanni De Micheli. 77-81 [doi]
- On Reducing Transitions Through Data ModificationsRajeev Murgai, Masahiro Fujita. 82 [doi]
- Kernel Scheduling in Reconfigurable ComputingRafael Maestre, Fadi J. Kurdahi, Nader Bagherzadeh, Hartej Singh, Román Hermida, Milagros Fernández. 90-96 [doi]
- CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded SystemsBharat P. Dav. 97-104 [doi]
- Exploiting Conditional Instructions in Code Generation for Embedded VLIW ProcessorsRainer Leupers. 105 [doi]
- Path Delay Fault Testing of ICs with Embedded Intellectual Property BlocksDimitris Nikolos, Haridimos T. Vergos, Th. Haniotakis, Y. Tsiatouhas. 112-116 [doi]
- An Effective BIST Architecture for Fast Multiplier CoresAntonis M. Paschalis, Nektarios Kranitis, Mihalis Psarakis, Dimitris Gizopoulos, Yervant Zorian. 117-121 [doi]
- A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue CodesIssam Alzaher-Noufal, Michael Nicolaidis. 122 [doi]
- An Efficient Filter-Based Approach for Combinational VerificationRajarshi Mukherjee, Jawahar Jain, Koichiro Takayama, Masahiro Fujita, Jacob A. Abraham, Donald S. Fussell. 132-137 [doi]
- Using Combinational Verification for Sequential CircuitsRajeev K. Ranjan, Vigyan Singhal, Fabio Somenzi, Robert K. Brayton. 138-144 [doi]
- Combinational Equivalence Checking Using Satisfiability and Recursive LearningJoão P. Marques Silva, Thomas Glass. 145-149 [doi]
- Formally Verified Redundancy RemovalStefan Hendricx, Luc J. M. Claesen. 150 [doi]
- Logic Transformation for Low Power SynthesisKi-Wook Kim, Sung-Mo Kang, TingTing Hwang, C. L. Liu. 158-162 [doi]
- Glitch Power Minimization by Gate FreezingLuca Benini, Giovanni De Micheli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi. 163-167 [doi]
- Spanning Tree-based State Encoding for Low Power DissipationWinfried Nöth, Reiner Kolla. 168-174 [doi]
- Peak Power Estimation Using Genetic Spot Optimization for Large VLSI CircuitsMichael S. Hsiao. 175 [doi]
- A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive TesterÉrika F. Cota, Luigi Carro, Marcelo Lubaszewski. 184-188 [doi]
- Minimal Length Diagnostic Tests for Analog Circuits using Test HistoryAlfred V. Gomes, Abhijit Chatterjee. 189-194 [doi]
- Parametric Fault Diagnosis for Analog Systems Using Functional MappingSasikumar Cherubal, Abhijit Chatterjee. 195 [doi]
- Temporal Partitioning combined with Design Space Exploration for Latency Minimization of Run-Time Reconfigured DesignsMeenakshi Kaul, Ranga Vemuri. 202-209 [doi]
- Time Constrained Modulo Scheduling with Global Resource SharingChristoph Jäschke, Rainer Laur, Friedrich Beckmann. 210-216 [doi]
- Polynomial Methods for Allocating Complex ComponentsJames Smith, Giovanni De Micheli. 217-222 [doi]
- Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL DesignsNazanin Mansouri, Ranga Vemuri. 223 [doi]
- A Digital Partial Built-In Self-Test for a High Performance Automatic Gain Control Circuit A. Lechner, J. Ferguson, Andrew Richardson, B. Hermes. 232-238 [doi]
- Design, Characterization & Modelling of a CMOS Magnetic Field SensorLaurent Latorre, Yves Bertrand, P. Hazard, F. Pressecq, Pascal Nouet. 239-243 [doi]
- Fast, Robust DC and Transient Fault Simulation for Nonlinear Analog CircuitsZheng Rong Yang, Mark Zwolinski. 244-248 [doi]
- On Analog Signature AnalysisFranc Novak, Bojan Hvala, Sandi Klavzar. 249 [doi]
- The Rugby Model: A Conceptual Frame for the Study of Modelling, Analysis and Synthesis Concepts of Electronic SystemsAxel Jantsch, Shashi Kumar, Ahmed Hemani. 256-262 [doi]
- MOCSYN: Multiobjective Core-Based Single-Chip System SynthesisRobert P. Dick, Niraj K. Jha. 263-270 [doi]
- A Methodology and Design Environment for DSP ASIC Fixed-Point RefinementRadim Cmar, Luc Rijnders, Patrick Schaumont, Serge Vernalde, Ivo Bolsens. 271 [doi]
- Synthesis of Controllers for Full Testability of Integrated Datapath-Controller PairsJoan Carletta, Mehrdad Nourani, Christos A. Papachristou. 278-282 [doi]
- Channel-Based Behavioral Test Synthesis for Improved Module ReachabilityYiorgos Makris, Alex Orailoglu. 283-288 [doi]
- Efficient BIST Hardware Insertion with Low Test Application Time for Synthesized Data PathsNicola Nicolici, Bashir M. Al-Hashimi. 289 [doi]
- High-speed Software-based Platform for Embedded Software of a Single-chip MPEG-2 Video Encoder LSI with HDTV ScalabilitKatsuyuki Ochiai, Hiroe Iwasaki, Jiro Naganuma, Makoto Endo, Takeshi Ogura. 303-308 [doi]
- Fast Hardware-Software Co-simulation Using VHDL ModelsBassam Tabbara, Marco Sgroi, Alberto L. Sangiovanni-Vincentelli, Enrica Filippi, Luciano Lavagno. 309 [doi]
- Systematic Biasing of Negative Feedback AmplifiersChris J. M. Verhoeven, Arie van Staveren. 318-322 [doi]
- Automating the Sizing of Analog CMOS Circuits by Consideration of Structural ConstraintsRobert Schwencker, Josef Eckmueller, Helmut E. Graeb, Kurt Antreich. 323-327 [doi]
- Hierarchical Constraint Transformation Using Directed Interval Search for Analog System SynthesisNagu R. Dhanwada, Adrián Núñez-Aldana, Ranga Vemuri. 328 [doi]
- A VHDL-AMS Compiler and Architecture Generator for Behavioral Synthesis of Analog SystemsAlex Doboli, Ranga Vemuri. 338-345 [doi]
- Reasoning about VHDL and VHDL-AMS using Denotational SemanticsPeter T. Breuer, Natividad Martínez Madrid, Jonathan P. Bowen, Robert B. France, María M. Larrondo-Petrie, Carlos Delgado Kloos. 346-352 [doi]
- A Formal Semantics for Verilog-VHDL Simulation Interoperability by Abstact State MachineHisashi Sasaki. 353 [doi]
- Design For Testability Method for CML Digital CircuitsBernard Antaki, Yvon Savaria, Nanhan Xiong, Saman Adham. 360-367 [doi]
- On the Design of Self-Checking Functional Units Based on Shannon CircuitsMichele Favalli, Cecilia Metra. 368-375 [doi]
- Parametric Built-In Self-Test of VLSI SystemsDirk Niggemeyer, M. Rüffer. 376 [doi]
- Hardware Synthesis from C/C++ ModelsGiovanni De Micheli. 382-383 [doi]
- C for System Level DesignGuido Arnout. 384-386 [doi]
- Hardware Synthesis from C/C++Abhijit Ghosh, Joachim Kunkel, Stan Y. Liao. 387-389 [doi]
- C-based Synthesis Experiences with a Behavior Synthesizer, Cyber Kazutoshi Wakabayashi. 390 [doi]
- Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC sJoao Paulo Costa, L. Miguel Silveira, Mike Chou. 396-400 [doi]
- A Power Estimation Model for High-Speed CMOS A/D ConvertersErik Lauwers, Georges G. E. Gielen. 401-405 [doi]
- An Analog Performance Estimator for Improving the Effectiveness of CMOS Analog Systems Circuit SynthesisAdrián Núñez-Aldana, Ranga Vemuri. 406-411 [doi]
- An Accurate Error Control Mechanism for Simplification Before Generation AlgorihmsOscar Guerra, J. D. Rodríguez-García, Elisenda Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez. 412 [doi]
- Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package ParasiticsPeter Feldmann, Sharad Kapur, David E. Long. 418-417 [doi]
- Potentials of Chip-Package Co-Design for High-Speed Digital ApplicationsGerhard Tröster. 423-422 [doi]
- A Single-Package Solution for Wireless TransceiversPiet Wambacq, Stéphane Donnay, Hocine Ziad, Marc Engels, Hugo De Man, Ivo Bolsens. 425 [doi]
- Scaling Deeper to Submicron: On-Line Testing to the RescueMichael Nicolaidis, Yervant Zorian. 432 [doi]
- Functional Verification Methodology for Microprocessors Using the Genesys Test-Program Generator-Application to the x86 Microprocessors FamilyLaurent Fournier, Yaron Arbetman, Moshe Levinger. 434-441 [doi]
- Symbolic Functional Vector Generation for VHDL SpecificationsFabrizio Ferrandi, Franco Fummi, Luca Gerli, Donatella Sciuto. 442 [doi]
- Interpretable Symbolic Small-Signal Characterization of Large Analog Circuits using Determinant Decision DiagramsXiang-Dong Tan, C.-J. Richard Shi. 448-453 [doi]
- Cycle-based Simulation with Decision DiagramsRaimund Ubar, Jaan Raik, Adam Morawiec. 454-458 [doi]
- Efficient Switching Activity Simulation under a Real Delay Model Using a Bitparallel ApproachMarkus Bühler, Matthias Papesch, K. Kapp, Utz G. Baitinger. 459 [doi]
- Full Scan Fault Coverage With Partial ScanXijiang Lin, Irith Pomeranz, Sudhakar M. Reddy. 468-472 [doi]
- At-Speed Boundary-Scan Interconnect Testing in a Board with Multiple System ClocksJongchul Shin, Hyunjin Kim, Sungho Kang. 473 [doi]
- OpenJ: An Extensible System Level Design LanguageJianwen Zhu, Daniel Gajski. 480-484 [doi]
- EXPRESSION: A Language for Architecture Exploration through Compiler/Simulator RetargetabilityAshok Halambi, Peter Grun, Vijay Ganesh, Asheesh Khare, Nikil D. Dutt, Alexandru Nicolau. 485-490 [doi]
- Data Type Analysis for Hardware Synthesis from Object-Oriented ModelsMartin Radetzki, Ansgar Stammermann, Wolfram Putzke-Röming, Wolfgang Nebel. 491 [doi]
- How to use Knowledge in an Analysis ProcessHeiko Holzheuer. 498-502 [doi]
- Digital MOS Circuit Partitioning with Symbolic ModelingLluis Ribas, Jordi Carrabina. 503-508 [doi]
- High Speed GaAs Subsystem Design using Feed Through LogicJuan A. Montiel-Nelson, Saeid Nooshabadi, V. de Armas, Roberto Sarmiento, Antonio Núñez. 509 [doi]
- Integrating Symbolic Techniques in ATPG-Based Sequential Logic OptimizationEnrique San Millán, Luis Entrena, José Alberto Espejo, Silvia Chiusano, Fulvio Corno. 516-520 [doi]
- An Algorithm for Face-Constrained Encoding of Symbols Using Minimum Code LengthManuel Martínez, Maria J. Avedillo, José M. Quintana, José L. Huertas. 521-525 [doi]
- Algorithms for Solving Boolean Satisfiability in Combinational CircuitsLuís Guerra e Silva, Luis Miguel Silveira, João P. Marques Silva. 526-530 [doi]
- Wavefront Technology MappingLeon Stok, Andrew J. Sullivan, Mahesh A. Iyer. 531 [doi]
- On-Chip Transient Current Monitor for Testing of Low Voltage CMOS ICViera Stopjaková, Hans A. R. Manhaeve, M. Sidiropulos. 538-542 [doi]
- Exploring the Combination of IDDQ and iDDt Testing: Energy TestingJosep Rius, Joan Figueras. 543-548 [doi]
- Defect-Oriented Mixed-Level Fault Simulation of Digital Systems-on-a-Chip Using HDLMarcelino B. Santos, João Paulo Teixeira. 549 [doi]
- Combining Software Synthesis and Hardware/Software Interface Generation to Meet Hard Real-Time ConstraintsSteven Vercauteren, Jan van der Steen, Diederik Verkest. 556-561 [doi]
- Operating System Sensitive Device Driver Synthesis from Implementation Independent Protocol SpecificationMattias O Nils, Axel Jantsch. 562-567 [doi]
- Codex-dp: Co-design of Communicating Systems Using Dynamic ProgrammingJui-Ming Chang, Massoud Pedram. 568 [doi]
- Efficient 3D Modelling for Extraction of Interconnect Capacitances in Deep Submicron Dense LayoutsA. Toulouse, David Bernard, Christian Landrault, Pascal Nouet. 576-580 [doi]
- Post-Placement Residual-Overlap Removal with Minimal MovementSudip Nag, Kamal Chaudhary. 581-586 [doi]
- Iterative Improvement Based Multi-Way Netlist Partitioning for FPGAsHelena Krupnova, Gabriele Saucier. 587 [doi]
- Self Recovering Controller and Datapath CodesignSamuel Norman Hamilton, Alex Orailoglu, Andre Hertwig. 596-601 [doi]
- Identification and Exploitation of Symmetries in DSP AlgorithmsC. A. J. van Eijk, E. T. A. F. Jacobs, Bart Mesman, Adwin H. Timmer. 602-608 [doi]
- Exploiting State Equivalence on the Fly while Applying Code Motion and SpeculationLuiz C. V. dos Santos, Jochen A. G. Jess. 609 [doi]
- Single Chip or Hybrid System IntegrationIvo Bolsens, Wojtek Maly, Ludo Deferm, Jo Borel, Harry J. M. Veendrick. 616 [doi]
- Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA sMichel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian. 618-622 [doi]
- Industrial Evaluation of DRAM TestsA. J. van de Goor, J. de Neef. 623-630 [doi]
- ATPG Tools for Delay Faults at the Functional LevelSpyros Tragoudas, Maria K. Michael. 631 [doi]
- Performance Driven Resynthesis by Exploiting Retiming-Induced State Register EquivalencePriyank Kalla, Maciej J. Ciesielski. 638-642 [doi]
- Minimizing Sensitivity to Delay Variations in High-Performance Synchronous CircuitsXun Liu, Marios C. Papaefthymiou, Eby G. Friedman. 643-649 [doi]
- Retiming Sequential Circuits with Multiple Register ClassesKlaus Eckl, Christian Legl. 650 [doi]
- Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital DesignsLun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano. 658-663 [doi]
- Coupled Noise Estimation for Distributed RC Interconnect ModelJanet Meiling Wang, Qingjian Yu, Ernest S. Kuh. 664-668 [doi]
- Projective Convolution: RLC Model-Order Reduction Using the Impulse ResponseBernard N. Sheehan. 669 [doi]
- The Design Space Layer: Supporting Early Design Space Exploration for Core-Based DesignsMargarida F. Jacome, Helvio P. Peixoto, Ander Royo, Juan Carlos López. 676-683 [doi]
- Specification and Validation of Distributed IP-Based Designs with JavaCADMarcello Dalpasso, Alessandro Bogliolo, Luca Benini. 684-688 [doi]
- Object-Oriented Reuse Methodology for VHDLCristina Barna, Wolfgang Rosenstiel. 689 [doi]
- Multi-Language System DesignAhmed Amine Jerraya, Rolf Ernst. 696 [doi]
- Symmetric Transparent BIST for RAMsSybille Hellebrand, Hans-Joachim Wunderlich, Vyacheslav N. Yarmolik. 702-707 [doi]
- On Programmable Memory Built-In Self Test ArchitecturesKamran Zarrineh, Shambhu J. Upadhyaya. 708-713 [doi]
- A Physical Design Tool for Built-in Self-Repairable Static RAMsKanad Chakraborty, Anurag Gupta, Mayukh Bhattacharya, Shriram Kulkarni, Pinaki Mazumder. 714 [doi]
- Java, VHDL-AMS, ADA or C for System Level Specifications?720 [doi]
- Case Study: System Model of Crane and Embedded ControlEduard Moser, Wolfgang Nebel. 721 [doi]
- Virtual Components Application and CustomizationJean-François Agaësse, Bernard Laurent. 726-727 [doi]
- Design Methodology for IP ProvidersJürgen Haase. 728 [doi]
- Large European Programs in Microelectronic System and Circuit DesignPatrick Dewilde. 734 [doi]
- Sequential Circuit Test Generation Using Decision Diagram ModelsJaan Raik, Raimund Ubar. 736-740 [doi]
- Illegal State Space Identification for Sequential Circuit Test GenerationM. H. Konijnenburg, J. Th. van der Linden, A. J. van de Goor. 741-746 [doi]
- FreezeFrame: Compact Test Generation Using a Frozen Clock StrategyYanti Santoso, Matthew C. Merten, Elizabeth M. Rudnick, Miron Abramovici. 747 [doi]
- Approximate Equivalence Verification of Sequential Circuits via Genetic AlgorithmsFulvio Corno, Matteo Sonza Reorda, Giovanni Squillero. 754-755 [doi]
- Interval Diagram Techniques for Symbolic Model Checking of Petri NetsKarsten Strehl, Lothar Thiele. 756-757 [doi]
- Variable Reordering for Shared Binary Decision Diagrams Using Output ProbabilitiesMitchell A. Thornton, J. P. Williams, Rolf Drechsler, Nicole Drechsler. 758-759 [doi]
- Increasing Efficiency of Symbolic Model Checking by Accelerating Dynamic Variable ReorderingChristoph Meinel, Christian Stangier. 760-761 [doi]
- Influence of Caching and Encoding on Power Dissipation of System-Level Buses for Embedded SystemsWilliam Fornaciari, Donatella Sciuto, Cristina Silvano. 762-763 [doi]
- Emulation of a Fast Reactive Embedded System using a Real Time Operating SystemKarlheinz Weiß, Thorsten Steckstor, Wolfgang Rosenstiel. 764-765 [doi]
- The Heterogeneous Structure Problem in Hardware/Software Codesign: A Macroscopic ApproachJ. A. Maestro, Daniel Mozos, Román Hermida. 766-767 [doi]
- Codesign of Embedded Systems Based on Java and Reconfigurable Hardware ComponentsJosef Fleischmann, Klaus Buchenrieder, Rainer Kress. 768-769 [doi]
- ADOLT - An ADaptable On - Line Testing Scheme for VLSI CircuitsA. Maamar, G. Russell. 770-771 [doi]
- Integrated Resource Assignment and Scheduling of Task Graphs Using Finite Domain ConstraintsKrzysztof Kuchcinski. 772-773 [doi]
- A Method of Distributed Controller Design for RTL CircuitsChristos A. Papachristou, Yusuf Alzazeri. 774-775 [doi]
- OTA Amplifiers Design on Digital Sea-of-Transistors ArrayJung Hyun Choi, Sergio Bampi. 776-777 [doi]
- A DAG-Based Design Approach for Reconfigurable VLIW ProcessorsCesare Alippi, William Fornaciari, Laura Pozzi, Mariagiovanna Sami. 778-779 [doi]
- A Fault List Reduction Approach for Efficient Bridge Fault DiagnosisJue Wu, Gary S. Greenstein, Elizabeth M. Rudnick. 780-781 [doi]
- An Object-Based Executable Model for Simulation of Real-Time Hw/Sw SystemsOlivier Pasquier, Jean Paul Calvez. 782-783 [doi]
- An Efficient and Flexible Methodology for Modelling and Simulation of Heterogeneous Mechatronic SystemsStefan Scherber, Christian Müller-Schloer. 784-785 [doi]
- Software Bit-Slicing: A Technique for Improving Simulation PerformancePeter M. Maurer, William J. Schilp. 786-787 [doi]
- Interoperability of Verilog/VHDL Procedural Language Interfaces to Build a Mixed Language GUIFrançoise Martinolle, Charles Dawson, Debra Corlette, Mike Floyd. 788-789 [doi]
- Experiences with Modeling of Analog and Mixed A/D Systems Based on PWL TechniqueJerzy Dabrowski, Andrzej Pulka. 790-791 [doi]
- A One-Bit-Signature BIST for Embedded Operational Amplifiers in Mixed-Signal Circuits Based on the Slew-Rate DetectionIyad Rayane, Jaime Velasco-Medina, Michael Nicolaidis. 792 [doi]