Rakesh Chadha - researchr alias

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Viewing Publication 1 - 7 from 7

1999

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital DesignsLun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano. date 1999: 658-663 [doi]

1992

M:::3:::-a multilevel mixed-mode mixed A/D simulatorRakesh Chadha, Chandramouli Visweswariah, Chin-Fu Chen. tcad, 11(5):575-585, 1992. [doi]

Switched-capacitor simulation models for full-chips verificationTom Chanak, Rakesh Chadha, Kishore Singhal. tcad, 11(11):1363-1371, 1992. [doi]

1988

M/sup 3/-a multilevel mixed-mode mixed D/A simulatorRakesh Chadha, Chin-Fu Chen. iccad 1988: 258-261 [doi]

Extension of a transistor level digital timing simulator to include first order analog behaviorRakesh Chadha, Chin-Fu Chen. iccd 1988: 116-119 [doi]

Model Development and Verification for High Level Analog BlocksChandramouli Visweswariah, Rakesh Chadha, Chin-Fu Chen. dac 1988: 376-382 [doi]

1987

WATOPT -- An Optimizer for Circuit ApplicationsRakesh Chadha, Kishore Singhal, Jiri Vlach, Ernst Christen, Milan Vlach. tcad, 6(3):472-479, 1987. [doi]

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