Table of Contents

• A parallel simulated annealing algorithm for channel routing on a hypercube multiprocessorRandall J. Brouwer, Prithviraj Banerjee. 4-7 [doi]
• Object relocation in OXJames H. Kukula. 8-10 [doi]
• Test generation in a parallel processing environmentSusheel J. Chandra, Janak H. Patel. 11-14 [doi]
• Super computer technology at ConvexHarold Dozier, Jeff Gruger. 16-20 [doi]
• The Cray Y-MP-a VLSI supercomputerS. Bowen. 21-23 [doi]
• The design of a reduced ambient temperature, air cooled supercomputerDonald R. Mullen, Geoffrey Fernald. 24-29 [doi]
• Comparative analysis of approaches to hardware acceleration for sparse-matrix factorizationP. Sadayappan, V. Visvanathan. 32-35 [doi]
• Sorting on an array of processorsH. V. Jagadish. 36-39 [doi]
• Floating point CORDIC for matrix computationsJoseph R. Cavallaro, Franklin T. Luk. 40-42 [doi]
• Analog circuit synthesis and exploration in OASYSRamesh Harjani, Rob A. Rutenbar, L. Richard Carley. 44-47 [doi]
• Knowledge-based analog circuit synthesis with flexible architectureAntony H. Fung, David J. Chen, Ying-Nan Lai, Bing J. Sheu. 48-51 [doi]
• Interconnection delay in very high-speed VLSID. Zhou, Franco P. Preparata, S. M. Kang. 52-55 [doi]
• Test generation by fault samplingVishwani D. Agrawal, Hassan Farhat, Sharad Seth. 58-61 [doi]
• Adaptative backtrace and dynamic partitioning enhance ATPGA. Lioy. 62-65 [doi]
• The BACK algorithm for sequential test generationWu-Tung Cheng. 66-69 [doi]
• Random testability analysis: comparing and evaluating existing approachesPaolo Camurati, Paolo Prinetto, Matteo Sonza Reorda. 70-73 [doi]
• Multi-chip packaging for high performance systemsClinton C. Chao, Kim H. Chen, Ravi Kaw, Jacques Leibovitz, V. K. Nagesh, Kenneth D. Scholz. 76-81 [doi]
• Modeling and simulation of coupled lossy lines for VLSI interconnectionsOlgierd A. Palusinski, Andreas C. Cangellaris, John L. Prince, J. C. Liao, L. Vakanis. 82-86 [doi]
• Computer-aided simulation of optical interconnects for high-speed digital systemsAndrew T. Yang, D. S. Gao, S. M. Kang. 87-90 [doi]
• Free-space optical crossover interconnects for parallel computersJürgen Jahns. 91-94 [doi]
• Instruction reorganization for a variable-length pipelined microprocessorSeth Abraham, Krishnan Padmanabhan. 96-101 [doi]
• Cache-based pipeline architecture in the Hitachi H32/200 32-bit microprocessorTadahiko Nishimukai, Hideo Inayoshi, Kikuko Takagi, Kazuhiko Iwasaki, Ikuya Kawasaki, M. Hanawa, Takeshi Okada. 102-105 [doi]
• The capability mechanism of a VLSI processorKanad Ghose, Robert M. Stewart. 106-109 [doi]
• Design tradeoffs for a 40 MIPS (peak) CMOS 32-bit microprocessorD. K. Lewis, J. P. Costello, D. M. O'Connor. 110-113 [doi]
• Extension of a transistor level digital timing simulator to include first order analog behaviorRakesh Chadha, Chin-Fu Chen. 116-119 [doi]
• MILES: a mixed level simulator for analog/digital designA. C. J. Stroucken, G. J. J. M. van de Ven. 120-123 [doi]
• Variable reduction in MOS timing modelsCharles A. Zukowski, De-Ping Chen. 124-128 [doi]
• Parallel LU factorization for circuit simulation on an MIMD computerChien-Chih Chen, Yu Hen Hu. 129-132 [doi]
• A class of fault-tolerant cellular permutation networksMohsine Eleuldj, El Mostapha Aboulhamid, Eduard Cerny. 136-139 [doi]
• Test generation of C-testable array dividersChin-Long Wey, Sin-Min Chang. 140-144 [doi]
• Testing of VLSI regular arraysWilliam P. Marnane, Will R. Moore. 145-148 [doi]
• VLSI programming and silicon compilation; a novel approach from Philips researchCees Niessen, Kees van Berkel 0001, Martin Rem, Ronald W. J. J. Saeijs. 150-151 [doi]
• VLSI programmingKees van Berkel 0001, Martin Rem, Ronald W. J. J. Saeijs. 152-156 [doi]
• Compilation of communicating processes into delay-insensitive circuitsKees van Berkel 0001, Ronald W. J. J. Saeijs. 157-162 [doi]
• The design of the VLSI image-generator ZaPRonald W. J. J. Saeijs, Kees van Berkel 0001. 163-166 [doi]
• Tera-Hertz study of normal and superconducting transmission linesC. C. Chi, D. Grischkowsky. 168-171 [doi]
• c superconducting transmission lines in integrated systemsMehdi Hatamian, Larry A. Hornak, Stuart K. Tewksbury. 172-177 [doi]
• Automatic layout and optimization of static CMOS cellsFrédéric Mailhot, Giovanni DeMicheli. 180-185 [doi]
• Optimization for automatic cell assemblyD. P. Dutt, G. Lakhani. 186-189 [doi]
• An octagonal geometry compactorPaul K. Sun. 190-193 [doi]
• Processor design using path programmable logicJ. Kelly Flanagan, Brent E. Nelson. 196-199 [doi]
• Direct synthesis of mapping circuitsLiliana Díaz-Olavarrieta, Safwat G. Zaky. 200-203 [doi]
• SID: synthesis of integral designDonald F. Hooper Jr.. 204-208 [doi]
• The KARL/KARATE system - integrating functional test development into a CAD environment for VLSIGerold Alfs, Reiner W. Hartenstein, Andrea Wodtko. 209-212 [doi]
• Design of a high-speed arithmetic datapathMark Birman, George Chu, Larry Hu, John McLeod, N. Bedard, F. Ware, L. Torban, C. M. Lim. 214-215 [doi]
• Generation of high speed CMOS multiplier-accumulatorsKing Fai Pang, Hsui-Wei Soong, Randal Sexton, Peng-Huat Ang. 217-220 [doi]
• Approaching a nanosecond: a 32 bit adderGary Bewick, Paul Song, Giovanni De Micheli, Michael J. Flynn. 221-226 [doi]
• A comparison of two digit serial VLSI addersMary Jane Irwin, Robert Michael Owens. 227-229 [doi]
• System interface of the NS32532 microprocessorSidi Yom Tov, Benjamin Maytal, Z. Bikovsky, Dan Biran, Jonathan Levy II, Y. Milstain, A. Ostrer. 232-235 [doi]
• Limits of backplane bus designPaul L. Borrill. 236-239 [doi]
• VLSI support for copyback caching protocols on FuturebusPaul Sweazey. 240-246 [doi]
• CTP-A family of optimizing compilers for the NS32532 microprocessorChaim Bendelac, Gady Erlich. 247-250 [doi]
• McMAP: a fast technology mapping procedure for multi-level logic synthesisRobert Lisanke, Franc Brglez, Gershon Kedem. 252-256 [doi]
• Mapping properties of multi-level logic synthesis operationsMario C. Lega. 257-261 [doi]
• A rule based logic reorganization system LORES/EXJ. Ishikawa, H. Sato, M. Hiramine, K. Ishida, S. Oguri, Y. Kazuma, S. Murai. 262-266 [doi]
• PLA based finite state machines using Johnson counters as state memoriesRainer Amann, Bernhard Eschermann, Utz G. Baitinger. 267-270 [doi]
• Transient fault behavior in a microprocessor - A case studyP. Duba, R. K. Iyer. 272-276 [doi]
• Classical fault analysis for MOS VLSI circuitsBrian L. Shing, Mark A. Franklin. 277-282 [doi]
• A new class of symmetric error correcting / unidirectional error detecting codesNiraj K. Jha. 283-286 [doi]
• Large memory embedded ASICsT. Iizuka, T. Sakurai, J. Matsunaga, K. Maeguchi, K. Kawagai, T. Kobayashi, Y. Shiotari, K. Kobayashi, T. Miyoshi. 292-295 [doi]
• Gate array technologyConrad J. Dell'Oca. 296-299 [doi]
• The CydraTM 5 computer system architectureMichael Schlansker, Michael McNamara. 302-306 [doi]
• The Astronautics ZS-1 processorJames E. Smith 0001, G. E. Dermer, B. D. Vanderwarn, S. D. Klinger, C. M. Rozewski, D. L. Fowler, K. R. Scidmore, James Laudon. 307-310 [doi]
• EXIST: an interactive VLSI architectural environmentPieter S. van der Meulen, Ming-Der Huang, Uzi Bar-Gadda, Eva Lee, Peter G. M. Baltus. 312-319 [doi]
• PARET: an integrated visual tool for the study of parallel systemsKathleen M. Nichols, John T. Edmark. 320-323 [doi]
• Critic: a knowledge-based program for critiquing circuit designsRick L. Spickelmier, A. Richard Newton. 324-327 [doi]
• A proposed standard test bus and boundary scan architectureLee Whetsel. 330-333 [doi]
• IEEE P1149 Proposed Standard Testability Bus - An update with case historiesJon Turino. 334-337 [doi]
• HIT: a standard constructional system for testability and maintainabilityBrian R. Wilkins. 338-341 [doi]
• High speed, low power CMOS transmitter-receiver systemThaddeus J. Gabara, David W. Thompson. 344-347 [doi]
• A high speed static CMOS PLA architectureWilliam E. Engeler, Menahem Lowy, John Pedicone, John Bloomer, James Richotte, David Chan. 348-351 [doi]
• A matched-delay CMOS TDM multiplexer cellCharles A. Zukowski, Kevin Shum. 352-355 [doi]
• CREATE-LIFE: a design system for high performances VLSI circuitsJunien Labrousse, Gerrit A. Slavenburg. 356-360 [doi]
• Microarchitecture of the 80960 high-integration processorsGlenn Hinton, Konrad Lai, Randy Steck. 362-365 [doi]
• The MIPS M2000 systemTom Riordan, G. P. Grewal, Simon Hsu, John Kinsel, Jeff Libby, Roger March, Marvin Mills, Paul Ries, Randy Scofield. 366-369 [doi]
• RISC architecture of the M88000Charles Melear. 370-373 [doi]
• First 32-bit SPARC-based processors implemented in high-speed CMOSMasood Namjoo. 374-376 [doi]
• Synthesis from VHDLJoseph Lis, Daniel D. Gajski. 378-381 [doi]
• Representation of control and timing behavior with applications to interface synthesisSally A. Hayati, Alice C. Parker, John J. Granacki. 382-387 [doi]
• A novel approach to the synthesis of practical datapath architectures using artificial intelligence techniquesN. S. H. Brooks, R. J. Mack. 388-391 [doi]
• UBIST version of the SYCO's control section compilerKholdoun Torki, Michael Nicolaidis, Ahmed Amine Jerraya, Bernard Courtois. 392-396 [doi]
• Integrated design and test synthesisCatherine H. Gebotys, Mohamed I. Elmasry. 398-401 [doi]
• Estimation of area and performance overheads for testable VLSI circuitsJ. R. Miles, Anthony P. Ambler, K. A. E. Totton. 402-407 [doi]
• A modular scan-based testability systemFranc Brglez, David Bryan, John D. Calhoun, Robert Lisanke. 408-412 [doi]
• CESAR - A programmable high performance systolic array processorMorten Toverud, Vidar Andersen. 414-417 [doi]
• Reconfiguration strategies in VLSI processor arraysKrishna P. Belkhale, Prith Banerjee. 418-421 [doi]
• Parallel calculation of shortest paths in sparse graphs on a systolic arraySabine Bauer, Uwe Schwiegelshohn. 422-425 [doi]
• Area evaluation metrics for transistor placementTom Shiple, Paul Kollaritsch, Derek Smith, Jonathan Allen. 428-433 [doi]
• VITAL: fully automatic placement strategies for very large semicustom designsRathin Putatunda, David Smith, Michael Stebnisky, Carl Puschak, Paul Patent. 434-439 [doi]
• Alternative strategies for applying min-cut to VLSI placementDwight D. Hill. 440-444 [doi]
• A global chip test implementation including built-in self-testA. C. Erdal, Pierre A. Uszynski. 446-449 [doi]
• A testable PLA design with low overhead and ease of test generationJing-Yang Jou. 450-453 [doi]
• Current sensing for built-in testing of CMOS circuitsDerek Feltham, Phil Nigh, L. Richard Carley, Wojciech Maly. 454-457 [doi]
• Aliasing errors in signature analysis testing of integrated circuitsMaurizio Damiani, Piero Olivo, Michele Favalli, Bruno Riccò. 458-461 [doi]
• A modular VLSI architecture for coincidence detection in positron emission tomographyDanny F. Newport, H. M. Dent, M. E. Casey, Donald W. Bouldin. 464-467 [doi]
• A co-processor with supercomputer capabilities for personal computersW. Marwood, A. P. Clarke. 468-471 [doi]
• A methodology for the control and custom VLSI implementation of large-scale Clos networksJ. Robert Heath, Eric Allen Disch. 472-477 [doi]
• Set-associative dynamic random access memoryStephen A. Ward, Robert C. Zak. 478-483 [doi]
• Implementation of fast radix-4 division with operands scalingMilos D. Ercegovac, Tomás Lang, Ramin Modiri. 486-489 [doi]
• A serial-input serial-output bit-sliced convolverLuigi Dadda, Luca Breveglieri. 490-495 [doi]
• Use of redundant binary representation for fault-tolerant arithmetic array processorsVincenzo Piuri, Renato Stefanelli. 496-501 [doi]
• n±1)Alexander Skavantzos, Fred J. Taylor. 502-506 [doi]
• The POTATO chip architecture: a study in tradeoffs for signal processing chip designB. Sharma, Rajiv Jain, Melvin A. Breuer, Alice C. Parker, Cauligi S. Raghavendra, C. Y. Tseng. 508-513 [doi]
• Fault tolerance and testing aspects of an architecture for a generalized sidelobe cancellorMelvin A. Breuer, Amitava Majumdar, Cauligi S. Raghavendra. 514-519 [doi]
• VLSI implementation of GSC architecture with a new ripple carry adderIrving S. Reed, B. Sharma, Ming-Tang Shih, John Bailey, Trieu-Kien Truong. 520-523 [doi]
• Design of a 64-processor by 128-memory crossbar switching networkRobert F. Miracky, A. Hartmann, L. N. Smith, S. Redfield, U. Ghoshal, B. Weigler. 526-532 [doi]
• Trace driven modelling and performance evaluation of tightly coupled multiprocessor systemsKhai-Quang Luc, Shauchi Ong, Elbert C. Hu. 533-536 [doi]
• A highly parallel processor with an instruction set including relational algebraPascal Faudemay, Daniel Etiemble, Jean-Luc Béchennec. 537-538 [doi]
• Simulated annealing on a multiprocessorRoger D. Chamberlain, Mark N. Edelman, Mark A. Franklin, Ellen E. Witte. 540-544 [doi]
• Error tolerance in parallel simulated annealing techniquesRajeev Jayaraman, Frederica Darema. 545-548 [doi]
• Stop criteria in simulated annealingRalph H. J. M. Otten, Lukas P. P. P. van Ginneken. 549-552 [doi]
• On fault-tolerant structure, distributed fault-diagnosis, reconfiguration, and recovery of the array processorsS. H. Hosseini. 554-559 [doi]
• A self-reconfiguration scheme for fault-tolerant VLSI processor arraysStephen Pateras, Janusz Rajski. 560-563 [doi]
• Array partitioning: a methodology for reconfigurability and reconfiguration problemsF. Distante, Fabrizio Lombardi, Donatella Sciuto. 564-567 [doi]
• APES: an integrated system for behavioral design, simulation and evaluation of array processorsFausto Distante, Vincenzo Piuri. 568-572 [doi]
• Design of a 20 MHz 64-tap transversal filterChip C. Stearns, Daniel Luthi, Peter A. Ruetz, Peng H. Ang. 574-577 [doi]
• A high performance CMOS chipset for FFT processorsShannon Shen, Surendar Magar, Raul Aguilar, Gerry Luikuo, Mike Fleming, K. Rishavy, K. Murphy, C. Furman. 578-581 [doi]
• A novel VLSI architecture for the real-time implementation of 2-D signal processing systemsSeong-Mo Park, Winser E. Alexander, Jung H. Kim, William E. Batchelor, William T. Krakow. 582-585 [doi]
• A GaAs vector memory system for signal processingT. A. Misko. 586-589 [doi]
• A functional approach to formal hardware verification: the MTI experienceDominique Borrione, Paolo Camurati, J. L. Paillet, Paolo Prinetto. 592-595 [doi]
• A higher level hardware design verificationAtsushi Takahara, Takashi Nanya. 596-599 [doi]
• Proof and synthesisM. P. Fourman, W. J. Palmer, R. M. Zimmer. 600-603 [doi]
• Verifiable and executable theories of design for synthesizing correct hardwareShiu-Kai Chin, Kevin J. Greene. 604-610 [doi]
• ES/3090: a realization of ESA/370 system architecture in IBM's most powerful mainframe computer through a balance of technology and system innovationsWilliam J. Nohilly. 611-614 [doi]