V. Visvanathan - researchr alias

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Viewing Publication 1 - 47 from 47

2015

Best is the Enemy of Good: Design Techniques for Low Power Tunable Approximate Application Specific Integrated Chips Targeting Media-Based ApplicationsNeel Gala, V. R. Devanathan, V. Visvanathan, V. Kamakoti. jolpe, 11(2):133-148, 2015. [doi]

2014

ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICsNeel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti. vlsid 2014: 342-347 [doi]

2013

Supply and Body-Bias Voltage Assignment Based Technique for Power and Temperature Control on a Chip at Iso-Performance ConditionsVirat Gandhi, V. R. Devanathan, V. Visvanathan, Milan Patnaik, V. Kamakoti. jolpe, 9(2):207-228, 2013. [doi]

2012

Thermal-Safe Dynamic Test Scheduling Method Using On-Chip Temperature Sensors for 3D MPSoCsRama Kumar Pasumarthi, V. R. Devanathan, V. Visvanathan, Seetal Potluri, V. Kamakoti. jolpe, 8(5):684-695, 2012. [doi]

2010

Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural NetworksJanakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan. tcad, 29(7):1056-1069, 2010. [doi]

2008

Within-die gate delay variability measurement using re-configurable ring oscillatorBishnu Prasad Das, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind, V. Visvanathan. cicc 2008: 133-136 [doi]

Voltage and Temperature Scalable Logic Cell Leakage Models Considering Local Variations Based on Transistor StacksJanakiraman Viraraghavan, Bharadwaj Amrutur, V. Visvanathan. jolpe, 4(3):301-319, 2008. [doi]

2005

A Comprehensive Methodology for Noise Characterization of ASIC Cell LibrariesSreeram Chandrasekar, Gaurav Kumar Varshney, V. Visvanathan. isqed 2005: 530-535 [doi]

Application of DC Transfer Characteristics in the Elimination of Redundant Vectors for Transient Noise Characterization of Static CMOS CircuitsSreeram Chandrasekar, V. Visvanathan, Gaurav Kumar Varshney. vlsid 2005: 336-341 [doi]

Application of Alpha Power Law Models to PLL Design MethodologyB. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni. vlsid 2005: 768-773 [doi]

2001

CMOS op-amp sizing using a geometric programming formulationPradip Mandal, V. Visvanathan. tcad, 20(1):22-38, 2001. [doi]

2000

Reconfigurable Filter Coprocessor Architecture for DSP ApplicationsS. Ramanathan, S. K. Nandy, V. Visvanathan. vlsisp, 26(3):333-359, 2000. [doi]

1999

Automatic Generation of Tree Multipliers Using Placement-Driven NetlistsAvinash K. Gautam, V. Visvanathan, S. K. Nandy. iccd 1999: 285-288 [doi]

A New Approach for CMOS Op-Amp SynthesisPradip Mandal, V. Visvanathan. vlsid 1999: 189-195

Synthesis of ASIPs for DSP algorithmsS. Ramanathan, V. Visvanathan, S. K. Nandy. integration, 28(1):13-32, 1999. [doi]

Architectural Synthesis of Computational Engines for Subband Adaptive FilteringS. Ramanathan, V. Visvanathan, S. K. Nandy. vlsisp, 22(3):173-195, 1999. [doi]

Synthesis of Configurable Architectures for DSP AlgorithmsS. Ramanathan, V. Visvanathan, S. K. Nandy. vlsid 1999: 350-357 [doi]

Low-power pipelined LMS adaptive filter architectures with minimal adaptation delay1S. Ramanathan, V. Visvanathan. integration, 27(1):1-32, 1999. [doi]

A computational engine for multirate FIR digital filteringS. Ramanathan, V. Visvanathan, S. K. Nandy. sigpro, 79(2):213-222, 1999. [doi]

1997

A Self-Biased High Performance Folded Cascode CMOS Op-AmpPradip Mandal, V. Visvanathan. vlsid 1997: 429-434 [doi]

Low-Power Configurable Processor Array for DLMS Adaptive FilteringS. Ramanathan, V. Visvanathan. vlsid 1997: 198-207 [doi]

1996

VLSI Implementation of DSP ArchitecturesA. Ratan Gupta, V. Visvanathan. vlsid 1996: 3 [doi]

Design of high performance two stage CMOS cascode op-amps with stable biasingPradip Mandal, V. Visvanathan. vlsid 1996: 234-237 [doi]

A systolic architecture for LMS adaptive filtering with minimal adaptation delayS. Ramanathan, V. Visvanathan. vlsid 1996: 286-289 [doi]

1995

A modular systolic architecture for delayed least mean squares adaptive filteringV. Visvanathan, S. Ramanathan. vlsid 1995: 332-337 [doi]

1994

A CORDIC Based Programmable DXT Processor ArrayV. K. Anuradha, V. Visvanathan. vlsid 1994: 343-348

High Speed Digital Filtering on SRAM-Based FPGAsA. Giri, V. Visvanathan, S. K. Nandy, S. K. Ghoshal. vlsid 1994: 229-232

1993

Supernodal Sparse Cholesky Facotrization on Distributed-Memory MultiprocessorsKalluri Eswar, P. Sadayappan, Chua-Huang Huang, V. Visvanathan. icpp 1993: 18-22

NPCPL: Normal Process Complementary Pass Transistor Logic for Low Latency, High Throughput DesignsDebabrata Ghosh, S. K. Nandy, K. Parthasarathy, V. Visvanathan. vlsid 1993: 341-346

Macromodeling of the A.C. characteristics of CMOS Op-ampsPradip Mandal, V. Visvanathan. iccad 1993: 334-340 [doi]

A Parallel Progressive Refinement Image Rendering Algorithm on a Scalable Multithreaded VLSI Processor ArrayS. K. Nandy, Ranjani Narayan, V. Visvanathan, P. Sadayappan, Prashant S. Chauhan. icpp 1993: 94-97

A Methodology for Generating Application Specific Tree MultipliersS. Ramanathan, Nibedita Mohanty, V. Visvanathan. vlsid 1993: 176-179

A 230MHz Half Bit Level Pipelined Multiplier Using True Single Phase ClockingDinesh Somasekhar, V. Visvanathan. vlsid 1993: 347-350

A 230-MHz half-bit level pipelined multiplier using true single-phase clockingDinesh Somasekhar, V. Visvanathan. tvlsi, 1(4):415-422, 1993. [doi]

An Area-Efficient Systolic Architecture for Real-Time VLSI Finite Impulse Response FiltersV. Visvanathan, Nibedita Mohanty, S. Ramanathan. vlsid 1993: 166-171

1991

Multifrontal Factorization of Sparse Matrices on Shared-Memory MultiprocessorsKalluri Eswar, P. Sadayappan, V. Visvanathan. icpp 1991: 159-166

1989

1988

Comparative analysis of approaches to hardware acceleration for sparse-matrix factorizationP. Sadayappan, V. Visvanathan. iccd 1988: 32-35 [doi]

Parallelization and performance evaluation of circuit simulation on a shared-memory multiprocessorP. Sadayappan, V. Visvanathan. ics 1988: 254-265 [doi]

Circuit Simulation on Shared-Memory MultiprocessorsP. Sadayappan, V. Visvanathan. TC, 37(12):1634-1642, 1988.

1986

An Efficient Algorithm to Determine the Image of a Parallelepiped Under a Linear TransformationV. Visvanathan, Linda S. Milor. compgeom 1986: 207-215 [doi]

1984

A Computational Approach for the Diagnosability of Dynamical CircuitsV. Visvanathan, Alberto L. Sangiovanni-Vincentelli. tcad, 3(3):165-171, 1984. [doi]

1981

Diagnosability of Nonlinear Circuits and Systems - Part II: Dynamical SystemsRichard Saeks, Alberto L. Sangiovanni-Vincentelli, V. Visvanathan. TC, 30(11):899-904, 1981.

Diagnosability of Nonlinear Circuits and Systems - Part I: The dc CaseV. Visvanathan, Alberto L. Sangiovanni-Vincentelli. TC, 30(11):889-898, 1981.

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