Abstract is missing.
- Tutorial T1: Ambient Intelligence through Internets-of-Things - An Application Development ApproachAnil Kumar Gupta, Anand Singh, Vineeta Yadav. 1 [doi]
- Tutorial T2A: Scheduling Issues in Embedded Real-Time SystemsParmesh Ramanathan. 2 [doi]
- Tutorial T2B: Cost / Application / Time to Market Driven SoC Design and Manufacturing StrategyBarun Kumar De, Anupam Chattopadhyay, Ansuman Banerjee. 3-4 [doi]
- Tutorial T3A: Testing Low-Power Integrated Circuits: Challenges, Solutions, and Industry PracticesSrivaths Ravi, Vivek Chickermane, Krishna Chakravadhanula. 5-6 [doi]
- Tutorial T3B: Engineering Change Order (ECO) Phase Challenges and Methodologies for High Performance DesignSridhar Rangarajan, Pinaki Chakrabarti, Sourav Sahais, Ayan Datta, Adarsh Subramanya. 7-8 [doi]
- Tutorial T4: All You Need to Know about Hardware Trojans and Counterfeit ICsMohammad Tehranipoor, Domenic Forte. 9-10 [doi]
- Tutorial T5: Microfluidic Biochips: Connecting VLSI and Embedded Systems to the Life SciencesKrishnendu Chakrabarty, Tsung-Yi Ho. 11-12 [doi]
- Tutorial T6A: Pedagogy of Negative Feedback CircuitsNagendra Krishnapura. 13 [doi]
- Tutorial T6B: Embedded Memory Design for Future Technologies: Challenges and SolutionsSwaroop Ghosh. 14-15 [doi]
- Tutorial T7A: Techniques for Network-on-Chip (NoC) Design and TestSantanu Chattopadhyay. 16-17 [doi]
- Tutorial T7B: Network on Chips - The Journey OverviewJoycee Mekie, Sneha N. Ved. 18 [doi]
- Tutorial T8A: Realization of RF Front-End for a Cognitive RadioB. Ravi Kishore, B. Kameswara Rao. 19 [doi]
- A Test Partitioning Technique for Scheduling Tests for Thermally Constrained 3D Integrated CircuitsSpencer K. Millican, Kewal K. Saluja. 20-25 [doi]
- Analytical Modeling of 3D Stacked IC Yield from Wafer to Wafer Stacking with Radial Defect ClusteringEshan Singh. 26-31 [doi]
- Process-Variation Aware Multi-temperature Test SchedulingNima Aghaee, Zebo Peng, Petru Eles. 32-37 [doi]
- Reliability Aware Gate Sizing Combating NBTI and Oxide BreakdownSubhendu Roy, David Z. Pan. 38-43 [doi]
- Debug Automation for Synchronization Bugs at RTLMehdi Dehbashi, Görschwin Fey. 44-49 [doi]
- Techniques to Improve the Efficiency of SAT Based Path Delay Test GenerationKun Bian, D. M. H. Walker, Sunil P. Khatri. 50-55 [doi]
- SAT-Based Test Pattern Generation with Improved Dynamic CompactionAlexander Czutro, Sudhakar M. Reddy, Ilia Polian, Bernd Becker. 56-61 [doi]
- Efficient SAT-Based Circuit Initialization for Larger DesignsMatthias Sauer, Sven Reimer, Sudhakar M. Reddy, Bernd Becker. 62-67 [doi]
- A Coverage Guided Mining Approach for Automatic Generation of Succinct AssertionsDavid Sheridan, Lingyi Liu, Hyungsul Kim, Shobha Vasudevan. 68-73 [doi]
- Effective Liveness Verification Using a Transformation-Based FrameworkPradeep Kumar Nalla, Raj Kumar Gajavelly, Hari Mony, Jason Baumgartner, Robert Kanzelman. 74-79 [doi]
- Formal Verification and Debugging of Array Dividers with Auto-correction MechanismM. H. Haghbayan, Bijan Alizadeh, Payman Behnam, Saeed Safari. 80-85 [doi]
- All-SAT Using Minimal Blocking ClausesYinlei Yu, Pramod Subramanyan, Nestan Tsiskaridze, Sharad Malik. 86-91 [doi]
- CryptIP: An Approach for Encrypting Intellectual Property Cores with Simulation CapabilitiesSpencer K. Millican, Parameswaran Ramanathan, Kewal K. Saluja. 92-97 [doi]
- A Cube-Aware Compaction Method for Scan ATPGSharada Jha, Kameshwar Chandrasekar, Weixin Wu, Ramesh Sharma, Sanjay Sengupta, Sudhakar M. Reddy. 98-103 [doi]
- Scalable Test Generation by Interleaving Concrete and Symbolic ExecutionXiaoke Qin, Prabhat Mishra. 104-109 [doi]
- Application of Test-View Modeling to Hierarchical ATPGRahul Shukla, Phong Loi, Ken Pham, Arie Margulis, Kathy Yang, Nagesh Tamarapalli. 110-115 [doi]
- A New Sensitivity-Driven Process Variation Aware Self-Repairing Low-Power SRAM DesignNandakishor Yadav, Sunil Dutt, G. K. Sharma. 116-121 [doi]
- Timing Variation Adaptive Pipeline Design: Using Probabilistic Activity Completion Sensing with Backup Error ResilienceJayaram Natarajan, Sahil Kapoor, Debesh Bhatta, Abhijit Chatterjee, Adit D. Singh. 122-127 [doi]
- A Novel Low Power Error Detection Logic for Inexact Leading Zero Anticipator in Floating Point UnitsB. Naveen Kumar Reddy, M. Chandra Sekhar, Sreehari Veeramachaneni, M. B. Srinivas. 128-132 [doi]
- Better-than-Worst-Case Timing Design with Latch Buffers on Short PathsRavi Kanth Uppu, Ravi Tej Uppu, Adit D. Singh, Ilia Polian. 133-138 [doi]
- Pipelined Non-strobed Sensing Scheme for Lowering BL Swing in Nano-scale MemoriesSudhanshu Khanna, Satyanand Nalam, Benton H. Calhoun. 139-144 [doi]
- Energy Efficient Memory Decoder Design for Ultra-low Voltage SystemsK. R. Viveka, Bharadwaj Amrutur. 145-149 [doi]
- A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write AssistPrashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja. 150-155 [doi]
- Minimizing Power and Skew in VLSI-SoC Clocking with Pulsed Resonance Driven De-skewing LatchesIgnatius Bezzam, Shoba Krishnan. 156-161 [doi]
- Efficient Two-Phase Approaches for Branch-and-Bound Style Resource Constrained SchedulingMingsong Chen, Fan Gu, Lei Zhou, Geguang Pu, Xiao Liu. 162-167 [doi]
- Inserting Placeholder Slack to Improve Run-Time Scheduling of Non-preemptible Real-Time Tasks in Heterogeneous SystemsHsiang-Kuo Tang, Parmesh Ramanathan, Katherine Morrow. 168-173 [doi]
- Hardware Implementation of Real-Time, High Performance, RCE-NN Based Face Recognition SystemSantu Sardar, K. Ananda Babu. 174-179 [doi]
- EME Electric Supervision Embedded on Gas Panel with Microshock Dangerousness DegreeMarcelo Trindade Rebonatto, Fabiano Passuelo Hessel, Luiz Eduardo Schardong Spalding. 180-185 [doi]
- Design of AFE and PWM Drive for Lithium-Ion Battery Management System for HEV/EV SystemSudhakar Singamala, Mandfed Brandl, Sandeep Vernekar, Veereshbabu Vulligadala, Ravikumar Adusumalli, Vijay Ele. 186-191 [doi]
- Process Disturbance Analyzer for Nuclear ReactorsE. M. T. Sirisha, T. Sridevi, D. Thirugnana Murthy. 192-197 [doi]
- Design and Implementation of Safety Logic with Fine Impulse Test System for a Nuclear Reactor Shutdown SystemManoj Kumar Misra, N. Sridhar, D. Thirugnana Murthy. 198-203 [doi]
- Performance and Power Benefits of Sharing Execution Units between a High Performance Core and a Low Power CoreRance Rodrigues, Israel Koren, Sandip Kundu. 204-209 [doi]
- Process Synchronization in Multi-core Systems Using On-Chip MemoriesArun Joseph, Nagu R. Dhanwada. 210-215 [doi]
- TECS: Temperature- and Energy-Constrained Scheduling for Multicore SystemsXiaoke Qin, Prabhat Mishra. 216-221 [doi]
- Challenges in Implementing Cache-Based Side Channel Attacks on Modern ProcessorsJyoti Gajrani, Pooja Mazumdar, Sampreet Sharma, Bernard Menezes. 222-227 [doi]
- Tiny NoC: A 3D Mesh Topology with Router Channel Optimization for Area and Latency MinimizationCésar A. M. Marcon, Ramon Fernandes, Rodrigo Cataldo, Fernando Grando, Thais Webber, Ana Benso, Leticia B. Poehls. 228-233 [doi]
- NoC Scheduling for Improved Application-Aware and Memory-Aware Transfers in Multi-core SystemsTejasi Pimpalkhute, Sudeep Pasricha. 234-239 [doi]
- CARM: Congestion Adaptive Routing Method for On Chip NetworksManoj Kumar, Vijay Laxmi, Manoj Singh Gaur, Seok-Bum Ko, Mark Zwolinski. 240-245 [doi]
- Knowledge-Guided Methodology for Third-Party Soft IP AnalysisBhanu Pratap Singh, Arunprasath Shankar, Francis G. Wolff, Daniel J. Weyer, Christos A. Papachristou, Bhanu Negi. 246-251 [doi]
- Pre-mapping Algorithm for Heterogeneous MPSoCsCésar A. M. Marcon, Thais Webber, Leticia B. Poehls, Igor K. Pinotti. 252-257 [doi]
- Efficient QR Decomposition Using Low Complexity Column-wise Givens Rotation (CGR)Farhad Merchant, Anupam Chattopadhyay, Ganesh Garga, S. K. Nandy, Ranjani Narayan, Nandhini Gopalan. 258-263 [doi]
- Temperature Minimization Using Power Redistribution in Embedded SystemsRehan Ahmed, Parameswaran Ramanathan, Kewal K. Saluja. 264-269 [doi]
- Process Variation Aware Synthesis of Application-Specific MPSoCs to Maximize YieldNishit Ashok Kapadia, Sudeep Pasricha. 270-275 [doi]
- Hard versus Soft Software Defined RadioWim Meeus, Tom Vander Aa, Praveen Raghavan, Dirk Stroobandt. 276-281 [doi]
- Interfacing Synchronous and Asynchronous Domains for Open Core ProtocolVikas S. Vij, Raghu Prasad Gudla, Kenneth S. Stevens. 282-287 [doi]
- Control Mechanism to Solve False Blocking Problem at MAC Layer in Wireless Sensor NetworksBrajendra Kumar Singh, Kemal E. Tepe, Mohammed A. S. Khalid. 288-293 [doi]
- Architecture for Blocking Detection in Wireless Video Source AuthenticationAmit Pande, Shaxun Chen, Prasant Mohapatra, Gaurav Pande. 294-299 [doi]
- A Novel Architecture for FPGA Implementation of Otsu's Global Automatic Image Thresholding AlgorithmJ. G. Pandey, A. Karmakar, Chandra Shekhar, S. Gurunarayanan. 300-305 [doi]
- Accelerating Genome Assembly Using Hard Embedded Blocks in FPGAsB. Sharat Chandra Varma, Kolin Paul, M. Balakrishnan. 306-311 [doi]
- A Hardware Intensive Approach for Efficient Implementation of Numerical Integration for FPGA PlatformsBurhan Khurshid, Roohie Naz Mir. 312-317 [doi]
- Embedded Complex Floating Point Hardware AcceleratorAmin Ghasemazar, Mehran Goli, Ali Afzali-Kusha. 318-323 [doi]
- A Power Efficient Video Encoder Using Reconfigurable Approximate Arithmetic UnitsArnab Raha, Hrishikesh Jayakumar, Vijay Raghunathan. 324-329 [doi]
- QUICKRECALL: A Low Overhead HW/SW Approach for Enabling Computations across Power Cycles in Transiently Powered ComputersHrishikesh Jayakumar, Arnab Raha, Vijay Raghunathan. 330-335 [doi]
- Configurable Systolic Matrix MultiplicationParastoo Kamranfar, Ali Shahabi, Ghazaleh Vazhbakht, Zainalabedin Navabi. 336-341 [doi]
- ProCA: Progressive Configuration Aware Design Methodology for Low Power Stochastic ASICsNeel Gala, V. R. Devanathan, Karthik Srinivasan, V. Visvanathan, V. Kamakoti. 342-347 [doi]
- Hardware Efficient VLSI Architecture for 3-D Discrete Wavelet TransformAnand D. Darji, Saurabh Shukla, S. N. Merchant, Arun N. Chandorkar. 348-352 [doi]
- Design and Implementation of High Throughput and Area Efficient Hard Decision Viterbi Decoder in 65nm TechnologyNarayan V. Sugur, Saroja V. Siddamal, Samba Sivam Vemala. 353-358 [doi]
- Scalable Low Power FFT/IFFT Architecture with Dynamic Bit Width ConfigurabilitySundarrajan Rangachari, Jaiganesh Balakrishnan, Nitin Chandrachoodan. 359-364 [doi]
- A Decimal/Binary Multi-operand Adder Using a Fast Binary to Decimal ConverterCh. Santosh Varma, Syed Ershad Ahmed, M. B. Srinivas. 365-368 [doi]
- Global Routing Using Monotone Staircases with Minimal BendsBapi Kar, Susmita Sur-Kolay, Chittaranjan A. Mandal. 369-374 [doi]
- Delete and Correct (DaC): An Atomic Logic Operation for Removing Any Unwanted WireXing Wei, Tak-Kei Lam, Xiaoqing Yang, Wai-Chung Tang, Yi Diao, Yu-Liang Wu. 375-380 [doi]
- On Manufacturing Aware Physical Design to Improve the Uniqueness of Silicon-Based Physically Unclonable FunctionsRaghavan Kumar, Siva Nishok Dhanuskodi, Sandip Kundu. 381-386 [doi]
- Obstacle Avoiding Rectilinear Clock Tree Construction with Skew MinimizationPartha Pratim Saha, Tuhina Samanta. 387-392 [doi]
- Layout-Aware Delay Variation Optimization for CNTFET-Based CircuitsMatthias Beste, Saman Kiamehr, Mehdi Baradaran Tahoori. 393-398 [doi]
- Leakage Modeling for Devices with Steep Sub-threshold Slope Considering Random Threshold VariationsAyan Paul, Chaitanya Kshirsagar, Sachin S. Sapatnekar, Steven J. Koester, Chris H. Kim. 399-404 [doi]
- Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness AsymmetryNeha Sharan, Santanu Mahapatra. 405-410 [doi]
- Analytical Modeling of Sub-onset Current of Tunnel Field Effect TransistorParmanand Singh, Vivek Asthana, Radhakrishnan Sithanandam, Anand Bulusu, Sudeb Dasgupta. 411-414 [doi]
- Statistical Modeling of Glitching Effects in Estimation of Dynamic Power ConsumptionMichael Meixner, Tobias G. Noll. 415-420 [doi]
- BSIM6 - Benchmarking the Next-Generation MOSFET Model for RF ApplicationsAnupam Dutta, Saurabh Sirohi, Ethirajan Tamilmani, Harshit Agarwal, Yogesh Singh Chauhan, Richard Q. Williams. 421-426 [doi]
- Analysis of Nanoscale Strained-Si/SiGe MOSFETs including Source/Drain Series Resistance through a Multi-iterative TechniqueAmrita Kumari, Subindu Kumar. 427-432 [doi]
- An ABCD Parameter Based Modeling and Analysis of Crosstalk Induced Effects in Multiwalled Carbon Nanotube Bundle InterconnectsManodipan Sahoo, Prasun Ghosal, Hafizur Rahaman. 433-438 [doi]
- Performance Optimization and Parameter Sensitivity Analysis of Ultra Low Power Junctionless MOSFETsMukta Singh Parihar, Abhinav Kranti. 439-443 [doi]
- Improvements to Negative-C Compensation Based Amplifiers for Broadband ApplicationsRajesh Cheeranthodi, Santhosh Madhavan, Umesh K. Shukla, Giri Rangan. 444-449 [doi]
- An Adaptive Inductorless Continuous Time Equalizer for Gigabit Links in 0.13 um CMOSSushrant Monga, Shouri Chatterjee. 450-454 [doi]
- On Dependence of Amplitude Noise versus Offset Frequency in LC OscillatorsR. Sivaramakrishna, Shalabh Gupta. 455-459 [doi]
- A 1 V, Sub-mW CMOS LNA for Low-Power 1 GHz Wide-Band Wireless ApplicationsArunkumar Salimath, Pradeep Karamcheti, Achintya Halder. 460-465 [doi]
- Low Power Single Amplifier Voltage RegulatorSanjay Kumar Wadhwa, Jaideep Banerjee, Rakesh Kumar Gupta. 466-469 [doi]
- Forward Body Biased Adiabatic Logic for Peak and Average Power Reduction in 22nm CMOSMatthew Morrison, Nagarajan Ranganathan. 470-475 [doi]
- FinFET Logic Circuit Optimization with Different FinFET Styles: Lower Power Possible at Higher Supply VoltageSourindra Chaudhuri, Niraj K. Jha. 476-482 [doi]
- Operand Isolation with Reduced Overhead for Low Power Datapath DesignLokesh Siddhu, Amit Mishra, Virendra Singh. 483-488 [doi]
- High-Speed, Low-Power Quasi Delay Insensitive Handshake Circuits Based on FinFET TechnologyMohammad Yousef Zarei, Mahdi Mosaffa, Siamak Mohammadi. 489-494 [doi]
- Active Cooling Technique for Efficient Heat Mitigation in 3D-ICsPramod Kaddi, Basireddy Karunakar Reddy, Shiv Gobind Singh. 495-498 [doi]
- Improved Design Methodology for the Development of Electrically Actuated MEMS StructuresA. V. S. S. Prasad, K. P. Venkatesh, Rudra Pratap, Navakanta Bhat. 499-503 [doi]
- Correctness Checking of Bio-chemical Protocol Realizations on a Digital Microfluidic BiochipSukanta Bhattacharjee, Ansuman Banerjee, Krishnendu Chakrabarty, Bhargab B. Bhattacharya. 504-509 [doi]
- A Novel Wire Planning Technique for Optimum Pin Utilization in Digital Microfluidic BiochipsPranab Roy, Samadrita Bhattacharya, Rupam Bhattacharyay, Firdousi Jamil Imam, Hafizur Rahaman, Parthasarathi Dasgupta. 510-515 [doi]
- Output Impedance as Figure of Merit to Predict Transient Performance for Embedded Linear Voltage RegulatorsSaurabh Kumar Singh, Nitin Bansal. 516-521 [doi]
- A Time-Based Low Voltage Body Temperature Monitoring UnitKarthik Ramkumar Jeyashankar, Makrand Mahalley, Bharadwaj Amrutur. 522-527 [doi]
- Trimless, PVT Insensitive Voltage Reference Using Compensation of Beta and Thermal VoltageHande Vinayak Gopal, Maryam Shojaei Baghini. 528-533 [doi]
- A Low Power CMOS Imager Based on Distributed Compressed SensingBhuvanan Kaliannan, Vijaya Sankara Rao Pasupureddi. 534-538 [doi]
- All Optical Reversible Multiplexer Design Using Mach-Zehnder InterferometerKamalika Datta, Indranil Sengupta. 539-544 [doi]
- Circuit for Reversible Quantum Multiplier Based on Binary Tree Optimizing Ancilla and Garbage BitsSaurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan. 545-550 [doi]
- Design of Dedicated Reversible Quantum Circuitry for Square ComputationH. V. Jayashree, Himanshu Thapliyal, Vinod Kumar Agrawal. 551-556 [doi]
- An Optimized Design of Reversible Quantum ComparatorSai Phaneendra P., Chetan Vudadha, Sreehari Veeramachaneni, M. B. Srinivas. 557-562 [doi]
- Light Load Efficiency Improvement in High Frequency DC-DC Buck Converter Using Dynamic Width Segmentation of Power MOSFETN. J. Metilda Sagaya Mary, Ashis Maity, Amit Patra. 563-568 [doi]
- Histogram Based Deterministic Digital Background Calibration for Pipelined ADCsChithira Ravi, T. Rahul, Bibhudatta Sahoo. 569-574 [doi]
- A Power Efficient Fully Differential Back Terminated Current-Mode HDMI SourceR. Gopikrishnan, Vijaya Sankara Rao Pasupureddi, Govindarajulu Regeti. 575-579 [doi]
- An Adaptive Body-Biased Clock Generation System in 28nm CMOSMakarand Shirasgaonkar, Roxanne Vu, Deborah Dressler, Nhat Nguyen, Kambiz Kaviani, Yueyong Wang. 580-583 [doi]