Santanu Mahapatra - researchr alias

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Viewing Publication 1 - 16 from 16

2022

Massive Monte Carlo simulations-guided interpretable learning of two-dimensional Curie temperatureArnab Kabiraj, Tripti Jain, Santanu Mahapatra. patterns, 3(12):100625, 2022. [doi]

2020

First Principles Based Compact Model for 2D-Channel MOSFETsBiswapriyo Das, Santanu Mahapatra. isdcs 2020: 1-6 [doi]

2019

Insights on Anisotropic Dissipative Quantum Transport in n-Type Phosphorene MOSFETMadhuchhanda Brahma, Arnab Kabiraj, Santanu Mahapatra. vlsid 2019: 179-184 [doi]

2018

New Asymmetric Atomistic Model for the Analysis of Phase-Engineered MoS2-Gold Top ContactRicha Chakravarty, Dipankar Saha, Santanu Mahapatra. vlsid 2018: 139-142 [doi]

2016

Compact noise modelling for common double-gate metal-oxide-semiconductor field-effect transistor adapted to gate-oxide-thickness asymmetryNeha Sharan, Santanu Mahapatra. iet-cds, 10(1):62-67, 2016. [doi]

2014

Small Signal Nonquasi-static Model for Common Double-Gate MOSFETs Adapted to Gate Oxide Thickness AsymmetryNeha Sharan, Santanu Mahapatra. vlsid 2014: 405-410 [doi]

2010

Impact of energy quantisation in single electron transistor island on hybrid complementary metal oxide semiconductor- single electron transistor integrated circuitsSurya Shankar Dan, Santanu Mahapatra. iet-cds, 4(5):449-457, 2010. [doi]

A Non Quasi-static Small Signal Model for Long Channel Symmetric DG MOSFETSudipta Sarkar, Ananda S. Roy, Santanu Mahapatra. vlsid 2010: 21-26 [doi]

2009

Concept of Crossover Point and its Application on Threshold Voltage Definition for Undoped-Body TransistorsRatul Kumar Baruah, Santanu Mahapatra. vlsid 2009: 241-246 [doi]

Analysis of the Energy Quantization Effects on Single Electron Inverter Performance through Noise Margin ModelingSurya Shankar Dan, Santanu Mahapatra. vlsid 2009: 493-498 [doi]

2008

Drive current boosting of n-type tunnel FET with strained SiGe layer at sourceNayan Patel, A. Ramesha, Santanu Mahapatra. mj, 39(12):1671-1677, 2008. [doi]

A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire TransistorBiswajit Ray, Santanu Mahapatra. vlsid 2008: 447-452 [doi]

2007

Modeling and Analysis of Noise Margin in SET LogicChaitanya Sathe, Santanu Mahapatra. vlsid 2007: 207-214 [doi]

2003

A CAD Framework for Co-Design and Analysis of CMOS-SET Hybrid Integrated CircuitsSantanu Mahapatra, Kaustav Banerjee, Florent Pegeon, Adrian M. Ionescu. iccad 2003: 497-503 [doi]

2002

Few electron devices: towards hybrid CMOS-SET integrated circuitsAdrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier. dac 2002: 88-93 [doi]

A SET quantizer circuit aiming at digital communication systemSantanu Mahapatra, Adrian M. Ionescu, Kaustav Banerjee, Michel J. Declercq. iscas 2002: 860-863 [doi]

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