Table of Contents

• Synthesizing Performance-Aware (m, k)-Firm Control Execution Patterns Under Dropped SamplesSumana Ghosh, Soumyajit Dey, Pallab Dasgupta. 1-6 [doi]
• Write Variation Aware Non-volatile Buffers for On-Chip InterconnectsKhushboo Rani, Hemangee K. Kapoor. 7-12 [doi]
• Performance Enhancement of Caches in TCMPs Using Near Vicinity PrefetcherDipika Deb, John Jose, Maurizio Palesi. 13-18 [doi]
• EdgeCoolingMode: An Agent Based Thermal Management Mechanism for DVFS Enabled Heterogeneous MPSoCsSomdip Dey, Enrique Zaragoza Guajardo, Basireddy Karunakar Reddy, Xiaohang Wang, Amit Kumar Singh, Klaus D. McDonald-Maier. 19-24 [doi]
• Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active TerminationAntroy Roy Chowdhury, Nijwm Wary, Pradip Mandal. 25-30 [doi]
• Ultra Low Energy Reduced Switching DAC for SAR ADCJapesh Vohra, Hande Vinayak Gopal. 31-35 [doi]
• A Power Efficient Output Capacitor-Less LDO Regulator with Auto-Low Power Mode and Using Feed-Forward CompensationAbirmoya Santra, Qadeer A. Khan. 36-40 [doi]
• MOS Varactor RO Architectures in Near Threshold Regime Using Forward Body Biasing TechniquesLalit Dani, Neeraj Mishra, Bulusu Anand. 41-45 [doi]
• Low-Complexity Continuous-Flow Memory-Based FFT Architectures for Real-Valued SignalsJinti Hazarika, Mohd Tasleem Khan, Shaik Rafi Ahamed. 46-51 [doi]
• Reducing the Overhead of Stochastic Number Generators Without Increasing ErrorYudai Sakamoto, Shigeru Yamashita. 52-57 [doi]
• Low Complexity & Improved Efficiency of Encoded Data Using Peres Gate in BWAR with Testable FeatureTripti Nirmalkar, Deepti Kanoujia, Kshitiz Varma. 58-63 [doi]
• A Systematic Approach for Acceleration of Matrix-Vector Operations in CGRA through Algorithm-Architecture Co-DesignFarhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers. 64-69 [doi]
• A State Encoding Methodology for Side-Channel Security vs. Power Trade-off ExplorationRicha Agrawal, Mike Borowczak, Ranga Vemuri. 70-75 [doi]
• An Efficient Memory Zeroization Technique Under Side-Channel AttacksAnkush Srivastava, Prokash Ghosh. 76-81 [doi]
• Two-Pattern ∆IDDQ Test for Recycled IC DetectionPrattay Chowdhury, Ujjwal Guin, Adit D. Singh, Vishwani D. Agrawal. 82-87 [doi]
• Parallelization of Brute-Force Attack on MD5 Hash Algorithm on FPGAMaruthi Gillela, Vaclav Prenosil, Venkat Reddy Ginjala. 88-93 [doi]
• A Binary Decision Diagram Approach to On-line Testing of Asynchronous CircuitsPradeep Kumar Biswal, Santosh Biswas. 94-99 [doi]
• RTL Test Generation on Multi-core and Many-Core ArchitecturesAravind Krishnan Varadarajan, Michael Hsiao. 100-105 [doi]
• On-chip MISR Compaction Technique to Reduce Diagnostic Effort and Test TimeJaidev Shenoy, Kelly A. Ockunzzi, Virendra Singh, Kushal Kamal. 106-111 [doi]
• RSBST: A Rapid Software-Based Self-Test Methodology for Processor TestingVasudevan M. S, Santosh Biswas, Aryabartta Sahu. 112-117 [doi]
• A 19.3-24.8 GHz Dual-Slope VCO in 65-nm CMOS for Automotive Radar ApplicationsVipul Jain, Saurabh Kumar Gupta, Vishal Khatri, Gaurab Banerjee. 118-123 [doi]
• Analysis and Design of Low Phase Noise LC Oscillator for Sub-mW PLL-Free Biomedical ReceiversAbhishek Srivastava, Maryam Shojaei Baghini. 124-129 [doi]
• IIP3 Improvement in Subthreshold LNAs Using Modified Derivative Superposition Technique for IoT ApplicationsAnant Rungta, Kavindra Kandpal. 130-134 [doi]
• Enhanced IIP2 Chopper Stabilized Direct Conversion Mixer ArchitectureRohit Rothe, Rajesh Zele. 135-138 [doi]
• Power and Area Efficient Approximate Heterogeneous 8T SRAM for Multimedia ApplicationsPramod Kumar Bharti, Neelam Surana, Joycee Mekie. 139-144 [doi]
• Ultra Low Power Digital Front-End for Single Lead ECG AcquisitionSanket Thakkar, Biswajit Mishra. 145-150 [doi]
• Scheduling of Dual Supercapacitor for Longer Battery Lifetime in Systems with Power GatingSumanta Pyne. 151-156 [doi]
• An Energy Efficient In-Memory Computing Machine Learning Classifier SchemeShixiong Jiang, Sheena Ratnam Priya, Naveena Elango, James Clay, Ramalingam Sridhar. 157-162 [doi]
• An Unified Charge Centroid Model for Silicon and Low Effective Mass III-V Channel Double Gate MOS TransistorsAmratansh Gupta, Mohit Ganeriwala, Nihar Ranjan Mohapatra. 163-167 [doi]
• Optimization of Multiple Physical Phenomena through a Universal Metric in Junctionless TransistorsManish Gupta, Abhinav Kranti. 168-173 [doi]
• Delay Skew Reduction in IO Glitch FilterKiran Gopal, Avanish K. 174-178 [doi]
• Insights on Anisotropic Dissipative Quantum Transport in n-Type Phosphorene MOSFETMadhuchhanda Brahma, Arnab Kabiraj, Santanu Mahapatra. 179-184 [doi]
• Modeling, Fabrication and Investigation of Mixing in Low-Cost Passive PDMS MicromixersT. Pravinraj, Rajendra Patrikar. 185-190 [doi]
• Design of Continuous-Flow Lab-on-Chip with 3D Microfluidic Network for Sample PreparationTapalina Banerjee, Sudip Poddar, Sarmishtha Ghoshal, Bhargab B. Bhattacharya. 191-196 [doi]
• Security Assessment of Microfluidic Fully-Programmable-Valve-Array BiochipsMohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty, Ramesh Karri. 197-202 [doi]
• Improved Look-Ahead Approaches for Nearest Neighbor Synthesis of 1D Quantum CircuitsAnirban Bhattacharjee, Chandan Bandyopadhyay, Robert Wille, Rolf Drechsler, Hafizur Rahaman. 203-208 [doi]
• UniWiG: Unified Winograd-GEMM Architecture for Accelerating CNN on FPGAsS. Kala, Jimson Mathew, Babita R. Jose, Nalesh Sivanandan. 209-214 [doi]
• The Ramifications of Making Deep Neural Networks CompactNandan Kumar Jha, Sparsh Mittal, Govardhan Mattela. 215-220 [doi]
• Machine Learning Based Power Efficient Approximate 4: 2 Compressors for Imprecise MultipliersLavanya Maddisetti, J. V. R. Ravindra. 221-226 [doi]
• MAVI: Mobility Assistant for Visually Impaired with Optional Use of Local and Cloud ResourcesRajesh Kedia, Anupam Sobti, Mukund Rungta, Sarvesh Chandoliya, Akhil Soni, Anil Kumar Meena, Chrystle Myrna Lobo, Richa Verma, M. Balakrishnan, Chetan Arora 0001. 227-232 [doi]
• RiverOpt: A Multiobjective Optimization Framework Based on Modified River Formation Dynamics HeuristicSatyabrata Dash, Sukanta Dey, Anish Augustine, Sankar Dhar, Jan Pidanic, Zdenek Nemec, Gaurav Trivedi. 233-238 [doi]
• Structural and Behavioural Facets of Digital Microfluidic Biochips with Hexagonal-Electrode-Based ArrayAmartya Dutta, Riya Majumder, Debasis Dhal, Rajat Kumar Pal. 239-244 [doi]
• Parasitic-Aware Automatic Analog CMOS Circuit Design EnvironmentSubhash Jagadishchandra Patel, Rajesh A. Thakker. 245-250 [doi]
• Ultra Low Power Low Frequency On-chip Oscillator for Elapsed Time CounterSachin Kalburgi, Deven Gupta, Sampath Holi, Rohit Shetty, Shripad Annigeri, Shraddha H, Saroja V. S, Sujata K, Nalini C. Iyer. 251-256 [doi]
• Criticality Aware Soft Error Mitigation in the Configuration Memory of SRAM Based FPGASwagata Mandal, Sreetama Sarkar, Ming Ming Wong, Anupam Chattopadhyay, Amlan Chakrabarti. 257-262 [doi]
• Multidimensional Grid Aware Address Prediction for GPGPUShivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy. 263-268 [doi]
• Efficient Heap Data Management on Software Managed Manycore ArchitecturesJinn-Pean Lin, Jing Lu, Jian Cai, Aviral Shrivastava. 269-274 [doi]
• In Situ Latency Monitoring for Heterogeneous Real-Time SystemsMartin Geier, Tobias Burghart, Martin Hackl, Samarjit Chakraborty. 275-280 [doi]
• Investigation of Unified Emerging-NVM SoC Architecture for IoT-WSN ApplicationsVivek Kamalkant Parmar, Swatilekha Majumdar, Preeti Ranjan Panda, Manan Suri. 281-286 [doi]
• A 75-µW 2.4 GHz Wake-up Receiver in 65-nm CMOS for Neonatal Healthcare ApplicationKundan Kumar, Raghunath K. P, Akshay Muraleedharan, Javed S. Gaggatur, Gaurab Banerjee. 287-292 [doi]
• Perturbation Based Workload Augmentation for Comprehensive Functional Safety AnalysisV. Prasanth, Rubin A. Parekhji, Bharadwaj Amrutur. 293-298 [doi]
• A Double Pumped Single-Line-Cache SRAM Architecture for Ultra-low Energy IoT and Machine Learning ApplicationsArijit Banerjee, Benton H. Calhoun. 299-304 [doi]
• A Mismatch Resilient 16-Bit 20 MS/s Pipelined ADCSatyajit Mohapatra, Hari Shanker Gupta, Nihar Ranjan Mohapatra, Sanjeev Mehta, Arup Roy Chowdhury, Nisha Pandya. 305-310 [doi]
• Large Dynamic Range Readout Integrated Circuit for Infrared DetectorsHari Shanker Gupta, Sanjeev Mehta, Maryam Shojaei Baghini, Arup Roy Chowdhury, A. S. Kiran Kumar, Dinesh Kumar Sharma. 311-316 [doi]
• Current DAC Based -40dB PSRR Configurable Output LDO in BCD TechnologyVivek Tyagi, Vikas Rana, Laura Capecchi, Marcella Carissimi, Riccardo Zurla, Marco Pasotti. 317-322 [doi]
• Modeling and Characterization of VBUS Power Discharge for Embedded Superspeed USB Host/DevicesManeesh Pandey, Mohit Goyal, Parul Sharma, Rohit Sharma. 323-328 [doi]
• High-Throughput and High-Speed Polar-Decoder VLSI-Architecture for 5G New RadioRahul Shrestha, Pooja Bansal, Srikant Srinivasan. 329-334 [doi]
• VLSI Architectures for Jacobi Symbol ComputationAyan Palchaudhuri, Anindya Sundar Dhar. 335-340 [doi]
• Soft Error Resilient and Energy Efficient Dual Modular TSPC Flip-FlopShubhanshu Gupta, Joycee Mekie. 341-346 [doi]
• k-Core: Hardware Accelerator for k-Mer Generation and Counting used in Computational GenomicsSimmi M. Bose, Varsha S. Lalapura, S. Saravanan, Madhura Purnaprajna. 347-352 [doi]
• Novel Randomized & Biased Placement for FPGA Based Robust Random Number Generator with Enhanced UniquenessArjun Singh Chauhan, Vineet Sahula, Atanendu S. Mandal. 353-358 [doi]
• SoCINT: Resilient System-on-Chip via Dynamic Intrusion DetectionAmr Sayed-Ahmed, Jawad Haj-Yahya, Anupam Chattopadhyay. 359-364 [doi]
• Linear Approximation and Differential Attacks on Logic Locking TechniquesGhanshyam Bairwa, Souvik Mandal, Tatavarthy Venkat Nikhil, Bodhisatwa Mazumdar. 365-370 [doi]
• Efficient Post-Silicon Validation of Network-on-Chip Using Wireless LinksSidhartha Sankar Rout, Kanad Basu, Sujay Deb. 371-376 [doi]
• Improving Performance of a Path-Based Equivalence Checker Using Counter-ExamplesRamanuj Chouksey, Chandan Karfa, Purandar Bhaduri. 377-382 [doi]
• Selective Sensitization of Useless Sneak-Paths for Test Optimization in Memristor-ArraysManobennath Mondal, Susmita Sur-Kolay, Bhargab B. Bhattacharya. 383-388 [doi]
• A Methodology for SAT-Based Electrical Error Debugging During Post-Silicon ValidationBinod Kumar 0001, Masahiro Fujita, Virendra Singh. 389-394 [doi]
• Test Configuration Generation for Different FPGA Architectures for Application Independent TestingShukla Banik, Suchismita Roy, Bibhash Sen. 395-400 [doi]
• An Efficient Design Approach for Implementation of 2 Bit Ternary Flash ADC Using Optimized Complementary TFET DevicesSanjay Vidhyadharan, Ramakant Ramakant, Abhay S. V, A. Krishna Shyam, Mohit P. Hirpara, Surya S. Dan. 401-406 [doi]
• Optimizing Quantum Circuits for Modular ExponentiationRakesh Das, Anupam Chattopadhyay, Hafizur Rahaman. 407-412 [doi]
• A Capacity-Aware Wash Optimization for Contamination Removal in Programmable Microfluidic Biochip DevicesPiyali Datta, Arpan Chakraborty, Rajat Kumar Pal. 413-418 [doi]
• Novel Low and High Threshold TFET Based NTI and PTI Cells Benchmarked with Standard 45 nm CMOS Technology for Ternary Logic ApplicationsRamakant Ramakant, Sanjay Vidhyadharan, A. Krishna Shyam, Mohit Hirpara, Tanmay Chaudhary, Surya S. Dan. 419-424 [doi]
• Write Variation Aware Cache Partitioning for Improved Lifetime in Non-volatile CachesArijit Nath, Hemangee K. Kapoor. 425-430 [doi]
• Applying Modified Householder Transform to Kalman FilterFarhad Merchant, Tarun Vatwani, Anupam Chattopadhyay, Soumyendu Raha, S. K. Nandy, Ranjani Narayan, Rainer Leupers. 431-436 [doi]
• Area Efficient & High Performance Word Line Segmented Architecture in 7nm FinFET SRAM CompilerVinay Kumar, Neeraj Kapoor, Sudhir Kumar, Monila Juneja, Amit Khanuja. 437-442 [doi]
• Design of an Optimized CMOS ELM AcceleratorManoj Kumar Sharma, Umesh Chandra Lohani, Vivek Parmar, Manan Suri. 443-447 [doi]
• Design and Physical Implementation of Array Signal Processor ASIC for Sector Imaging SystemsJayaraj U. Kidav, N. M. Sivamangai, M. P. Pillai, Sreejeesh S. G. 448-453 [doi]
• Low Power Design Technique in Passive Tag to Reduce the EMD Noise for Reliable Communication with ReaderRahul Pathak, Raghavendra Kongari, Shankar Joshi. 454-458 [doi]
• Allowing Switching off Periphery Voltage Island Instead of Doing it per Instance Through Periphery VDD Collapse in SRAMsKrashna Nand Mishra, Ruchin Jain, Shailendra Sharad, Ravindra Shrivastava. 459-463 [doi]
• Majority Logic: Prime Implicants and n-Input Majority Term EquivalenceRajeswari Devadoss, Kolin Paul, M. Balakrishnan. 464-469 [doi]
• Heterogeneity Aware Power Abstraction for Hierarchical Power AnalysisArun Joseph, Spandana Rachamalla, Shashidhar Reddy, Nagu R. Dhanwada. 470-475 [doi]
• HEART: A Heterogeneous Energy-Aware Real-Time SchedulerSanjay Moulik, Rajesh Devaraj, Arnab Sarkar. 476-481 [doi]
• Adaptive Fractional Open Circuit Voltage Method for Maximum Power Point Tracking in a Photovoltaic PanelShubham Negi, Ashis Maity, Amit Patra, Mrigank Sharad. 482-487 [doi]
• Energy Efficient Power Distribution on Many-Core SoCMustafa M. Shihab, Vishwani Agrawal. 488-493 [doi]
• Current Collapse Reduction Technique Using N-Doped Buffer Layer into the Bulk Region of a Gate Injection TransistorKoushik Bharadwaj, Ashok Ray, Sushanta Bordoloi, Gaurav Trivedi. 494-495 [doi]
• Design and Analysis of a Minimally Invasive and ECG Controlled Ventricular Assistive DevicePrajwal Prajwal Sharma, Prashanthi K, Vinay Chandrasekhar, Krishna Nagaraja, Vikas Vahiyal, Madhav Rao. 496-497 [doi]
• A Simple Synthesis Process for Combinational QCA Circuits: QSynthesizerVaishali Dhare, Usha Mehta. 498-499 [doi]
• Mapping of Boolean Logic Functions onto 3D Memristor CrossbarNaveen Murali G, Peddireddi Satya Vardhan, F. Lalchhandama, Kamalika Datta, Indranil Sengupta 0001. 500-501 [doi]
• Stability Analysis of SRAM Designed Using In0.53Ga0.47As nFinFET with Underlap RegionJay Pathak, A. D. Darji. 502-503 [doi]
• Neuromorphic Circuits on FDSOI Technology for Computer Vision ApplicationsDinesh Rajasekharan, Amit Ranjan Trivedi, Yogesh Singh Chauhan. 504-505 [doi]
• Reconfigurable Digital Logic Gate Based on Neuromorphic ApproachNavin Singhal, M. Santosh, S. C. Bose. 506-507 [doi]
• Realizing Boolean Functions Using Probabilistic Spin Logic (PSL)Vaibhav Agarwal, Sneh Saurabh. 508-509 [doi]
• Comparative Study of Analog Matching Structures in 28FDSOIVarun Kumar Dwivedi, Meenakshi Didharia, Madhvi Sharma, Manoj Kumar Sharma. 510-511 [doi]
• A Model of Spurs for Delta-Sigma Fractional PLLsDebdut Biswas, Tarun Kanti Bhattacharyya. 512-513 [doi]
• Exploiting Negative Control Lines and Nearest Neighbor for Improved Comparator DesignTathagato Bose, Kamalika Datta, Indranil Sengupta 0001. 514-515 [doi]
• Intelligent Scheduling of Smart Appliances in Energy Efficient Buildings: A Practical ApproachNilotpal Chakraborty, Arijit Mondal, Samrat Mondal. 516-517 [doi]
• Design and Implementation of Threshold Logic Functions Using MemristorsYaswanth Krishna Yadav Danaboina, Pravanjan Samanta, Kamalika Datta, Indrajit Chakrabarti, Indranil Sengupta 0001. 518-519 [doi]
• A Transimpedance Amplifier with Improved PSRR at High Frequencies for EMI RobustnessSana Mujeeb, Krishna Kanth Gowri Avalur. 520-521 [doi]
• On-chip RF to DC Power Converter for Bio-Medical ApplicationsHarshal Chapade, Rajesh Zele. 522-524 [doi]
• Energy Efficient Communication with Lossless Data Encoding for Swarm Robot CoordinationKarthik Narayanan, Vinayak Honkote, Dibyendu Ghosh, Swamy Baldev. 525-526 [doi]
• Multi-application Based Network-on-Chip Design for Mesh-of-Tree Topology Using Global Mapping and Reconfigurable ArchitectureMohit Upadhyay, Monil Shah, P. Veda Bhanu, Soumya J., Linga Reddy Cenkeramaddi. 527-528 [doi]
• Extending STL BASOPs Used in 3GPP Codecs to Leverage Features of Modern DSP ArchitecturesAjay Homkar, Satish Patil, Lukman Rahumathulla, Raj Pawate, Sachin Ghanekar. 529-530 [doi]
• A Machine Learning Based Approach to Predict Power Efficiency of S-BoxesRajat Sadhukhan, Nilanjan Datta, Debdeep Mukhopadhyay. 531-532 [doi]
• RF and RFID Based Object Identification and Navigation System for the Visually ImpairedGaurav Mishra, Urvi Ahluwalia, Karan Praharaj, Shreyangi Prasad. 533-534 [doi]
• Design and Implementation of Low-Power High-throughput PRNGs for Security ApplicationsBikram Paul, Apratim Khobragade, Soumith Javvaji Sai, Sushree Sila P. Goswami, Sunil Dutt, Gaurav Trivedi. 535-536 [doi]
• Hardware Trojan Detection by Stimulating Transitions in Rare NetsTapobrata Dhar, Surajit Kumar Roy, Chandan Giri. 537-538 [doi]
• Continuous Transparent Mobile Device Touchscreen Soft Keyboard Biometric AuthenticationTimothy Dee, Ian Richardson, Akhilesh Tyagi. 539-540 [doi]
• Design of a Charge Sensitive Amplifier for Silicon Particle Detector in BCD 180 nm ProcessIndu Yadav, Ashish Joshi, Ettore Ruscino, Valentino Liberali, Attilio Andreazza, Hitesh Shrimali. 541-542 [doi]
• WCET-Aware Stack Frame Management of Embedded Systems Using Scratchpad MemoriesYooseong Kim, Mohammad Khayatian, Aviral Shrivastava. 543-544 [doi]
• Self-Organizing Maps-Based Flexible and High-Speed Packet Classification in Software Defined NetworkingShih-Chang Hung, Nick Iliev, Balajee Vamanan, Amit Ranjan Trivedi. 545-546 [doi]
• A 0.8V V_MIN Ultra-Low Leakage High Density 6T SRAM in 40nm CMOS Technology Using Repeated-Pulse Wordline Suppression SchemeAshish Kumar, Mohammad Aftab Alam, Gangaikondan S. Visweswaran. 547-548 [doi]