Prashant Dubey - researchr alias

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Viewing Publication 1 - 11 from 11

2017

A 0.42V high bandwidth synthesizable parallel access smart memory fabric for computer visionPrashant Dubey, Kritika Aditya, Ankur Srivastava, Amit Khanuja, Jamil Kawa, Thu Nguyen. iscas 2017: 1-4 [doi]

2014

A 500 mV to 1.0 V 128 Kb SRAM in Sub 20 nm Bulk-FinFET Using Auto-adjustable Write AssistPrashant Dubey, Gaurav Ahuja, Vaibhav Verma, Sanjay Kumar Yadav, Amit Khanuja. vlsid 2014: 150-155 [doi]

2013

PODIA: Power Optimization through Differential Imbalanced AmplifierPrashant Dubey, Atul Kumar Kashyap, Navneet Gupta, Kaushik Saha. vlsid 2013: 125-129 [doi]

38dB Tuning Range Coupled VCO Based Divider Architecture with 68uW Power @2.0 GHz in 65nm CMOSPrashant Dubey, Rashmi Agarwal. vlsid 2013: 158-162 [doi]

2010

Study of Read Recovery Dynamic Faults in 6T SRAMS and Method to Improve Test TimePrashant Dubey, Akhil Garg, Shashank Mahajan. et, 26(6):659-666, 2010. [doi]

2008

On Chip Jitter Measurement through a High Accuracy TDCAkhil Garg, Prashant Dubey. isqed 2008: 844-847 [doi]

2007

Low Area Adaptive Fail-Data Compression Methodology for Defect Classification and Production Phase PrognosisPrashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani. isvlsi 2007: 171-178 [doi]

Built in Defect Prognosis for Embedded MemoriesPrashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani. ddecs 2007: 167-172

GALS Based Shared Test Architecture for Embedded MemoriesPrashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani. iscas 2007: 157-160 [doi]

2006

Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip CostAkhil Garg, Prashant Dubey. dft 2006: 166-174 [doi]

Fuse Area Reduction Based on Quantitative Yield Analysis and Effective Chip CostAkhil Garg, Prashant Dubey. socc 2006: 235-238 [doi]

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