Abstract is missing.
- A 12-bit@40MS/s Gm-C Cascade 3-2 Continuous-Time Sigma-Delta ModulatorRamon Tortosa Navas, Antonio Aceituno, José Manuel de la Rosa, Ángel Rodríguez-Vázquez, Francisco V. Fernández. 1-4 [doi]
- An I/Q Channel Time-Interleaved Band-Pass Sigma-Delta Modulator for a Low-IF ReceiverMinho Kwon, Gunhee Han. 5-8 [doi]
- On the modeling and the stability of continuous-time Sigma-Delta-ModulatorsJens Anders, Wolfgang Mathis. 9-12 [doi]
- Delta-Sigma Analog-to-Digital Conversion via Time-Mode Signal ProcessingChristopher S. Taillefer, Gordon W. Roberts. 13-16 [doi]
- A 1.2V 130µA 10-bit MOS-Only Log-Domain Sigma Delta ModulatorXavier Redondo, Jofre Pallares, Francisco Serra-Graells. 17-20 [doi]
- Living and Dealing with RF Impairments in Communication TransceiversEdiz Çetin, Izzet Kale, Richard C. S. Morling. 21-24 [doi]
- 3.9G Radio Reception with SC-FDMA Waveforms Under I/Q ImbalanceLauri Anttila, Mikko Valkama, Markku Renfors. 25-28 [doi]
- Blind I/Q Imbalance Compensation in Multipath EnvironmentsPiotr Rykaczewski, Friedrich Jondral. 29-32 [doi]
- On the Impact of I/Q Imbalance in Multi-Carrier Systems for Different Channel ScenariosMarcus Windisch, Gerhard Fettweis. 33-36 [doi]
- On the Joint Compensation of IQ Imbalances and Phase Noise in MIMO-OFDM SystemsQiyue Zou, Alireza Tarighat, Ali H. Sayed. 37-40 [doi]
- Distributed Video Coding with Spatial Correlation Exploited Only at the DecoderMei Guo, Yan Lu, Feng Wu, Shipeng Li, Wen Gao. 41-44 [doi]
- Peak Transform for Efficient Image Representation and CodingZhihai He. 45-48 [doi]
- Rate Control for Hierarchical B-picture Coding with Scaling-factorsLong Xu, Wen Gao, Xiangyang Ji, Debin Zhao. 49-52 [doi]
- Block-Interleaved Error-Resilient Entropy CodingYong Fang, Lu Yu. 53-56 [doi]
- A Perceptual Coding Method based on the Luma Sensitivity ModelShilin Xu, Li Yu, Guangxi Zhu. 57-60 [doi]
- Fundamental Performance Limits in Lossy Polyphase Systems: Apparent Power and Optimal CompensationHanoch Lev-Ari, Alex M. Stankovic. 61-64 [doi]
- Computing Criticality of Lines in Power SystemsAli Pinar, Adam Reichert, Bernard C. Lesieutre. 65-68 [doi]
- Probability Distribution of Blackouts in Complex Power NetworksBei Gou, Hui Zheng, Weibiao Wu, Xingbin Yu. 69-72 [doi]
- Analog Emulation of a Reconfigurable Tap Changing TransformerAaron St. Leger, Juan C. Jimenez, Agung Fu, Sanal Djimbinov, Sa Em Soeurn, Sun Sit Lwin, Chika O. Nwankpa. 73-76 [doi]
- Application of Two-Layered Tabu Search to Optimal Allocation of D-FACTS for Uncertain Wind Power GenerationHiroyuki Mori, Hidenobu Tani. 77-80 [doi]
- Design and Optimization of a Capacitive Micromachined Ultrasonic Transducer Micro-Array for Near Field SensingClyde Clarke, Carl White, Ralph Etienne-Cummings. 81-84 [doi]
- A CMOS-Based Capacitive Sensor for Laboratory-On-Chips: Design and Experimental ResultsEbrahim Ghafar-Zadeh, Mohamad Sawan. 85-88 [doi]
- Piezo-powered floating gate injector for self-powered fatigue monitoring in biomechanical implantsNizar Lajnef, Shantanu Chakrabartty, Niell Elvin, Alex Elvin. 89-92 [doi]
- A novel current scaling active pixel sensor with correlated double sampling readout circuit for real time medical x-ray imagingNader Safavian, G. Reza Chaji, S. J. Ashtiani, Arokia Nathan, John A. Rowlands. 93-96 [doi]
- DSP implementation of a low-complexity algorithm for real-time automated vessel detection in images of the fundus of the human retinaAndrea Anzalone, Federico Bizzarri, Paolo Camera, Luca Petrillo, Marco Storace. 97-100 [doi]
- A Novel Interference Supression Technique employing Complex Adaptive ICA for Time-Varying Channels in Diversity Wireless QAM ReceiversRaghuram Ranganathan, Wasfy B. Mikhael. 101-104 [doi]
- Adaptive IIR Filtering via a Recursive Total Instrumental Variable AlgorithmDa-Zheng Feng, Wei Xing Zheng. 105-108 [doi]
- Generalized Blind Mismatch Correction for a Two-Channel Time-Interleaved ADC: Analytic ApproachMunkyo Seo, Mark J. W. Rodwell. 109-112 [doi]
- An Adaptive Low Rank Algorithm for Semispherical Antenna ArraysJeffrey A. Foutz, Andreas S. Spanias. 113-116 [doi]
- New Normalized LMS Algorithms Based on the Kalman FilterPaulo Alexandre Crisóstomo Lopes, José Beltran Gerald. 117-120 [doi]
- Reduction of Register File Delay Due to Process Variability in VLIW Embedded ProcessorsPraveen Raghavan, José L. Ayala, David Atienza, Francky Catthoor, Giovanni De Micheli, Marisa López-Vallejo. 121-124 [doi]
- Non Return Mobile Logic FamilyHéctor Pettenghi, Maria J. Avedillo, José M. Quintana. 125-128 [doi]
- A Four-Resonant-Tunneling-Diode (4RTD) NAND/NOR Logic GateTakao Waho, Akinori Yamada, Hiroki Okuyama, Victor Khorenko, Thai Do, Werner Prost. 129-132 [doi]
- Synthesis of Finite State Machines with Magnetic Domain Wall LogicJacques-Olivier Klein, Eric Belhaire, Claude Chappert, Florent Ouchet, Russell Cowburn, Dan Read, Dorothee Petit. 133-136 [doi]
- A Self-Biased Operational Transconductance Amplifier in 0.18 micron 3D SOI-CMOSJennifer Blain Christen, Andreas G. Andreou. 137-140 [doi]
- Soft Error Mitigation in Switch Modules of SRAM-based FPGAsHamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew. 141-144 [doi]
- Efficient Thermal Via Planning for Placement of 3D Integrated CircuitsJing Li, Hiroshi Miyashita. 145-148 [doi]
- Design for Secure Test - A Case Study on Pipelined Advanced Encryption StandardYouhua Shi, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki. 149-152 [doi]
- Embedded Jitter Measurement of High-speed I/O SignalsXueqing Wang, William R. Eisenstadt, Robert M. Fox. 153-156 [doi]
- GALS Based Shared Test Architecture for Embedded MemoriesPrashant Dubey, Akhil Garg, Sravan Kumar Bhaskarani. 157-160 [doi]
- A Genetic Algorithm for Scheduling Tasks onto Dynamically Reconfigurable HardwareYang Qu, Juha-Pekka Soininen, Jari Nurmi. 161-164 [doi]
- Real-Time Extraction of Maximally Stable Extremal Regions on an FPGAFredrik Kristensen, W. James MacLean. 165-168 [doi]
- Programmable Floating Gate FPAA Switches Are Not Dead WeightChristopher M. Twigg, Jordan D. Gray, Paul E. Hasler. 169-172 [doi]
- Programmable Conductance Switches for FPAAsChristopher M. Twigg, Paul E. Hasler. 173-176 [doi]
- An OTA-based Large-Scale Field Programmable Analog Array (FPAA) for faster On-Chip Communication and ComputationPaul E. Hasler, Christopher M. Twigg. 177-180 [doi]
- A 1Gb/s Optical Transceiver Array Chipset for Automotive Wired InterconnectsBoo-Young Choi, Jung-Won Han, Sung Min Park, Kang Yeob Park, Won-S. Oh, J.-C. Choi. 181-184 [doi]
- A Novel Tri-State Binary Phase DetectorDavid Rennie, Manoj Sachdev. 185-188 [doi]
- Crosstalk-Aware Transmitter Pulse-Shaping for Parallel Chip-to-Chip LinksMike Bichan, Anthony Chan Carusone. 189-192 [doi]
- A 0.25-um BiCMOS Feed Foward Equalizer Using Active Delay Line for Backplane CommunicationHyoungsoo Kim, Franklin Bien, Youngsik Hur, Soumya Chandramouli, Jeongwon Cha, Edward Gebara, Joy Laskar. 193-196 [doi]
- Digitally Controlled 10-Gb/s Adjustable Delay Line for Adaptive Filter Design in standard CMOS TechnologyFranklin Bien, Soumya Chandramouli, Hyoungsoo Kim, Edward Gebara, Joy Laskar. 197-200 [doi]
- Generation of White Noise by Using Chaos in Practical Phase-Locked Loop Integrated Circuit ModuleTetsuro Endo, Jun Yokota. 201-204 [doi]
- Reverse-Time Chaos from a Randomly Driven FilterNed J. Corron, Scott T. Hayes, Shawn D. Pethel, Jonathan N. Blakely. 205-208 [doi]
- Switching Phase States of Chaotic Circuits Coupled by Time-Varying ResistorYoko Uwate, Yoshifumi Nishio. 209-212 [doi]
- ADCs, Chaos and TRNGs: a Generalized View Exploiting Markov Chain Lumpability PropertiesSergio Callegari, Gianluca Setti. 213-216 [doi]
- Design of Multi-Directional Multi-Scroll Chaotic Attractors Based on Fractional Differential SystemsWeihua Deng, Jinhu Lu. 217-220 [doi]
- A Compact High Current Efficiency Low-Voltage MOS Transconductor with Nearly Constant Input Voltage RangeChutham Sawigun, Jirayuth Mahattanakul. 221-224 [doi]
- A Three-Stage Amplifier with Quenched Multipath Frequency Compensation for All Capacitive LoadsJingjing Hu, Johan H. Huijsing, Kofi A. A. Makinwa. 225-228 [doi]
- Low-Power Digitally Controlled CMOS Source Follower Variable AttenuatorT. Hui Teo, Wooi Gan Yeoh. 229-232 [doi]
- Predictive Switched-Capacitor Track-and-Hold Amplifier with Improved LinearityHirokazu Yoshizawa, Gabor C. Temes. 233-236 [doi]
- 150 µA CMOS Transconductor with 82 dB SFDRSalvatore Pennisi, Giuseppe Scotti, Alessandro Trifiletti. 237-240 [doi]
- A Method for the Discrete-Time Simulation of Continuous-Time Sigma-Delta ModulatorsMatthias Keller, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli. 241-244 [doi]
- A DEM Scheme for I/Q Mismatch Compensation in Multi-Bit CT Delta Sigma ModulatorChi-Tung Ko, Kong-Pang Pun. 245-248 [doi]
- Noise-Coupled Multi-Cell Delta-Sigma ADCsKyehyung Lee, Gabor C. Temes, Franco Maloberti. 249-252 [doi]
- Continuous Compensation of Binary-Weighted DAC Nonlinearities in Bandpass Delta-Sigma ModulatorsGhyslain Gagnon, Leonard MacEachern. 253-256 [doi]
- Mixed-Order Sturdy MASH Delta-Sigma ModulatorNima Maghari, Sunwoo Kwon, Gabor C. Temes, Un-Ku Moon. 257-260 [doi]
- Carrier frequency synchronization for mobile television receiversTimo Roman, Visa Koivunen. 261-264 [doi]
- Efficient Transmitter Self-Calibration and Amplifier Linearization TechniquesXinping Huang, Mario Caron. 265-268 [doi]
- Digital Compensation of Frequency Dependent Imperfections in Direct Conversion I-Q ModulatorsAntonio Cantoni, John Tuthill. 269-272 [doi]
- Multipath Polyphase Circuits and their Application to RF TransceiversEric A. M. Klumperink, Rameswor Shrestha, Eisse Mensink, Gerard Wienk, Zhiyu Ru, Bram Nauta. 273-276 [doi]
- Adaptive Pre-Distortion of Nonlinear Systems Using Out-of-Band Energy MinimizationKutluyil Dogancay. 277-280 [doi]
- A Universal Approach to Developing Fast Algorithm for Simplified Order-16 ICTJie Dong, King Ngi Ngan, Chi-Keung Fong, Wai-kuen Cham. 281-284 [doi]
- A PD Feed-back Rate Control Algorithm for Multiple Video Object CodingJiancong Luo, Yu Sun, Ishfaq Ahmad. 285-288 [doi]
- On Model Parameter Estimation for H.264/AVC Rate ControlJianpeng Dong, Nam Ling. 289-292 [doi]
- Chroma Coding Efficiency Improvement with Context Adaptive Lagrange Multiplier (CALM)Jun Zhang, Xiaoquan Yi, Nam Ling, Weijia Shang. 293-296 [doi]
- Image Compression using 2D Dual-tree Discrete Wavelet Transform (DDWT)Jing-yu Yang, Wenli Xu, Qionghai Dai, Yao Wang. 297-300 [doi]
- A PEEC approach for circular spiral inductive components modelingPhilippe Artillan, Bruno Estibals, Alain Salles, Jean Abboud, Pierre Aloisi, Corinne Alonso. 301-304 [doi]
- An Integrated Switching Power Converter with a Hybrid Pulse-Train/PWM ControlFeng Luo, Dongsheng Ma. 305-308 [doi]
- Modeling the Substrate Noise Injected by a DC-DC ConverterVincent Binet, Yvon Savaria, Michel Meunier, Yves Gagnon. 309-312 [doi]
- Digital Inverse Timing Generator with Wide Dynamic RangeBharath Balaji Kannan, Khai D. T. Ngo. 313-316 [doi]
- Design of Maximum-Efficiency Integrated Voltage DoublerAlessandro Cabrini, L. Gobbi, Guido Torelli. 317-320 [doi]
- A Low-Noise Preamplifier with Adjustable Gain and Bandwidth for Biopotential Recording ApplicationsMing Yin, Maysam Ghovanloo. 321-324 [doi]
- An Experimental Study of Voltage, Current, and Charge Controlled Stimulation Front-End CircuitryJim Simpson, Maysam Ghovanloo. 325-328 [doi]
- A New RF Radiometer for Absolute Noninvasive Temperature Sensing in Biomedical ApplicationsAbdEl-Monem M. El-Sharkawy, Paul-Peter Sotiriadis, Paul A. Bottomley, Ergin Atalar. 329-332 [doi]
- A 2.5-V 4-µW Low-Power Delta-Sigma Modulator for Implantable Cardiac Pacemaker with Periodic Bias Current Reduction TechniqueChae-Ryung Kim, Yu-Ri Kang, Young-Jae Min, Soo-Won Kim. 333-336 [doi]
- A Novel Variable-Gain Micro-Power Band-Pass Auto-Zeroing CMOS AmplifierChiu-Hsien Chan, Jack Wills, Jeff LaCoss, John J. Granacki, John Choma Jr.. 337-340 [doi]
- Fast Basis Selection and Instantaneous Frequency Tracking for Audio Signal Analysis and SynthesisHuimin Chen, Dimitrios Charalampidis. 341-344 [doi]
- Emotion Recognition Using Novel Speech Signal FeaturesTalieh Seyed Tabatabaei, Sridhar Krishnan, Aziz Guergachi. 345-348 [doi]
- An Identification Technique for Noisy ARMA Systems in Correlation DomainShaikh Anowarul Fattah, Wei-Ping Zhu, M. Omair Ahmad. 349-352 [doi]
- Real-Time DSP Implementation of a Subband Beamforming Algorithm for Dual Microphone Speech EnhancementZohra Yermeche, Benny Sallberg, Nedelko Grbic, Ingvar Claesson. 353-356 [doi]
- Novel Non-linear Inverse Quantization Algorithm and its Architecture for Digital Audio CodecsHan Jae Hee, Myung Hoon Sunwoo, Jong Ha Moon. 357-360 [doi]
- Fault Tolerance Analysis of NoC ArchitecturesTeijo Lehtonen, Pasi Liljeberg, Juha Plosila. 361-364 [doi]
- Multiple Upsets Tolerance in SRAM MemoryCostas Argyrides, Hamid R. Zarandi, Dhiraj K. Pradhan. 365-368 [doi]
- A Miniaturized Delay Line based on Slow-Wave SubstratesThemistoklis Prodromakis, Christos Papavassiliou, George Konstantinidis. 369-372 [doi]
- Gigascale System Design of Sensor Networks for Active VolcanoesWai-Chi Fang, Sharon Kedar. 373-376 [doi]
- Open Two-State Quantum Systems Solved by Harmonic BalancePier Paolo Civalleri, Marco Gilli, Michele Bonnin. 377-380 [doi]
- Characterization of a Fault-tolerant NoC RouterSumit D. Mediratta, Jeffrey T. Draper. 381-384 [doi]
- Fast Fair Crossbar Scheduler for On-chip RouterShyue-Wen Yang, Ming-Hwa Sheu, Chun-Kai Yeh, Chih-Yuen Wen, Chih-Chieh Lin, Wen-Kai Tsai. 385-388 [doi]
- Evaluation of Algorithms for Low Energy Mapping onto NoCsCésar A. M. Marcon, Edson I. Moreno, Ney Laert Vilar Calazans, Fernando Gehm Moraes. 389-392 [doi]
- An Information Theory Approach to Power - Optimal Trafic Routing in Networks on ChipsPaul-Peter Sotiriadis. 393-396 [doi]
- Binary-Truncated CDMA-Based On-Chip NetworkIk-Jae Chun, Tae Moon Roh, Bo-Gwan Kim. 397-400 [doi]
- Holographic memory reconfigurable VLSIMinoru Watanabe, Fuminori Kobayashi. 401-404 [doi]
- Area and Throughput Aware Comparator Networks Optimization for Parallel Data Processing on FPGAChristophe Layer, Daniel Schaupp, Hans-Jörg Pfleiderer. 405-408 [doi]
- Rapid C to FPGA Prototyping with Multithreaded Emulation EngineShin-Kai Chen, Bing-Shiun Wang, Tay-Jyi Lin, Chih-Wei Liu. 409-412 [doi]
- Visualization of SystemC DesignsChristian Genz, Rolf Drechsler, Gerhard Angst, Lothar Linhard. 413-416 [doi]
- Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem ApplicationsSayed Hafizur Rahman, Asif Iqbal Ahmed, Otmane Aït Mohamed. 417-420 [doi]
- A 0.18-µm CMOS Squarer Circuit for a Non-Coherent UWB ReceiverAndrea Gerosa, M. Soldan, Alessandro Bevilacqua, Andrea Neviani. 421-424 [doi]
- A Fully Integrated Concurrent Dual-Band Low Noise Amplifier with Suspended Inductors in SiGe 0.35µm BiCMOS TechnologyYu-Tso Lin, Tao Wang, Shey-Shi Lu. 425-428 [doi]
- A Low-Power Frequency Synthesizer with Quadrature Signal Generation for 2.4 GHz Zigbee Transceiver ApplicationsRangakrishnan Srinivasan, Didem Zeliha Turker, Sang Wook Park, Edgar Sánchez-Sinencio. 429-432 [doi]
- A Low-Power CMOS Low-IF Receiver Front-End for 2450-MHz Band IEEE 802.15.4 ZigBee StandardSaeed Sarhangian, Seyed Mojtaba Atarodi. 433-436 [doi]
- A Power-Optimized CMOS Quadrature VCO with Wide-Tuning Range for UWB ReceiversZhujin Zhou, Ning Li, Wei Li, Junyan Ren. 437-440 [doi]
- The Composition Rule for Multivariate Volterra Operators and its Application to Circuit AnalysisHeinz Koeppl. 441-444 [doi]
- Studying Nonlinear Dynamical Systems on a Reconfigurable Analog PlatformKofi M. Odame, Christopher M. Twigg, Arindam Basu, Paul E. Hasler. 445-448 [doi]
- Per-Element Decompostion in Distortion AnalysisGuoji Zhu, Ajoy Opal. 449-452 [doi]
- Modeling the Telephone Call NetworkWai Man Tam, Francis C. M. Lau, C. K. Michael Tse. 453-456 [doi]
- Novel Analysis of Phase Noise in OscillatorsAndrew Buschmeier, Douglas Frey. 457-460 [doi]
- Low-Voltage Linearly Tunable CMOS Transconductor with Common-Mode FeedforwardBelén Calvo, Santiago Celma, Maria Teresa Sanz, Juan Pablo Alegre. 461-464 [doi]
- THD+Noise Estimation in Class-D AmplifiersBurak Kelleci, Edgar Sánchez-Sinencio, Aydin I. Karsilayan. 465-468 [doi]
- Two-Stage OTA Design Based on Settling-Time ConstraintsGianluca Giustolisi. 469-472 [doi]
- A Very Linear OTA with V-I Conversion based on Quasi-Floating MOS ResistorRamón González Carvajal, Juan Antonio Gómez Galán, Antonio B. Torralba, C. Lujan-Martinez, Jaime Ramírez-Angulo, Antonio J. López-Martín. 473-476 [doi]
- A Robust Rail-to-Rail Input Stage with Constant-gm and Constant Slew Rate Using a Novel Level ShifterTongyu Song, Shouli Yan. 477-480 [doi]
- A Segmented Data-Weighted-Averaging TechniqueZhenyong Zhang, Gabor C. Temes. 481-484 [doi]
- A Digital-Summing Feedforward Sigma-Delta Modulator and its Application to a Cascade ADCYi Tang, Subhanshu Gupta, Jeyanandh Paramesh, David J. Allstot. 485-488 [doi]
- A 0.9mA 95dB Sigma Delta Modulator for Digital RF Hearing Aid in 0.35µm CMOSLong-Xi Chang, Day-Uei Li, Chi-Chen Chung, Tim-Kuei Shia. 489-492 [doi]
- A Theoretical Analysis of Split Delta-Sigma ADCsSudhakar Pamarti. 493-496 [doi]
- Discrete-Time Modeling of Clock Jitter in Continuous-Time Delta Sigma ModulatorsPhilip M. Chopp, Anas A. Hamoui. 497-500 [doi]
- Algorithmic aspects in RF Circuit SimulationFlorin Constantinescu, Angelo Brambilla, Giancarlo Storti Gajani, Miruna Nitescu. 501-504 [doi]
- Nonlinear, Transient Simulation of Distributed RF Circuits using Discrete-Time ConvolutionThomas J. Brazil. 505-508 [doi]
- An inverse method of characteristics for analyzing circuits with widely separated time-scalesHans Georg Brachtendorf, Angelika Bunse-Gerstner, Barbara Lang, Rainer Laur. 509-512 [doi]
- Noise Analysis Problems and Techniques for RF Electronic Circuits and Optical Fiber Communication SystemsAlper Demir. 513-516 [doi]
- Multi-Time Method Based on State Equations for RF Circuit AnalysisMihai Iordache, Lucia Dumitriu. 517-520 [doi]
- A Comparative Study of Compensation Techniques in Directional DCT sJingjing Fu, Bing Zeng. 521-524 [doi]
- Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing EngineTakeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. 525-528 [doi]
- Macroblock-level Reduced Resolution Video Coding Allowing Adaptive DCT Coefficients SelectionQiang Hao, Xiangyang Ji, Qingming Huang, Debin Zhao, Wen Gao, Xilin Chen. 529-532 [doi]
- High-Accuracy and Low-Complexity Fixed-Point Inverse Discrete Cosine Transform Based on AAN s Fast AlgortihmHonggang Qi, Wen Gao. 533-536 [doi]
- Macroblock-Level Adaptive Scan Scheme for Discrete Cosine Transform CoefficientsLi Zhang, Wen Gao, Qiang Wang, Debin Zhao. 537-540 [doi]
- Output Characteristics of Class E Amplifier With Nonlinear Shunt Capacitance Versus Supply VoltageTadashi Suetsugu, Marian K. Kazimierczuk. 541-544 [doi]
- Dynamic Droop Scaling for Improving Current Sharing Performance in a System with Multiple SuppliesHsin-Hsin Ho, Ke-Horng Chen, Wen Tsao Chen. 545-548 [doi]
- Designing an Accurate and Robust LC-Compliant Asynchronous Sigma Delta Boost DC-DC ConverterNeeraj Keskar, Gabriel A. Rincón-Mora. 549-552 [doi]
- Class DE Inverter with Asymmetric Shunt CapacitorsHirotaka Koizumi, Kosuke Kurokawa. 553-556 [doi]
- Power Harvesting With PZT CeramicsHong Chen, Chen Jia, Chun Zhang, Zhihua Wang, Chunsheng Liu. 557-560 [doi]
- Design Strategies for Multi-Channel Low-Noise Recording SystemsRobert Rieger, Yen-Yow Pan, John Taylor. 561-564 [doi]
- Wireless Stimulus-Reflex Detection for Neonatal MonitoringCraig Hyatt. 565-568 [doi]
- Novel Charge-Metering Stimulus Amplifier for Biomimetic Implantable ProsthesisXiang Fang, Jack Wills, John J. Granacki, Jeff LaCoss, Artak Arakelian, James D. Weiland. 569-572 [doi]
- Charge Balancing in Functional Electrical Stimulators: A Comparative StudyMaurits Ortmanns. 573-576 [doi]
- A 70dB Gain Low-Power Band-Pass Amplifier for Bio-Signals Sensing ApplicationsCheng Chih Liu. 577-580 [doi]
- A Class of Cosine-Modulated Filter Banks with Multiple Prototype FiltersChao Wu, Wei-Ping Zhu, M. N. S. Swamy. 581-584 [doi]
- Design of Cosine-Modulated Pseudo-QMF Banks Using Semidefinite Programming RelaxationH. H. Kha, H. D. Tuan, T. Q. Nguyen. 585-588 [doi]
- Beamforming of Temporally-Broadband-Bandpass Plane Waves using Real Polyphase 2-D FIR Trapezoidal FiltersThushara K. Gunaratne, Leonard T. Bruton. 589-592 [doi]
- Filtering of Discrete Linear Repetitive Processes with H and l2-l PerformanceLigang Wu, James Lam, Wojciech Paszke, Krzysztof Galkowski, Eric Rogers, Anton Kummert. 593-596 [doi]
- Revisiting the Absolutely Minimal Realization for Two-dimensional Digital FiltersZhiping Lin, Li Xu, Yoshihisa Anazawa. 597-600 [doi]
- Sensor Integration in Autonomous SystemsBertram Emil Shi, Csaba Rekeczky. 601-604 [doi]
- A Systems View of a Neuromorphic VLSI Echolocation SystemTimothy K. Horiuchi, Matthew Cheely. 605-608 [doi]
- Integrating high-level sensor features via STDP for bio-inspired navigationPaolo Arena, Luigi Fortuna, Mattia Frasca, Luca Patané, C. Sala. 609-612 [doi]
- Sensor-based Dynamic Control of the Central Pattern Generator for LocomotionFrancesco Tenore, R. Jacob Vogelstein, Ralph Etienne-Cummings. 613-616 [doi]
- Elastic Grid Based Analysis of Motion Field for Object-Motion Detection in Airborne Video FlowsGergely Balazs Soos, Csaba Rekeczky. 617-620 [doi]
- Delay and Clock Skew Variation due to Coupling Capacitance and InductanceAbinash Roy, Noha H. Mahmoud, Masud H. Chowdhury. 621-624 [doi]
- Design of Reversible Sequential Elements With Feasibility of Transistor ImplementationHimanshu Thapliyal, A. Prasad Vinod. 625-628 [doi]
- Crosstalk Effects in Event-Driven Self-Timed Circuits Designed With 90nm CMOS TechnologySyed Rafay Hasan, Yvon Savaria. 629-632 [doi]
- A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based DesignsBill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria. 633-636 [doi]
- Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-FlopsO. Sarbishei, Mohammad Maymandi-Nejad. 637-640 [doi]
- Quasi-Resonant Interconnects: A Low Power Design MethodologyJonathan Rosenfeld, Eby G. Friedman. 641-644 [doi]
- Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed SkewSherif A. Tawfik, Volkan Kursun. 645-648 [doi]
- Current Mode On-Chip Interconnect using Level-Encoded Two-Phase Dual-Rail EncodingEthiopia Nigussie, Juha Plosila, Jouni Isoaho. 649-652 [doi]
- Wavelet-Based Interpolation Point Selection for Multi-Shifted ArnoldiMehboob Alam, Arthur Nieuwoudt, Yehia Massoud. 653-656 [doi]
- A Novel Active Decoupling Capacitor Design in 90nm CMOSXiongfei Meng, Karim Arabi, Resve Saleh. 657-660 [doi]
- On the degree of MIMO systemsP. P. Vaidyanathan. 661-664 [doi]
- High Speed Sphere Decoding Based on Vertically Incremental ComputationSe-Hyeon Kang, In-Cheol Park. 665-668 [doi]
- Beamforming MIMO Receiver with Reduced Hardware ComplexityOmid Oliaei. 669-672 [doi]
- VLSI Implementation of a Lattice-Reduction Algorithm for Multi-Antenna Broadcast PrecodingAndreas Burg, Dominik Seethaler, Gerald Matz. 673-676 [doi]
- MIMO Transceiver Design Based on a Modified Geometric Mean DecompositionWen-Chih Kan, Gerald E. Sobelman. 677-680 [doi]
- Improved Dynamic Model of Fast-Settling Linear-in-dB Automatic Gain Control CircuitHsuan-Yu Marcus Pan, Lawrence E. Larson. 681-684 [doi]
- A Simplicial PWL Integrated Circuit RealizationMartin Di Federico, Pedro Julian, Tomaso Poggi, Marco Storace. 685-688 [doi]
- Class AB Pseudo-Differential CMOS Squarer CircuitJaime Ramírez-Angulo, Raghavender Chintham, Antonio J. López-Martín, Ramón González Carvajal. 689-692 [doi]
- Maximum-Period PRNGs Derived From A Piecewise Linear One-Dimensional MapTommaso Addabbo, Massimo Alioto, Ada Fort, Santina Rocchi, Valerio Vignoli. 693-696 [doi]
- From n-scroll to n-scroll attractors: A general structure based on Chua s circuit frameworkSimin Yu, Wallace Kit-Sang Tang, Guanrong Chen. 697-700 [doi]
- Power Supply Noise in Bang-Bang Control Class D AmplifierTong Ge, Joseph Sylvester Chang, Wei Shu. 701-704 [doi]
- Ultra-Low-Voltage, Low-Power, High-Speed Operational Amplifiers Using Body-Driven Gain-Boosting TechniqueS. Alireza Zabihian, Reza Lotfi. 705-708 [doi]
- Integrated Circuit Trimming Technique for Offset Reduction in a Precision CMOS AmplifierRahul Singh, Yves Audet, Yves Gagnon, Yvon Savaria. 709-712 [doi]
- Highly Linear Bipolar Transconductor For Broadband High-Frequency Applications with Improved Input Voltage SwingHsuan-Yu Marcus Pan, Lawrence E. Larson. 713-716 [doi]
- A New High-Speed Class-AB Current-Mode CircuitBehnam Sedighi, Mehrdad Sharif Bakhtiar. 717-720 [doi]
- On the Implicit Anti-Aliasing Feature of Continuous-Time Multistage Noise-Shaping Sigma-Delta ModulatorsMatthias Keller, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli. 721-724 [doi]
- Design of a 130-nm CMOS Reconfigurable Cascade Sigma Delta Modulator for GSM/UMTS/BluetoothAlonso Morgado, Rocio del Río, José Manuel de la Rosa. 725-728 [doi]
- Tonality Index of Sigma-Delta Modulators : A Psychoacoustics Model Based ApproachJaswinder Lota, Mohammed Al-Janabi, Izzet Kale. 729-732 [doi]
- A High-Speed Delta-Sigma Modulator with Relaxed DEM Timing RequirementSunwoo Kwon, Un-Ku Moon. 733-736 [doi]
- A 10-bit 2GHz Current-Steering CMOS D/A ConverterLing Yuan, Weining Ni, Yin Shi, Foster F. Dai. 737-740 [doi]
- Design Considerations for Future RF CircuitsBehzad Razavi. 741-744 [doi]
- Receiver Front-End Circuits for Future Generations of Wireless CommunicationsM. Sanduleanu, M. Vidojkovic, Vojkan Vidojkovic, Arthur H. M. van Roermund, Aleksandar Tasic. 745-748 [doi]
- Companding Baseband Switched Capacitor Filters and ADCs for WLAN ApplicationsVaibhav Maheshwari, Wouter A. Serdijn, John R. Long. 749-752 [doi]
- Multifunctional RF Transmitters for Next Generation Wireless TransceiversLawrence Larson, Peter Asbeck, Donald Kimball. 753-756 [doi]
- Low-Complexity Ultra Wideband CommunicationsJohn F. M. Gerrits, John R. Farserotu, John R. Long. 757-760 [doi]
- Analysis of an SOC Architecture for MPEG Reconfigurable Video Coding FrameworkJer-Min Hsiao, Chun-Jen Tsai. 761-764 [doi]
- Triangle-Level Depth Filter Method for Bandwidth Reduction in 3D Graphics HardwareJae-Sung Yoon, Chang-Hyo Yu, Donghyun Kim, Lee-Sup Kim. 765-768 [doi]
- CREMA: A Parallel Hardware Raytracing MachineUlf Ochsenfahrt, Ralf Salomon. 769-772 [doi]
- A Real Time and Low Cost Hardware Architecture for Video Abstraction SystemLi-Chuan Chang, Yen-Sung Chen, Rung-Wen Liou, Chih-Hung Kuo, Chia-Hung Yeh, Bin-Da Liu. 773-776 [doi]
- VLSI Implementation for Portable Application Oriented MPEG-4 Audio CodecPeilin Liu, Lingzhi Liu, Ning Deng, Xuan Fu, Jiayan Liu, Qianru Liu, Guocheng Zhang, Bin He. 777-780 [doi]
- Adaptive Variable Switching Frequency Digital Controller Algorithm to Optimize EfficiencyWisam Al-Hoor, Jaber A. Abu-Qahouq, Lilly Huang, Issa Batarseh. 781-784 [doi]
- Feed-Forward Pulse Width Modulation for High Line Regulation Buck or Boost ConvertersHuan-Jen Yang, Ke-Horng Chen, Yung-Pin Lee. 785-788 [doi]
- Bifurcation of multiple-input parallel dc-dc converters with dynamic winner-take-all switchingYuki Ishikawa, Toshimichi Saito. 789-792 [doi]
- Computer-Aided Average-Value Modeling of Fourth-Order PWM DC-DC ConvertersAli Davoudi, Juri Jatskevich, Patrick L. Chapman. 793-796 [doi]
- Hopf-Type Intermediate-Scale Bifurcation in Single-Stage Power-Factor-Correction Power SuppliesDong Dai, Shengnan Li, Xikui Ma, Chi K. Michael Tse. 797-800 [doi]
- Incorporating Back Telemetry in a Full-Wave CMOS Rectifier for RFID and Biomedical ApplicationsSuresh Atluri, Maysam Ghovanloo. 801-804 [doi]
- Low-Power Low-Noise Neural Amplifier in 0.18µm FD-SOI TechnologyDonghwi Kim, Ridha Kamoua, Milutin Stanacevic. 805-808 [doi]
- Wireless Implant Communications for Biomedical Monitoring Sensor NetworkMarc Simon Wegmueller, Martin Hediger, Thomas Kaufmann, Felix Bürgin, Wolfgang Fichtner. 809-812 [doi]
- A CMOS Contact Imager for Cell Detection in Bio-Sensing ApplicationsTerence Tam, Graham A. Jullien, Orly Yadid-Pecht. 813-816 [doi]
- A Matching Technique for Biphasic Stimulation PulseEdward K. F. Lee, Anthony Lam. 817-820 [doi]
- A Simultaneous Div-Curl 2D Clifford Fourier Transform Filter for Enhancing Vortices, Sinks and Sources in Sampled 2D Vector Field ImagesHoda Mohammadzade, Leonard T. Bruton. 821-824 [doi]
- Direct Batch Evaluation of Desirable Eigenvectors of the DFT Matrix by Constrained OptimizationMagdy T. Hanna. 825-828 [doi]
- An Efficient Identification Algorithm for FIR Filtering with Noisy DataDa-Zheng Feng, Wei Xing Zheng. 829-832 [doi]
- A New Minimum Variance Spectral Estimation Method for Analyzing Click-Evoked Otoacoustic EmissionsZ. G. Zhang, S. C. Chan, V. W. Zhang, B. McPherson. 833-836 [doi]
- A novel motion detection pointing device Using a binary CMOS image sensorHee Ju Park, Kyung Bum Kim, Jeong Hun Kim, Suki Kim. 837-840 [doi]
- Spike Events Processing for Vision SystemsRafael Serrano-Gotarredona, Teresa Serrano-Gotarredona, Antonio Acosta-Jimenez, Alejandro Linares-Barranco, Gabriel Jiménez-Moreno, Antón Civit Balcells, Bernabé Linares-Barranco. 841-844 [doi]
- Fast sensory motor control based on event-based hybrid neuromorphic-procedural systemTobi Delbrück, Patrick Lichtsteiner. 845-848 [doi]
- Address-Event Video Streaming over Wireless Sensor NetworksEugenio Culurciello, Joon Hyuk Park, Andreas Savvides. 849-852 [doi]
- Quantifying Input and Output Spike Statistics of a Winner-Take-All Network in a Vision SystemMatthias Oster, Rodney J. Douglas, Shih-Chii Liu. 853-856 [doi]
- High-Speed Serial AER on FPGAHans Kristian Otnes Berge, Philipp Häfliger. 857-860 [doi]
- Mixed Techniques to Protect Precharged Busses against Differential Power Analysis AttacksMassimo Alioto, Massimo Poli, Santina Rocchi, Valerio Vignoli. 861-864 [doi]
- Power Reduction of On-Chip Serial LinksAmit Kedia, Resve Saleh. 865-868 [doi]
- Low-Latency Quasi-Synchronous Transmission Technique for Multiple-Clock-Domain IP ModulesJhao-Ji Ye, You-Gang Chen, I-Chyn Wey, An-Yeu Wu. 869-872 [doi]
- Reconfigurable Heterogeneous Communications and Core Reallocation for Dynamic HW Task ManagementYana Esteves Krasteva, Eduardo de la Torre, Teresa Riesgo. 873-876 [doi]
- Reconfigurable Clock Distribution CircuitryAtanu Chattopadhyay, Zeljko Zilic. 877-880 [doi]
- Adaptive Low/High Voltage Swing CMOS Driver for On-Chip InterconnectsJosé C. García, Juan A. Montiel-Nelson, Saeid Nooshabadi. 881-884 [doi]
- Global Interconnect Optimization in the Presence of On-chip InductanceAbinash Roy, Masud H. Chowdhury. 885-888 [doi]
- A Novel Design Methodology of the On-Chip Power Distribution Network Enhancing the Performance and Suppressing EMI of the SoCHirokazu Tohya, Noritaka Toya. 889-892 [doi]
- Asymmetric clock driver for improved power and noise performancesJavier Castro, Pilar Parra, Manuel Valencia, Antonio J. Acosta. 893-896 [doi]
- Estimation of Capacitive Crosstalk-Induced Short-Circuit EnergyMosin Mondal, Sami Kirolos, Yehia Massoud. 897-900 [doi]
- A High-Speed Pipelined Degree-Computationless Modified Euclidean Algorithm Architecture for Reed-Solomon DecodersSeungbeom Lee, Hanho Lee, Jongyoon Shin, Je Soo Ko. 901-904 [doi]
- Simplified Degree Computationless Modified Euclid s Algorithm and its ArchitectureJaehyun Baek, Myung Hoon Sunwoo. 905-908 [doi]
- Towards Gb/s turbo decoding of product code onto an FPGA deviceCamille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel. 909-912 [doi]
- Low-latency Memory-efficient 150-Mbps Turbo FEC Encoder and DecoderTzu-Chieh Kuo, Alan N. Willson Jr.. 913-916 [doi]
- Efficient Message Passing Architecture for High Throughput LDPC DecoderZhiqiang Cui, Zhongfeng Wang. 917-920 [doi]
- An Efficient Oscillator Design Based on OTA NonlinearityKofi M. Odame, Paul E. Hasler. 921-924 [doi]
- Application of Pulsed Digital Oscillators in reverse mode to eliminate undesired vibrations in high-Q MEMS resonatorsManuel Domínguez, Joan Pons, Jordi Ricart. 925-928 [doi]
- CMOS Current-controlled OscillatorsJunhong Zhao, Chunyan Wang. 929-932 [doi]
- A High-Speed and Low-Power Voltage Controlled Oscillator in 0.18-µm CMOS ProcessMostafa Savadi Oskooei, Ali Afzali-Kusha, Seyed Mojtaba Atarodi. 933-936 [doi]
- A Noise Reduced Digitally Controlled Oscillator Using Complementary Varactor PairsShaohua Wang, Jinguo Quan, Rong Luo, Hao Cheng, Huazhong Yang. 937-940 [doi]
- Highly Linear V/I Converter with Programmable Current MirrorsIvan Padilla, Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio J. López-Martín. 941-944 [doi]
- Electrical Stress-free High Gain and High Swing Analog Buffer Using an Adaptive Biasing SchemeHayg Dabag, Dongwon Seo, Manu Mishra, Josef Hausner. 945-948 [doi]
- A SiGe BiCMOS Variable Gain Amplifier for Cryogenic Temperature ApplicationsTiejun Cao, Hung P. Hoang, Beth O. Woods, H. Alan Mantooth. 949-952 [doi]
- Transient Noise Analysis for Comparator-Based Switched-Capacitor CircuitsAlbert Chow, Hae-Seung Lee. 953-956 [doi]
- A Fully Integrated Architecture for Fast Programming of Floating GatesArindam Basu, Paul E. Hasler. 957-960 [doi]
- Incremetal Spatio-Temporal Feature Extraction and Retrieval for Large Video DatabaseBo Geng, Hong Lu, Xiangyang Xue. 961-964 [doi]
- A Missing Data-based Feature Fusion Strategy for Noise-Robust Automatic Speech Recognition Using Noisy SensorsCenk Demiroglu, David V. Anderson, Mark A. Clements. 965-968 [doi]
- Gait Analysis for Human Identification through Manifold Learning and HMMMing-Hsu Cheng, Meng-Fen Ho, Chung-Lin Huang. 969-972 [doi]
- Efficient Multi-Hypothesis Error Concealment Technique for H.264Kwanwoong Song, Taeyoung Chung, Chang-Su Kim, Young O. Park, Yongdeok Kim, Younghun Joo, Yunje Oh. 973-976 [doi]
- Optimized multi-path routing using dual decomposition for wireless video streamingYifeng He, Ivan Lee, Ling Guan. 977-980 [doi]
- Content-Adaptive Wavelet-Based Scalable Video CodingDionisis Athanasopoulos, Thanos Stouraitis. 981-984 [doi]
- An Object-based Approach to Plenoptic Video ProcessingShing-Chow Chan, Zhi-Feng Gan, Heung-Yeung Shum. 985-988 [doi]
- A Human Vision System based Flash Picture Coding Method for Video CodingQuqing Chen, Zhengang Nie, Zhibo Chen, Xiaodong Gu, Guoping Qiu, Charles Wang. 989-992 [doi]
- Disparity Estimation and Virtual View Synthesis from Stereo VideoJong Dae Oh, Siwei Ma, C. C. Jay Kuo. 993-996 [doi]
- Low-delay View Random Access for Multi-view Video CodingYanwei Liu, Qingming Huang, Debin Zhao, Wen Gao. 997-1000 [doi]
- System Bandwidth Analysis of Multiview Video Coding with Precedence ConstraintPei-Kuei Tsung, Li-Fu Ding, Wei-Yin Chen, Shao-Yi Chien, Tung-Chien Chen, Liang-Gee Chen. 1001-1004 [doi]
- Global Asymptotic Stability of Recurrent Neural Networks with Time Varying DelaysHuanxin Guan, Huaguang Zhang, Zhanshan Wang, Derong Liu. 1005-1008 [doi]
- Upper-Triangulization of Non-Symmetric Matrices Using Sanger s Type Learning SystemsMohammed A. Hasan. 1009-1012 [doi]
- Accurate Modeling of Drain Current Derivatives of MESFET/HEMT Devices for Intermodulation AnalysisAderinto J. Ogunniyi, Stanley L. Henriquez, Caroline W. Karangu, Corey Dickens, Carl White. 1013-1016 [doi]
- Cort-X II: low power element design of a large-scale spatio-temporal pattern clustering systemJie Yuan, Ning Song, Nabil Farhat, Jan Van der Spiegel. 1017-1020 [doi]
- Automatic Detection of Solder Joint Defects on Integrated CircuitsGiuseppe Acciani, Gioacchino Brunetti, Girolamo Fornarelli. 1021-1024 [doi]
- Minimum-Cost Load Balancing Document Distribution in Distributed Web Server SystemsTsukasa Sone, Toshinori Yamada. 1025-1028 [doi]
- Topology design for fast convergence of network consensus algorithmsMing Cao, Chai Wah Wu. 1029-1032 [doi]
- Cellular Automata with Large Channel SeparationsChristopher Jenkins, Jayawant Kakade, Dimitri Kagaris. 1033-1036 [doi]
- Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional UnitsAwni Itradat, M. Omair Ahmad, Ali Shatnawi. 1037-1040 [doi]
- 2-MITE Product-of-Power-Law NetworksShyam Subramanian, David V. Anderson. 1041-1044 [doi]
- DTS: A Tree Based Representation for 3D-Block PackingKunihiro Fujiyoshi, Hidenori Kawai, Keisuke Ishihara. 1045-1048 [doi]
- Further Improve Excellent Graph-Based FPGA Technology Mapping by RewiringWai-Chung Tang, Wing-Hang Lo, Yu-Liang Wu. 1049-1052 [doi]
- Thermal Modeling and Temperature Driven Placement for FPGAsShilpa Bhoj, Dinesh Bhatia. 1053-1056 [doi]
- Two Clustering Preprocessing Techniques for Large-Scale CircuitsLaleh Behjat, Jianhua Li, L. Rakai, Jie Huang. 1057-1060 [doi]
- Design Exploration of a Thermal Management Unit for Dynamic Control of Temperature-Induced Clock SkewKarthik Duraisami, Prassanna Sithambaram, Ashoka Visweswara Sathanur, Alberto Macii, Enrico Macii, Massimo Poncino. 1061-1064 [doi]
- Programmable Routing Tables for Degradable Torus-Based Networks on ChipsA. Shahabi, Nima Honarmand, Zainalabedin Navabi. 1065-1068 [doi]
- A Study on Impact of Leakage Current on Dynamic PowerAshesh Rastogi, Kunal P. Ganeshpure, Sandip Kundu. 1069-1072 [doi]
- Periodic Steady-State Analysis of Oscillators with a Specified Oscillation FrequencyIgor Vytyaz, David C. Lee, Suihua Lu, Amit Mehrotra, Un-Ku Moon, Kartikeya Mayaram. 1073-1076 [doi]
- Effective Acceleration of Iterative Slack Distribution ProcessXinjie Wei, Yici Cai, Xianlong Hong. 1077-1080 [doi]
- Design and Synthesis of a Three Input Flagged Prefix AdderVibhuti B. Dave, Erdal Oruklu, Jafar Saniie. 1081-1084 [doi]
- Designing Efficient Online Testable Reversible Adders With New Reversible GateHimanshu Thapliyal, A. Prasad Vinod. 1085-1088 [doi]
- Design and Synthesis of a Carry-Free Signed-Digit Decimal AdderJohn Moskal, Erdal Oruklu, Jafar Saniie. 1089-1092 [doi]
- High Speed 1-bit Bypass Adder Design for Low Precision AdditionsJong Suk Lee, Dong Sam Ha. 1093-1096 [doi]
- A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication ProblemsOscar Gustafsson. 1097-1100 [doi]
- Implementation of a Labeling Algorithm based on Contour Tracing with Feature ExtractionHugo Hedberg, Fredrik Kristensen, Viktor Öwall. 1101-1104 [doi]
- Flexible and Cost Effective Transport Stream Processor for DTVChia-Liang Tsai, Shao-Yi Chien. 1105-1108 [doi]
- Efficient Color Space Conversion using Custom Instruction in a RISC ProcessorMuhammad Bilal, Shahid Masud. 1109-1112 [doi]
- A Power-Aware Reconfigurable Rendering Engine Design with 453MPixels/s, 16.4MTriangles/s PerformanceChih-Hao Chao, Yen-Lin Kuo, An-Yeu Wu, Weber Chien. 1113-1116 [doi]
- Flexible Low Power Probability Density Estimation Unit For Speech RecognitionUllas Pazhayaveetil, Dhruba Chandra, Paul Franzon. 1117-1120 [doi]
- Design of Mixed-Voltage Crystal Oscillator Circuit in Low-Voltage CMOS TechnologyMing-Dou Ker, Hung-Tai Liao. 1121-1124 [doi]
- Efficient Insertion of Crosstalk Shielding along On-Chip Interconnect TreesBoyan Semerdjiev, Dimitrios Velenis. 1125-1128 [doi]
- Area Efficient Bus Encoding Technique for Minimizing Simultaneous Switching Noise (SSN)Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas. 1129-1132 [doi]
- Applications of AOGL Model-Order Reduction Techniques in Interconnect AnalysisMing-Hong Lai, Chia-Chi Chu, Wu-Shiung Feng. 1133-1136 [doi]
- A 1.9mW Portable ADPLL-based Frequency Synthesizer for High Speed Clock GenerationMing-Hung Chang, Zong-Xi Yang, Wei Hwang. 1137-1140 [doi]
- Clock Gating and Negative Edge Triggering for Energy Recovery ClockVishwanadh Tirumalashetty, Hamid Mahmoodi. 1141-1144 [doi]
- Efficient Power Macromodeling Technique for IP-Based Digital SystemYaseer A. Durrani, Ana Abril, Teresa Riesgo. 1145-1148 [doi]
- A CMOS Low Power Fully Digital Adaptive Power Delivery System Based on Finite State Machine ControlYong-Bin Kim, Kyung Ki Kim, James T. Doyle. 1149-1152 [doi]
- Impact of strain on the design of low-power high-speed circuitsH. Ramakrishnan, K. Maharatna, S. Chattopadhyay, A. Yakovlev. 1153-1156 [doi]
- An Energy-Efficient Dual-Edge Triggered Level-Converting Flip-FlopLih-Yih Chiou, Shien-Chun Lou. 1157-1160 [doi]
- Optimal Body Biasing for Minimum Leakage Power in Standby ModeKyung Ki Kim, Yong-Bin Kim. 1161-1164 [doi]
- A Low Power 4-bit Interleaved Burst Sampling ADC for Sub-GHz Impulse UWB RadioXiaodong Zhang, Magdy Bayoumi. 1165-1168 [doi]
- A Low Energy FFT/IFFT Processor for Hearing AidsKwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang. 1169-1172 [doi]
- Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy EfficiencyBo Fu, Paul Ampadu. 1173-1176 [doi]
- High performance processor array for image processingPéter Földesy, Ákos Zarándy, Csaba Rekeczky, Tamás Roska. 1177-1180 [doi]
- The RunBot Architecture for Adaptive, Fast, Dynamic WalkingPoramate Manoonpong, Tao Geng, Bernd Porr, Florentin Wörgötter. 1181-1184 [doi]
- ISCAS Special Session Demo: Wireless Video Sensor for Ad-hoc NetworksYu M. Chi, Paul Carpenter, Kent Colling, Gert Cauwenberghs, Ralph Etienne-Cummings. 1185 [doi]
- Silicon Neurons that Inhibit to SynchronizeJohn V. Arthur, Kwabena Boahen. 1186 [doi]
- A Self-Contained Large-Scale FPAA Development PlatformChristopher M. Twigg, Paul E. Hasler, I. Faik Baskaya. 1187-1191 [doi]
- Using FPGA for visuo-motor control with a silicon retina and a humanoid robotAlejandro Linares-Barranco, Francisco Gomez-Rodriguez, Angel Jiménez-Fernandez, Tobi Delbrück, P. Lichtensteiner. 1192-1195 [doi]
- Wide dynamic range, high-speed machine vision with a 2×256 pixel temporal contrast vision sensorChristoph Posch, Michael Hofstatter, Martin Litzenberger, Daniel Matolin, N. Donath, P. Schon, H. Garn. 1196-1199 [doi]
- Battery powered high dynamic range vision systemPierre-François Ruedi, Eric Grenet, Felix Lustenberger. 1200 [doi]
- AER Auditory Filtering and CPG for Robot ControlFrancisco Gomez-Rodriguez, Alejandro Linares-Barranco, Lourdes Miro-Amarante, Shih-Chii Liu, André van Schaik, Ralph Etienne-Cummings, M. Anthony Lewis. 1201-1204 [doi]
- An Integrated Patch-Clamp Amplifier for High-Density Whole-Cell RecordingsPujitha Weerakoon, Kate Klemic, Fred J. Sigworth, Eugenio Culurciello. 1205-1208 [doi]
- A Universal Method for Hierarchical Object Recognition based on Low-Power Vision SensorsFelix Lustenberger, David Beyeler, Edo Franzi, Peter Seitz, Thierry Zamofing. 1209 [doi]
- Thresholded samplers for UWB impulse radarHakon A. Hjortland, Dag T. Wisland, Tor Sverre Lande, Claus Limbodal, Kjetil Meisal. 1210-1213 [doi]
- Data Matrix Code Recognition Using the Eye-RIS Vision SystemAmanda Jimenez-Marrufo, Ainhoa Mendizabal, Sergio Morillas-Castillo, Rafael Domínguez-Castro, Servando Espejo-Meana, Rafael Romay-Juarez, Ángel Rodríguez-Vázquez. 1214 [doi]
- An On-line, Multi-Parametric, Multi-Channel Physicochemical Monitoring Platform for Stem Cell Culture BioprocessingXicai Yue, Emmanuel M. Drakakis, Hua Ye, Mayasari Lim, A. Mantalaris, Nicki Panoskaltsis, Anna Radomska, Chris Toumazou, T. Cass. 1215-1218 [doi]
- A Micropower Cochlear Prosthesis System DemonstratorJulius Georgiou, Timothy G. Constandinou, Chris Toumazou. 1219 [doi]
- A Prototyping Co-design Platform with A Simplified Architecture for Video Codec ImplementationYifeng Qiu, Wael M. Badawy, Robert D. Turney. 1220-1224 [doi]
- Statistical Analysis of Mapping Technique for Timing Error Correction in Current-Steering DACsYongjian Tang, Hans Hegt, Arthur H. M. van Roermund, Konstantinos Doris, Joost Briaire. 1225-1228 [doi]
- A Continuous Time Analog-to-Digital Converter With 90µW and 1.8µV/LSB Based on Differential Ring Oscillator StructuresAndreas Tritschler. 1229-1232 [doi]
- Digital Background Calibration of Higher Order Nonlinearities in Pipelined ADCsAnand Meruva, Bahar Jalali Farahani. 1233-1236 [doi]
- Split-ADC Digital Background Correction of Open-Loop Residue Amplifier Nonlinearity Errors in a 14b Pipeline ADCJohn A. McNeill, Sanjeev Goluguri, Abhilash Nair. 1237-1240 [doi]
- A Gradient-Based Algorithm for Sampling Clock Skew Calibration of SHA-less Pipeline ADCsPingli Huang, Yun Chiu. 1241-1244 [doi]
- Device Mismatch: An Analog Design PerspectivePeter R. Kinget. 1245-1248 [doi]
- Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal CircuitsMichael Fulde, Doris Schmitt-Landsiedel, Gerhard Knoblinger. 1249-1252 [doi]
- Digital RF Processing Techniques for Device Mismatch Tolerant Transmitters in Nanometer-Scale CMOSKhurram Waheed, Robert B. Staszewski. 1253-1256 [doi]
- An Approach to Detect Negative Bias Temperature Instability (NBTI) in Ultra-Deep Submicron TechnologiesRonald Carlsten, Jeremy Ralston-Good, Douglas Goodman. 1257-1260 [doi]
- Threshold Voltage Variation Effects on Aging-Related Hard Failure RatesBrian Greskamp, Smruti R. Sarangi, Josep Torrellas. 1261-1264 [doi]
- Effect of Recompression on Attacking JPEG Steganographic Schemes An Experimental StudyYun Q. Shi, Chunhua Chen, Wen Chen, Maala P. Kaundinya. 1265-1268 [doi]
- Data Hiding For Binary Images Authentication By Considering A Larger NeighborhoodHuijuan Yang, Alex C. Kot. 1269-1272 [doi]
- Enhanced Image Trans-coding Using Reversible Data HidingRichard Y. M. Li, Oscar C. Au, Carman K. M. Yuk, Shu-Kei Yip, Tai-Wai Chan. 1273-1276 [doi]
- Cost Effective Color Filter Array Demosaicking with Chrominance Variance Weighted InterpolationTsung-Huang Chen, Shao-Yi Chien. 1277-1280 [doi]
- Color Demosaicking Using Direction Similarity in Color Difference SpacesCarman K. M. Yuk, Oscar C. Au, Richard Y. M. Li, Sui-Yuk Lam. 1281-1284 [doi]
- A Simple Neural Cross-Correlation EngineJonathan Tapson, Ralph Etienne-Cummings. 1285-1288 [doi]
- An Energy-Scalable Margin Propagation-Based Analog VLSI Support Vector MachinePaul Kucher, Shantanu Chakrabartty. 1289-1292 [doi]
- Neural Learning by Retractions on ManifoldsSimone Fiori. 1293-1296 [doi]
- A Scalable and Programmable Architecture for the Continuous Restricted Boltzmann Machine in VLSIC.-C. Lu, C. Y. Hong, H. Chen. 1297-1300 [doi]
- A Current-Mode Analog Circuit for Reinforcement Learning ProblemsTerrence S. T. Mak, K. P. Lam, H. S. Ng, G. Rachmuth, C.-S. Poon. 1301-1304 [doi]
- Reduced Complexity Space-Time-Frequency Model for Multi-Channel EEG and Its ApplicationsYodchanan Wongsawat, Soontorn Oraintara, K. R. Rao. 1305-1308 [doi]
- On the Time-frequency Analysis of Trunk Muscles During Sudden Release of LoadK. M. Tsui, Zhiguo Zhang, Shing-Chow Chan, Yong Hu, Keith D. K. Luk. 1309-1312 [doi]
- 3D Shape Acquisition System Dedicated to a Visual Intracortical StimulatorAlexandra Delia Doljanu, Mohamad Sawan. 1313-1316 [doi]
- d-infinite Criteria for MEG CharacterizationPaolo Arena, Maide Bucolo, Luigi Fortuna, Mattia Frasca, Manuela La Rosa, F. Sapuppo, Elena Umana, David Shannahoff-Khalsa. 1317-1320 [doi]
- Design and Implementation of a Low Complexity Near-lossless Image Compression Method for Wireless Endoscopy Capsule SystemXiaowen Li, Xiang Xie, Xinkai Chen, Guolin Li, Li Zhang, Zhihua Wang, Hong Chen. 1321-1324 [doi]
- Energy-Efficient Double-Binary Tail-Biting Turbo Decoder Based on Border Metric EncodingJi-Hoon Kim, In-Cheol Park. 1325-1328 [doi]
- On equalization of channels with ZP precodersP. P. Vaidyanathan. 1329-1332 [doi]
- An Adaptive Step-size Order Statistic Time Domain Equaliser for Discrete Multitone SystemsSuchada Sitjongsataporn, Peerapol Yuvapoositanon. 1333-1336 [doi]
- Training-Based Estimation of Correlated MIMO Fading Channels in the Presence of Colored InterferenceDimitrios Katselis, Eleftherios Kofidis, Sergios Theodoridis. 1337-1340 [doi]
- An Efficient Finite Precision Realization of the Adaptive Decision Feedback EqualizerRafiahamed Shaik, Mrityunjoy Chakraborty. 1341-1344 [doi]
- Tradeoffs in the Design of CMOS Receivers for Low Power Wireless Sensor NetworksJames Ayers, Kartikeya Mayaram, Terri S. Fiez. 1345-1348 [doi]
- A Batteryless Vibration-based Energy Harvesting System for Ultra Low Power Ubiquitous ApplicationsLu Chao, Chi-Ying Tsui, Wing-Hung Ki. 1349-1352 [doi]
- An Inductor-less Micro Solar Power Management System Design for Energy Harvesting ApplicationsHui Shao, Chi-Ying Tsui, Wing-Hung Ki. 1353-1356 [doi]
- Design and Implementation of Routing Scheme for Wireless Network-on-ChipYi Wang, Dan Zhao. 1357-1360 [doi]
- Data Throughput Optimization in the IEEE 802.15.4 Medical Sensor NetworksStig Stoa, Ilangko Balasingham, Tor A. Ramstad. 1361-1364 [doi]
- Efficient Data Transfer Techniques and VLSI architecture for DWT-Block Coder Integration of JPEG2000 EncoderAmit Kumar Gupta, Saeid Nooshabadi, David Taubman. 1365-1368 [doi]
- Hardware Architecture of a Parallel Pattern Matching EngineMeeta Yadav, Ashwini Venkatachaliah, Paul D. Franzon. 1369-1372 [doi]
- A Hardware Efficient Very Large Bit Word Binary to Double Base Number System Converter for Encryption ApplicationsRoberto Muscedere. 1373-1376 [doi]
- An Efficient Pipelined VLSI Architecture for Lifting-Based 2D-Discrete Wavelet TransformRahul Jain, Preeti Ranjan Panda. 1377-1380 [doi]
- An Improved Frame-Level Pipelined Architecture for High Resolution Video Motion EstimationWei-Feng He, Zhi-Gang Mao. 1381-1384 [doi]
- Variable Threshold Voltage Design Scheme for CMOS Tapered BuffersAhmed Shebaita, Yehea I. Ismail. 1385-1388 [doi]
- Charge Recycling MTCMOS for Low Energy Active/Sleep Mode TransitionsZhiyu Liu, Volkan Kursun. 1389-1392 [doi]
- Power Grid Analysis of Dynamic Power Cutoff TechnologyBaozhen Yu, Michael L. Bushnell. 1393-1396 [doi]
- Multi-Vth Level Conversion Circuits for Multi-VDD SystemsSherif A. Tawfik, Volkan Kursun. 1397-1400 [doi]
- A Novel Low Power Interface Circuit Design Technique for Multiple Voltage Islands SchemeSaihua Lin, Huazhong Yang, Rong Luo. 1401-1404 [doi]
- A Parallel Architecture for Hermitian Decoders: Satisfying Resource and Throughput ConstraintsRachit Agarwal, Emanuel M. Popovici, Brendan O Flynn, Michael E. O Sullivan. 1405-1408 [doi]
- Direct Root Computation Architecture for Algebraic Soft-Decision Decoding of Reed-Solomon CodesJun Ma, Alexander Vardy, Zhongfeng Wang, Qinqin Chen. 1409-1412 [doi]
- Low-complexity Interpolation Architecture for Soft-decision Reed-Solomon DecodingXinmiao Zhang, Jiangli Zhu. 1413-1416 [doi]
- FFT Processor for OFDM Channel EstimationSimon Haene, Andreas Burg, Peter Luethi, Norbert Felber, Wolfgang Fichtner. 1417-1420 [doi]
- VLSI Implementation of a High-Speed Iterative Sorted MMSE QR DecompositionPeter Luethi, Andreas Burg, Simon Haene, David Perels, Norbert Felber, Wolfgang Fichtner. 1421-1424 [doi]
- Algorithmic ADC Offset Compensation by Non-White Data ChoppingStefano Vitali, Giampaolo Cimatti, Riccardo Rovatti, Gianluca Setti. 1425-1428 [doi]
- Stability Analysis of RED Gateway with Multiple TCP Reno ConnectionsXi Chen, Siu Chung Wong, Chi K. Michael Tse, Ljiljana Trajkovic. 1429-1432 [doi]
- Noncoherent Correlation-Based Communication Systems Choosing Different Chaotic MapsShintaro Arai, Yoshifumi Nishio. 1433-1436 [doi]
- Second-level NIST Randomness Tests for Improving Test ReliabilityFabio Pareschi, Riccardo Rovatti, Gianluca Setti. 1437-1440 [doi]
- Joint Design of a DS-UWB Modulator and Chaos-Based Spreading Sequences for Sensor NetworksLuca Antonio De Michele, Giampaolo Cimatti, Riccardo Rovatti, Gianluca Setti. 1441-1444 [doi]
- CMOS Integrated LC RF Bandpass Filter with Transformer-Coupled Q-Enhancement and Optimized LinearityWesley A. Gee, Phillip E. Allen. 1445-1448 [doi]
- Techniques for Dual-Band LNA Design using Cascode Switching and Inductor Magnetic CouplingMiguel A. Martins, Jorge R. Fernandes, Manuel M. Silva. 1449-1452 [doi]
- A New CMOS 3.1-11.7 GHz Low Power LNA for Ultra-Wideband Wireless ApplicationsMd. Mahbub Reja, C. Sellathamby, Igor M. Filanovsky. 1453-1456 [doi]
- A CMOS Variable Gain Front-end for a WCDMA ReceiverShaikh K. Alam, Joanne DeGroat. 1457-1460 [doi]
- Experimental Evaluation of Phase-Noise and Quadrature Error in a CMOS 2.4 GHz Relaxation OscillatorLuís Bica Oliveira, Jorge R. Fernandes, Manuel M. Silva, Igor M. Filanovsky, Chris J. M. Verhoeven. 1461-1464 [doi]
- Parallel current-steering D/A Converters for Flexibility and SmartnessGeorgi I. Radulov, Patrick J. Quinn, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund. 1465-1468 [doi]
- A 12-bit Current-Steering DAC with Calibration by Combination SelectionKati Virtanen, Janne Maunu, Jonne Poikonen, Ari Paasio. 1469-1472 [doi]
- Power/Area Trade-Offs in Low-Power/Low-Area Unary-R-2R CMOS Digital-to-Analog ConvertersBabak Nejati, Larry Larson. 1473-1476 [doi]
- A Digital Calibration Technique for the Correction of Glitches in High-Speed DAC sB. Catteau, Pieter Rombouts, Ludo Weyten. 1477-1480 [doi]
- An 8-bit 300MS/s Switched-Current Pipeline ADC in 0.18µm CMOSBehnam Sedighi, Mehrdad Sharif Bakhtiar. 1481-1484 [doi]
- Multi-level Order Reduction with Nonlinear Port ConstraintsMin Ma, Roni Khazaka. 1485-1488 [doi]
- Application of Relaxation-Based Technique to ADI-FDTD Method and Its EstimationYuya Nakazono, Hideki Asai. 1489-1492 [doi]
- Analysis for Signal and Power Integrity Using the Multilayered Finite Difference MethodEge Engin, Krishna Bharath, Madhavan Swaminathan. 1493-1496 [doi]
- Macromodeling for Nonlinear Distributed Interconnect NetworksTaha Amiralli, Anestis Dounavis. 1497-1500 [doi]
- Low-Order Rational Approximation of Interconnects Using Neural-Network Based Pole-Clustering TechniquesWendemagegnehu T. Beyene. 1501-1504 [doi]
- An Efficient Joint Source-Channel Coding for Wavelet Based Scalable VideoNaeem Ramzan, Shuai Wan, Ebroul Izquierdo. 1505-1508 [doi]
- Error-Resilience Transcoding of H.264/AVC Compressed VideosWen-Nung Lie, Han-Ching Yeh, Zhi-Wei Gao, Ping-Chang Jui. 1509-1512 [doi]
- UEP for Progressive Image Transmission with GA-based OptimizationLei Yao, Lei Cao. 1513-1516 [doi]
- Iterative Joint Source-Channel Decoding of H.264 Compressed VideoDavid Levine, William E. Lynch, Tho Le-Ngoc. 1517-1520 [doi]
- XML-driven Exploitation of Combined Scalability in Scalable H.264/AVC BitstreamsDavy De Schrijver, Wesley De Neve, Koen De Wolf, Peter Lambert, Davy Van Deursen, Rik Van de Walle. 1521-1524 [doi]
- Configuring of Spiking Central Pattern Generator Networks for Bipedal Walking Using Genetic AlgorthmsAlexander Russell, Garrick Orchard, Ralph Etienne-Cummings. 1525-1528 [doi]
- Spike-Based Feature Extraction for Noise Robust Speech Recognition Using Phase Synchrony CodingIsmail Uysal, Harsha Sathyendra, John G. Harris. 1529-1532 [doi]
- Self-Organizing Map Considering False Neighboring NeuronHaruna Matsushita, Yoshifumi Nishio. 1533-1536 [doi]
- LVDS Serial AER Link performanceLourdes Miro-Amarante, Angel Jiménez-Fernandez, Alejandro Linares-Barranco, Francisco Gomez-Rodriguez, R. Paz, Gabriel Jiménez, Antón Civit, Rafael Serrano-Gotarredona. 1537-1540 [doi]
- Synchronization and Bifurcations in Networks of Coupled Hindmarsh-Rose NeuronsPaolo Checco, Mario Biey, Marco Righero, Ljupco Kocarev. 1541-1544 [doi]
- Electromagnetic Compatibility Modeling in Low-Noise Medical Sensor InterfacesOlivier Valorge, Benoit Gosselin, Louis-Francois Tanguay, Mohamad Sawan. 1545-1548 [doi]
- Impact of Control Signal Non-Idealties on Two-Phase Charge PumpsAndrea Fantini, Alessandro Cabrini, Guido Torelli. 1549-1552 [doi]
- Issues in the Design and Simulation of a MEMS VCO based Phase-Locked LoopManeesha Yellepeddi, Kartikeya Mayaram. 1553-1556 [doi]
- Above Threshold pFET InjectionModeling intended for ProgrammingFloating-Gate SystemsPaul E. Hasler, Arindam Basu, Sctt Kozil. 1557-1560 [doi]
- A Physical Interpretation of the Distance Term in Pelgrom s Mismatch Model results in very Efficient CADBernabé Linares-Barranco, Teresa Serrano-Gotarredona. 1561-1564 [doi]
- An Energy-efficient Reconfigurable Viterbi Decoder on a Programmable MultiprocessorGuichang Zhong, Alan N. Willson Jr.. 1565-1568 [doi]
- A Memory-Based Hardware Accelerator for Real-Time MPEG-4 Audio Coding and ReverberationGuo-An Jian, Chih-Da Chien, Jiun-In Guo. 1569-1572 [doi]
- Address Code Optimization Exploiting Code Scheduling in DSP ApplicationsZhenmin Li, Taewhan Kim. 1573-1576 [doi]
- A Precompensation Algorithm for PWM-Based Digital Audio Amplifiers for Portable ApplicationsXiaoxiang Gong, John G. Harris. 1577-1580 [doi]
- Denoising for Generalized Sidelobe CancellerChun-Yat Ma, Tai-Chiu Hsung, Daniel Pak-Kong Lun, K. C. Ho, H. K. Kwan. 1581-1584 [doi]
- Design and Implementation of a Low-power Baseband-system for RFID TagAdam S. W. Man, Edward S. Zhang, H. T. Chan, Vincent K. N. Lau, C. Y. Tsui, Howard C. Luong. 1585-1588 [doi]
- Enabling Pervasive Sensing with RFID: An Ultra Low-Power Digital Core for UHF TranspondersAndrea Ricci, Ilaria De Munari. 1589-1592 [doi]
- A Novel Passive Tag with Asymmetric Wireless Link for RFID and WSN ApplicationsMajid Baghaei Nejad, Zhuo Zou, Hannu Tenhunen, Li-Rong Zheng. 1593-1596 [doi]
- Object Tracking Based on RFID Coverage Visual Compensation in Wireless Sensor NetworkJinseok Lee, Kyoung-Su Park, Sangjin Hong, We-Duke Cho. 1597-1600 [doi]
- Low-Complexity Encryption Using Redundant Bits and Adaptive Frequency Rates in RFIDMeng-Lin Hsia, Oscal T.-C. Chen. 1601-1604 [doi]
- An Efficient Pipelined Architecture for H.264/AVC Intra Frame ProcessingGenhua Jin, Jin-Su Jung, Hyuk-Jae Lee. 1605-1608 [doi]
- Architecture and VLSI Implementation of a programmable HD Real-Time Motion EstimatorK. Gaedke, M. Borsum, M. Georgi, A. Kluger, J.-P. Le Glanic, P. Bernard. 1609-1612 [doi]
- A High-Performance 2-D Inverse Transform Architecture for the H.264/AVC DecoderWoong Hwangbo, Jaemoon Kim, Chong-Min Kyung. 1613-1616 [doi]
- MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTVArnaldo Azevedo, Bruno Zatt, Luciano Volcan Agostini, Sergio Bampi. 1617-1620 [doi]
- A New Frame Recompression Algorithm Integrated with H.264 Video CompressionYongje Lee, Chae-Eun Rhee, Hyuk-Jae Lee. 1621-1624 [doi]
- A Low Power Domino with Differential-Controlled-KeeperPeiyi Zhao, Jason McNeely, Magdy A. Bayoumi, Golconda Pradeep Kumar, Weidong Kuang. 1625-1628 [doi]
- Towards Automated Power Gating of Registers using CoDeLNainesh Agarwal, Nikitas J. Dimopoulos. 1629-1632 [doi]
- Self-Supplied Integrable Active High-Efficiency AC-DC Converter for Piezoelectric Energy Scavenging SystemsEnrico Dallago, Daniele Miatton, Giuseppe Venchi, Giovanni Frattini, Giulio Ricotti. 1633-1636 [doi]
- Low Power On-Chip Current Monitoring Medium-Grained Adaptive Voltage ControlWei-Chih Hsieh, Wei Hwang. 1637-1640 [doi]
- A New Statistical Approach for Glitch Estimation in Combinational CircuitsAhmed Sayed, Hussain Al-Asaad. 1641-1644 [doi]
- Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless StandardKiran K. Gunnam, Gwan Choi, Weihuang Wang, Mark B. Yeary. 1645-1648 [doi]
- A High Throughput H-QC LDPC DecoderYi-Hsing Chien, Mong-Kai Ku. 1649-1652 [doi]
- FPGA Implementation of LDPC Decoders Based on Joint Row-column Decoding AlgorithmZhiyong He, Sébastien Roy, Paul Fortier. 1653-1656 [doi]
- Towards a GBit/s Programmable Decoder for LDPC Convolutional CodesEmil Matús, Marcos B. S. Tavares, Marcel Bimberg, Gerhard Fettweis. 1657-1660 [doi]
- Design and Realization of Analog Phi-Function for LDPC DecoderAbu Baker, Soumik Ghosh, Ashok Kumar, Magdy A. Bayoumi, Rafic A. Ayoubi. 1661-1664 [doi]
- Classes of stochastically switched (blinking) systemsMartin Hasler, Igor Belykh, Vladimir N. Belykh. 1665-1668 [doi]
- Synchronization in Complex Hybrid NetworksPaolo Checco, Mario Biey, Ljupco Kocarev. 1669-1672 [doi]
- Dynamics of a Logarithmic Transimpedance AmplifierArindam Basu, Kofi M. Odame, Paul E. Hasler. 1673-1676 [doi]
- Equivalence of two discretization schemes in a simple sliding mode control systemZbigniew Galias, Xinghuo Yu. 1677-1680 [doi]
- Convergence Analysis of the Unscented Kalman Filter for Filtering Noisy Chaotic SignalsJiuchao Feng, Hongjuan Fan, Chi K. Michael Tse. 1681-1684 [doi]
- A Design of DC Offset Canceller using Parallel CompensationSeung-Min Oh, Kyoung-Seok Park, Hyun-Hwan Yoo, Yoo-Sam Na, Taek-Soo Kim. 1685-1688 [doi]
- A Second Order Delta-Sigma Frequency Discriminator with Fractional-N Divider and Multi-Bit QuantizerJian-Hong Fang, Norman M. Filiol, Tom A. D. Riley, Miles A. Copeland. 1689-1692 [doi]
- A Power Optimized Base-Band Circuitry for the Low-IF ReceiversRamin Zanbaghi, Seyed Mojtaba Atarodi, Armin Tajalli. 1693-1696 [doi]
- A 90nm Quadrature Generator with Frequency Extension up to 4GHzBob Stengel, Said Rami. 1697-1700 [doi]
- A New Quadrature LC-OscillatorMalihe Zarre Dooghabadi, Sasan Naseh. 1701-1704 [doi]
- Bandwidth Mismatch Correction for a Two-Channel Time-Interleaved A/D ConverterPatrick Satarzadeh, Bernard C. Levy, Paul J. Hurst. 1705-1708 [doi]
- A 10-bit 500-MS/s 124-mW Subranging Folding ADC in 0.13 µm CMOSCheng Chen, Jiren Yuan. 1709-1712 [doi]
- A 12-bit Ratio-Independent Algorithmic ADC for a Capacitive Sensor InterfaceJere A. M. Jarvinen, Mikko Saukoski, Kari Halonen. 1713-1716 [doi]
- An 11 Bit Sub-Ranging SAR ADC with Input Signal Range of Twice Supply VoltageDevrim Yilmaz Aksin, Mohammad A. Al-Shyoukh, Franco Maloberti. 1717-1720 [doi]
- A High-Speed High-Resolution Low-Distortion CMOS Bootstrapped SwitchLei Wang, Junyan Ren, Wenjing Yin, Tingqian Chen, Jun Xu. 1721-1724 [doi]
- Satellite Navigation: New Signals, New ChallengesAndrew G. Dempster. 1725-1728 [doi]
- Analysis and Compensation of RF Impairments for Next Generation Multimode GNSS ReceiversEdiz Çetin, Izzet Kale, Richard C. S. Morling. 1729-1732 [doi]
- Efficient Software Defined Radio Implementations of GNSS ReceiversGianmarco Girau, Andrea Tomatis, Fabio Dovis, Paolo Mulassano. 1733-1736 [doi]
- Galileo L1 Civil Receiver Tracking Loops ArchitectureOlivier Julien, Gérard Lachapelle, M. Elizabeth Cannon. 1737-1741 [doi]
- Design of an Assisted GPS Receiver and its Performance AnalysisDeok Won Lim, Sang-Jeong Lee, Deuk Jae Cho. 1742-1745 [doi]
- Rate Control for Spatial/CGS Scalable Extension of H.264/AVCY. Liu, Y. C. Soh, Z. G. Li. 1746-1750 [doi]
- Multi-Stage MCTF Coding Efficiency Analysis with Directed-Tree ModelFengling Li, Nam Ling, Stephen A. Chiappari. 1751-1754 [doi]
- 3D Object-based Scalable Wavelet Video Coding with Boundary Effect SuppressionYu Liu, Feng Wu, King Ngi Ngan. 1755-1758 [doi]
- Balanced Inter-Layer Prediction for Combined Coarse Granular Scalability and Spatial ScalabilityWei Yao, Zhengguo Li, Susanto Rahardja. 1759-1762 [doi]
- Macroblock-Based Adaptive In-Scale Prediction for Scalable Video CodingRuiqin Xiong, Jizheng Xu, Feng Wu, Shipeng Li. 1763-1766 [doi]
- A Study of Delay-Dependent Stabilization for Discrete-Time Systems with Time DelaysShaosheng Zhou, Wei Xing Zheng. 1767-1770 [doi]
- Noise-robust automatic speech recognition using a discriminative echo state networkMark D. Skowronski, John G. Harris. 1771-1774 [doi]
- Multi-Channel Coherent Detection for Delay-Insensitive Model-Free Adaptive ControlDimitrios N. Loizos, Paul-Peter Sotiriadis, Gert Cauwenberghs. 1775-1778 [doi]
- Generalizations of Oja s Learning Rule to Non-Symmetric MatricesMohammed A. Hasan. 1779-1782 [doi]
- Effective Search with Hopping Chaos for Hopfield Neural Networks Solving QAPYoshifumi Tada, Yoko Uwate, Yoshifumi Nishio. 1783-1786 [doi]
- A Structured ASIC Design Approach Using Pass Transistor LogicKanupriya Gulati, Nikhil Jayakumar, Sunil P. Khatri. 1787-1790 [doi]
- Architecture Level Power-Performance Tradeoffs for Pipelined DesignsHaider Ali, Bashir M. Al-Hashimi. 1791-1794 [doi]
- A Fast Register Relocation Method for Circuit Size Reduction in Generalized-Synchronous FrameworkYukihide Kohira, Atsushi Takahashi. 1795-1798 [doi]
- Asynchronous Staggered Set/Reset Techniques for Low-Noise ApplicationsRenato Rimolo-Donadio, Antonio J. Acosta, Wolfgang H. Krautschneider. 1799-1802 [doi]
- Ensemble Dependent Matrix Methodology for Probabilistic-Based Fault-tolerant Nanoscale Circuit DesignHuifei Rao, Jie Chen, Changhong Yu, Woon Tiong Ang, I-Chyn Wey, An-Yeu Wu, Hong Zhao. 1803-1806 [doi]
- DPA Using Phase-Based Waveform Matching against Random-Delay CountermeasureSei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh. 1807-1810 [doi]
- An Accurate Algorithm for Fast Frequency WarpingSalvatore Caporale, Luca De Marchi, Nicolo Speciale. 1811-1814 [doi]
- Minimum Variance Spectral Estimation-Based Time Frequency Analysis for Nonstationary Time-SeriesS. C. Chan, Z. G. Zhang, K. M. Tsui. 1815-1818 [doi]
- Improved SVD-Based Technique for Enhancing the Time-Frequency Representation of SignalsHamid Hassanpour. 1819-1822 [doi]
- HRTF Interpolation Through Direct Angular ParameterizationFabio P. Freeland, Luiz W. P. Biscainho, Paulo S. R. Diniz. 1823-1826 [doi]
- New Architectures for Low-Cost Public Key Cryptography on RFID TagsMáire McLoone, Matthew J. B. Robshaw. 1827-1830 [doi]
- Public-Key Cryptography on the Top of a NeedleLejla Batina, Nele Mentens, Kazuo Sakiyama, Bart Preneel, Ingrid Verbauwhede. 1831-1834 [doi]
- ECC Processor with Low Die Size for RFID ApplicationsFranz Fürbass, Johannes Wolkerstorfer. 1835-1838 [doi]
- Strong Crypto for RFID Tags - A Comparison of Low-Power Hardware ImplementationsMartin Feldhofer, Johannes Wolkerstorfer. 1839-1842 [doi]
- New Light-Weight Crypto Algorithms for RFIDAxel Poschmann, Gregor Leander, Kai Schramm, Christof Paar. 1843-1846 [doi]
- SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery MultiplierAtsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh. 1847-1850 [doi]
- A New Compact Architecture for AES with Optimized ShiftRows OperationHua Li, Jianzhou Li. 1851-1854 [doi]
- Efficient Highly-Parallel Decoder Architecture for Quasi-Cyclic Low-Density Parity-Check CodesDaesun Oh, Keshab K. Parhi. 1855-1858 [doi]
- A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh. 1859-1862 [doi]
- High-Speed Parallel Hardware Architecture for Galois Counter ModeAkashi Satoh. 1863-1866 [doi]
- Fundamental Bounds on Power Reduction during Data-Retention in Standby SRAMAnimesh Kumar, Huifang Qin, Prakash Ishwar, Jan M. Rabaey, Kannan Ramchandran. 1867-1870 [doi]
- Breaking the Power-Delay Tradeoff: Design of Low-Power High-Speed MOS Current-Mode Logic Circuits Operating with Reduced Supply VoltageStéphane Badel, Yusuf Leblebici. 1871-1874 [doi]
- Integrated Heterogenous Modelling for Power Estimation of Single Processor based Reconfigurable SoC PlatformPrakash Srinivasan, Ali Ahmadinia, Ahmet T. Erdogan, Tughrul Arslan. 1875-1878 [doi]
- Critical Charge Characterization for Soft Error Rate Modeling in 90nm SRAMRiaz Naseer, Younes Boulghassoul, Jeff Draper, Sandeepan DasGupta, Art Witulski. 1879-1882 [doi]
- Battery-Aware Variable Voltage Scheduling on Real-Time Multiprocessor PlatformsYufeng Xie, Leibo Liu, Rui Dai, Shaojun Wei. 1883-1886 [doi]
- A Microwave OTA Using a Feedforward-Regulated Cascode TopologyYou Zheng, Carlos E. Saavedra. 1887-1890 [doi]
- GVD and PMD Compensation Using a Linear Adjustable Filter Prototype in a 40 Gb/s OSSB SystemMiguel Ângelo M. Madureira, Daniel Fonseca, Adolfo V. T. Cartaxo, Paulo M. P. Monteiro, Rui L. Aguiar. 1891-1894 [doi]
- A 4.1 GHz Dual Modulus Prescaler Using the E-TSPC Technique and Double Data Throughput StructuresFernando P. H. de Miranda, João Navarro Jr., Wilhelmus A. M. Van Noije. 1895-1898 [doi]
- On the Persistency of Excitation for Blind Channel Estimation in Cyclic Prefix SystemsBorching Su, P. P. Vaidyanathan. 1899-1902 [doi]
- Implementation of a Low-Complexity Frame-Start Detection Algorithm for MIMO SystemsDavid Perels, Christoph Studer, Wolfgang Fichtner. 1903-1906 [doi]
- Low Voltage CMOS Current and Voltage References without ResistorsChristian Falconi, Arnaldo D Amico, Giuseppe Scotti, Alessandro Trifiletti. 1907-1910 [doi]
- A 4-Bits Trimmed CMOS Bandgap Reference with an Improved Matching Modeling DesignJuan Pablo Martinez Brito, Sergio Bampi, Hamilton Klimach. 1911-1914 [doi]
- A Capacitor-Free CMOS Low-Dropout RegulatorMikko Loikkanen, Juha Kostamovaara. 1915-1918 [doi]
- A gm-C Ramp Generator for Voltage Feedforward Control of DC-DC Switching RegulatorsJader A. De Lima, Wallace A. Pimenta. 1919-1922 [doi]
- An Improved Temperature Compensation Technique for Current BiasingAnna Arbat, Ángel Dieguez, Josep Samitier. 1923-1926 [doi]
- A numerical design approach for single amplifier, Active-RC Butterworth filter of order 5H. Gaunholt. 1927-1930 [doi]
- Volterra Analysis Using Chebyshev SeriesIoannis Sarkas, Dimitrios Mavridis, Michail Papamichail, George D. Papadopoulos. 1931-1934 [doi]
- Digital Block Modeling and Substrate Noise Aware Floorplanning for Mixed Signal SOCsWilliam H. Kao, Xiaopeng Dong. 1935-1938 [doi]
- Design Centering High Frequency Integrated Continuous-Time FiltersTonse Laxminidhi, Shanthi Pavan. 1939-1942 [doi]
- On the Linearization of MOSFET CapacitorsMohammad Danaie, Hamed Aminzadeh, Sasan Naseh. 1943-1946 [doi]
- A Highly-Linear Successive-Approximation Front-End Digitizer with Built-in Sample-and-Hold Function for Pipeline/Two-Step ADCWeng-leng Mok, Pui-In Mak, Seng-Pan U., Rui Paulo Martins. 1947-1950 [doi]
- Analog Calibration of Mismatches in an Open-Loop Track-and-Hold Circuit for Time-Interleaved ADCsPieter Harpe, Athon Zanikopoulos, Hans Hegt, Arthur H. M. van Roermund. 1951-1954 [doi]
- A 1.5V 10-b 30-MS/s CMOS Pipelined Analog-to-Digital ConverterChi-Chang Lu, Jyun-Yi Wu, Tsung-Sum Lee. 1955-1958 [doi]
- Theory and Implementation of an Analog-to-Information Converter using Random DemodulationJason N. Laska, Sami Kirolos, Marco F. Duarte, Tamer Ragheb, Richard G. Baraniuk, Yehia Massoud. 1959-1962 [doi]
- An 8-bit Switched-Resistor Pipeline ADCBehnam Sedighi, Mehrdad Sharif Bakhtiar. 1963-1966 [doi]
- SiGe 77GHz Automotive Radar TechnologyW. M. Huang, J. P. John, S. Braithwaite, J. Kirchgessner, I. S. Lim, D. Morgan, Y. B. Park, S. Shams, I. To, P. Welch, R. Reuter, H. Li, A. Ghazinour, Peter Wennekers, Yi Yin. 1967-1970 [doi]
- CMOS SOCs at 100 GHz: System Architectures, Device Characterization, and IC Design ExamplesS. P. Voinigescu, S. T. Nicolson, M. Khanpour, K. K. W. Tang, K. H. K. Yau, N. Seyedfathi, A. Timonov, A. Nachman, G. Eleftheriades, P. Schvan, M. T. Yang. 1971-1974 [doi]
- SiGe IC- based mm-wave imagerHelen Kim, Sean Duffy, Jeff Herd, Charles Sodini. 1975-1978 [doi]
- 60 GHz SiGe-BiCMOS Radio for OFDM TransmissionEckhard Grass, Frank Herzel, Maxim Piz, Klaus Schmalz, Yaoming Sun, Srdjan Glisic, Milos Krstic, Klaus Tittelbach-Helmrich, Marcus Ehrig, Wolfgang Winkler, Christoph Scheytt, Rolf Kraemer. 1979-1982 [doi]
- CMOS Transceivers at 60 GHz and Beyond1Behzad Razavi. 1983-1986 [doi]
- An Irregular Search Window Reuse Scheme for Motion Estimation in MPEG-2 to H.264 TranscodingXianghui Wei, Shen Li, Yang Song, Satoshi Goto. 1987-1990 [doi]
- Motion Mapping for MPEG-2 to H.264/AVC TranscodingJun Xin, Jianjun Li, Anthony Vetro, Huifang Sun, Shun-ichi Sekiguchi. 1991-1994 [doi]
- Coding Mode Analysis of MPEG-2 to H.264/AVC Transcoding for Digital TV ApplicationsYi-Nung Liu, Chi-Sun Tang, Shao-Yi Chien. 1995-1998 [doi]
- Complexity Reduction of H.263 to H.264 Transcoder with Fast Mode DecisionTsung-Han Tsai, Hsueh-Yi Lin, Yu-Xuan Lee, Pin-Hua Chen. 1999-2002 [doi]
- Quality Enhancement in H.264 Transform Domain DownsizingHaiyan Shu, King Ngi Ngan. 2003-2006 [doi]
- Low-noise CMOS Fluorescence SensorDavid Sander, Marc Dandin, Honghao Ji, Nicole M. Nelson, Pamela Abshire. 2007-2010 [doi]
- Design, Analysis and Implementation of Integrated Micro-Thermal Control SystemsJennifer Blain Christen, Andreas G. Andreou. 2011-2014 [doi]
- Biosensor Integrated with Transducer to Detect the GlucoseJian-Yun Lai, Yan-Ting Chen, Te-Heng Wang, Hong-Si Chang, Jui-Lin Lai. 2015-2018 [doi]
- Classification of Driver s Cognitive Responses Using Nonparametric Single-trial EEG AnalysisChin-Teng Lin, Li-Wei Ko, Ken-Li Lin, Sheng-Fu Liang, Bor-Chen Kuo, I-Fang Chung, Lan-Da Van. 2019-2023 [doi]
- A multi-microchip retinal stimulator for in vitro / in vivo experimentsJun Ohta, Takahashi Tokuda, Keiichiro Kagawa, Akihiro Uehara, Yasuo Terasawa, Kazuaki Nakauchi, Takashi Fujikado, Yasuo Tano. 2024-2027 [doi]
- Noise-Aware Floorplanning for Fast Power Supply Network DesignChang-Tzu Lin, Tai-Wei Kung, De-Sheng Chen, Yi-Wen Wang, Ching-Hwa Cheng. 2028-2031 [doi]
- Topological Placement with Multiple Symmetry Groups of Devices for Analog Layout DesignKarthik Krishnamoorthy, Sarat C. Maruvada, Florin Balasa. 2032-2035 [doi]
- A 3D-Via Legalization Algorithm for 3D VLSI Circuits and its Impact on Wire LengthRenato Fernandes Hentschke, Ricardo Reis. 2036-2039 [doi]
- Clock-Tree Aware Placement Based on Dynamic Clock-Tree BuildingYanfeng Wang, Qiang Zhou, Xianlong Hong, Yici Cai. 2040-2043 [doi]
- A Fast 3D-BSG Algorithm for 3D Packing ProblemLingyi Zhang, Sheqin Dong, Xianlong Hong, Yuchun Ma. 2044-2047 [doi]
- Design of FIR Filters with Discrete Coefficients via Polynomial Programming: Towards the Global SolutionWu-Sheng Lu, Takao Hinamoto. 2048-2051 [doi]
- Synthesis of Wideband Linear-Phase FIR Filters with a Piecewise-Polynomial-Sinusoidal Impulse ResponseRaija Lehto, Tapio Saramäki, Olli Vainio. 2052-2055 [doi]
- The Design of Symmetric Square-Root Pulse-Shaping Filters for Transmitters and ReceiversChia-Yu Yao, Alan N. Willson Jr.. 2056-2059 [doi]
- Analytical Design of an Equiripple DC-Notch FIR FilterPavel Zahradnik, Miroslav Vlcek, Boris Simák. 2060-2063 [doi]
- A Sequential Constrained Least-Square Method for Minimax Design of Linear-phase FIR filters with Time-domain ConstraintsXiaoping Lai. 2064-2067 [doi]
- Low-Power Circuits for Brain-Machine InterfacesRahul Sarpeshkar, Woradorn Wattanapanitch, Benjamin I. Rapoport, Scott K. Arfin, Michael W. Baker, Soumyajit Mandal, Michale S. Fee, Sam Musallam, Richard A. Andersen. 2068-2071 [doi]
- Miniature Implantable System Dedicated to Bi-Channel Selective NeurostimulationF. Mounaim, Mohamad Sawan. 2072-2075 [doi]
- A Fully Integrated Fail-safe Stimulator Output Stage Dedicated to FES StimulationXiao Liu, Andreas Demosthenous, Nick Donaldson. 2076-2079 [doi]
- Designing Efficient Inductive Power Links for Implantable DevicesReid R. Harrison. 2080-2083 [doi]
- Florida Wireless Implantable Recording Electrodes (FWIRE) for Brain Machine InterfacesRizwan Bashirullah, John G. Harris, Justin C. Sanchez, Toshikazu Nishida, José Carlos Príncipe. 2084-2087 [doi]
- CSI-aided Demapping of Dual-Carrier Modulation for Multiband-OFDMSungchung Park, Yun-Young Kim, Jae-Ho Noh, Jun Jin Kong. 2088-2091 [doi]
- Blind Mode/GI Detection and Coarse Symbol Synchronization for DVB-T/HWei-Chang Liu, Ting-Chen Wei, Shyh-Jye Jou. 2092-2095 [doi]
- Parallel Architecture of List Sphere DecodersYuping Zhang, Keshab K. Parhi. 2096-2099 [doi]
- FPGA Implementation of an Interpolation Processor for Soft-Decision Decoding of Reed-Solomon CodesQinqin Chen, Zhongfeng Wang, Jun Ma. 2100-2103 [doi]
- VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC CodesYang Sun, Marjan Karkooti, Joseph R. Cavallaro. 2104-2107 [doi]
- Reducing Energy of DRAM/Flash Memory System by OS-controlled Data RefreshVasily G. Moshnyaga, Hua Vo, Glenn Reinman, Miodrag Potkonjak. 2108-2111 [doi]
- A Power Management Unit with Continuous Co-Locking of Clock Frequency and Supply Voltage for Dynamic Voltage and Frequency ScalingJeabin Lee, Byeong-Gyu Nam, Seong-Jun Song, Namjun Cho, Hoi-Jun Yoo. 2112-2115 [doi]
- Profile-Based Low Power Scheduling for Conditional Task Graph: A Communication Aware ApproachParth Malani, Prakash Mukre, Qinru Qiu. 2116-2119 [doi]
- Adaptive Clock Gating Technique for Low Power IP Core in SoC DesignXiaotao Chang, Mingming Zhang, Ge Zhang, Zhimin Zhang, Jun Wang. 2120-2123 [doi]
- Quasi-Static Energy Recovery Logic with Single Power-Clock SupplyShun Li, Feng Zhou, Chunhong Chen, Hua Chen, Yipin Wu. 2124-2127 [doi]
- A Two-port GFSK Direct Modulator for Wideband Applications at 5.8 GHzShayan Farahvash, Chee Quek, William Roberts, David Walker, Mohamed Mostafa, Hauw Liem, Robert Koupal. 2128-2131 [doi]
- Integrated Linear AC-coupling Circuit for DC-Balanced and Non-Balanced TrafficsYikui Dong, Cathy Liu, Freeman Zhong. 2132-2135 [doi]
- A 3.7mW, 1.6V CMOS Analog Adaptive Equalizer for a 125Mbps Wire-Line TransceiverAyman A. Fayed, Mohammed Ismail. 2136-2139 [doi]
- Quadrature VCOs Based on Coupled PLLsAndrea Bevilacqua, Christoph Sandner, Andrea Gerosa, Andrea Neviani. 2140-2143 [doi]
- Modified Reduced Constellation PLL for Higher Order QAMChanwoo Park, Jinbeom Lee, Younglok Kim. 2144-2147 [doi]
- 86 dB DR Cross-Coupled Time-Interleaved xx ADC for Audio Signal Band with 322 µA Current ConsumptionFranco Maloberti, Yonyoung Choi. 2148-2151 [doi]
- Low-Voltage Low-Power CMOS Oscillator with Low Temperature and Process SensitivityGiuseppe de Vita, Francesco Marraccini, Giuseppe Iannaccone. 2152-2155 [doi]
- A Fully Integrated Spread Spectrum Clock Generator Using Two-Point Delta-Sigma ModulationYi-Bin Hsieh, Yao-Huang Kao. 2156-2159 [doi]
- A New Cycle-Time-to-Digital Converter With Two Level Conversion SchemeHong-Yi Huang, Sheng-Da Wu, Yi-Jui Tsai. 2160-2163 [doi]
- A Sub-1V Low Power Temperature Compensated Current ReferenceAlfredo Olmos, Andre Vilas Boas, Jefferson Soldera. 2164-2167 [doi]
- VLSI Implementation of a Reconfigurable Mixed-Signal Finite Impulse Response FilterErhan Ozalevli, Walter Huang, Paul E. Hasler, David V. Anderson. 2168-2171 [doi]
- Current-Mode Phase-Locked Loops with Low Supply Voltage SensitivityD. DiClemente, F. Yuan. 2172-2175 [doi]
- On-Chip Substrate Noise Suppression Using Clock Randomization MethodologyYuxin Wang, Zeljko Ignjatovic. 2176-2179 [doi]
- Noise Figure Measurement Using Mixed-Signal BISTJie Qin, Charles E. Stroud, Foster F. Dai. 2180-2183 [doi]
- Congruence Synchronous Mirror DelayTsung-Chu Huang, Gau-Bin Chang, Ling Li. 2184-2187 [doi]
- Dual Active-Capacitive-Feedback Compensation for Area-Efficient Three-Stage AmplifiersSong Guo, Hoi Lee. 2188-2191 [doi]
- A 4-channel 12.5Gb/s Common-Gate Transimpedance Amplifier Array for DVI/HDMI ApplicationsK. Park, W. S. Oh, B.-Y. Choi, J.-W. Han, S. M. Park. 2192-2195 [doi]
- High-Accuracy, High-Precision DEM-CCII AmplifiersV. Stornelli, G. Ferri, A. De Marcellis, Christian Falconi, D. Mazzieri, Arnaldo D Amico. 2196-2199 [doi]
- Low-Voltage CMOS Single Ended and Fully Differential Amplifier with Programmable GainJose Luis Ruiz-Chavira, Jaime Ramírez-Angulo, Antonio J. López-Martín, Ramón González Carvajal, Antonio B. Torralba. 2200-2203 [doi]
- Mismatch-tolerant, Continuous Time, Gain Enhanced AmplifiersChristian Falconi, M. Cianella, Arnaldo D Amico, Giuseppe Scotti, Alessandro Trifiletti. 2204-2207 [doi]
- The Impact of Different Gain Control Methods on Performance of CMOS Variable-Gain LNAHsiao Wei Su, Zhi Hua Wang. 2208-2211 [doi]
- Rosenstark-like Representation of Feedback Amplifier ResistanceChristian Falconi, Arnaldo D Amico, Gianluca Giustolisi, Gaetano Palumbo. 2212-2215 [doi]
- Miller Compensation: Optimization with Current Buffer/AmplifierWalter Aloisi, Giuseppe Di Cataldo, Gaetano Palumbo, Salvatore Pennisi. 2216-2219 [doi]
- Low-Voltage Wilson Current Mirrors in CMOSBradley A. Minch. 2220-2223 [doi]
- A 0.5V Bulk-Input Operational Transconductance Amplifier with Improved Common-Mode FeedbackMichael Trakimas, Sameer R. Sonkusale. 2224-2227 [doi]
- On Problems of Compensated Continuous-Time Chebyshev Filters in the Time DomainJacek Piskorowski. 2228-2231 [doi]
- Analysis of Continuous-Time Digital Signal ProcessorsBob Schell, Yannis P. Tsividis. 2232-2235 [doi]
- A Continuous-Time Field Programmable Analog Array Using Parasitic Capacitance Gm-C FiltersFabian Henrici, Joachim Becker, Alexander Buhmann, Maurits Ortmanns, Yiannos Manoli. 2236-2239 [doi]
- Source-degenerated CMOS Transconductor with Auxiliary LinearizationPietro Monsurrò, Giuseppe Scotti, Alessandro Trifiletti, Salvatore Pennisi. 2240-2243 [doi]
- Simplified Low-Voltage CMOS Syllabic Companding Log Domain FilterIppei Akita, Kazuyuki Wada, Yoshiaki Tadokoro. 2244-2247 [doi]
- Analysis of Second-Order Modes of Linear Continuous-Time Systems under Positive-Real TransformationsShunsuke Koshita, Yousuke Mizukami, Taketo Konno, Masahide Abe, Masayuki Kawamata. 2248-2251 [doi]
- Performance Comparison of Switched-Capacitor and Switched-Current Pipeline ADCsGholamreza Nikandish, Behnam Sedighi, Mehrdad Sharif Bakhtiar. 2252-2255 [doi]
- CMOS Inductor Performance Estimation using Z- and S-parametersMaria Drakaki, Alkis A. Hatzopoulos, Stylianos Siskos. 2256-2259 [doi]
- An Algorithm for Automatic Tuning of PLLsEmad Hegazi. 2260-2263 [doi]
- Estimating Circuit Nonidealities of Continuous-Time Multibit Delta-Sigma ModulatorsAlexander Buhmann, Matthias Keller, Maurits Ortmanns, Yiannos Manoli. 2264-2267 [doi]
- Increasing the Sense Margin of 1T-1C Ferroelectric Random-Access MemoriesAly E. Salama, Sherif M. Sharroush, Mahmoud Y. Fekry. 2268-2271 [doi]
- Fault Tolerance Circuit for AM-OLEDDayong Li, Ming Liu, Wei Wang. 2272-2274 [doi]
- Chopper Modulation Improves OTA Information TransmissionNicole M. Nelson, Pamela Abshire. 2275-2278 [doi]
- Temperature-Robust Performance Yield through Supply Voltage SelectionDavid Wolpert, Paul Ampadu. 2279-2282 [doi]
- Subwavelength Plasmonic Bragg Reflector Structures for On-chip Optoelectronic ApplicationsAmir Hosseini, Yehia Massoud. 2283-2286 [doi]
- Dynamic Reconfigurable Architecture for a Low-Power Despreader in VSF-OFCDM SystemsTakayuki Sugawara, Shingo Yoshizawa, Yoshikazu Miyanaga. 2287-2290 [doi]
- An Efficient Method for Estimation of Autoregressive Signals Subject to Colored NoiseWei Xing Zheng. 2291-2294 [doi]
- Application of Sequential Monte Carlo to M-QAM Schemes in the Presence of Nonlinear Solid-State Power AmplifiersMahdi Shabany, P. Glenn Gulak. 2295-2298 [doi]
- PLL-Free Quadrature-Amplitude Modulation in Coherent Optical CommunicationUt-Va Koc. 2299-2302 [doi]
- Peak-Contrained WLS Strategy for FIR Digital Filter DesignHon Keung Kwan, Aimin Jiang. 2303-2306 [doi]
- Eigenvector and Fractionalization of Discrete Hadamard TransformC.-C. Tseng. 2307-2310 [doi]
- Noise Reduction System Based on LPEF and System Identification with Variable Step SizeNaoto Sasaoka, Masatoshi Watanabe, Yoshio Itoh, Kensaku Fujii. 2311-2314 [doi]
- Lagrangian Gradient for Principal Singular Component AnalysisMohammed A. Hasan. 2315-2318 [doi]
- Discrete Stockwell Transform and Reduced Redundancy Versions from Frame Theory ViewpointAlessandro Bastari, Stefano Squartini, Francesco Piazza. 2319-2322 [doi]
- Nonlinear Compensation for High Power Amplifiers using Genetic ProgrammingRobin Moritz, Henry Leung, Xinping Huang. 2323-2326 [doi]
- A New Binary Common Subexpression Elimination Method for Implementing Low Complexity FIR FiltersKavallur Gopi Smitha, A. Prasad Vinod. 2327-2330 [doi]
- A Diversity Controlled Genetic Algorithm for Optimization of FRM Digital Filters over DBNS Multiplier Coefficient SpaceSai Mohan Kilambi, Behrouz Nowrouzian. 2331-2334 [doi]
- Complexity Comparison of Linear-Phase Mth-Band and General FIR FiltersOscar Gustafsson, Håkan Johansson. 2335-2338 [doi]
- IIR Digital Filter Design with Novel Stability Criterion Based on Argument PrincipleAimin Jiang, Hon Keung Kwan. 2339-2342 [doi]
- FIR Filter Approximation by IIR Filters Based on Discrete-Time Vector FittingNgai Wong, Chi-Un Lei. 2343-2346 [doi]
- New Spatially Adaptive Wavelet-based Method for the Despeckling of Medical Ultrasound ImagesMd. Imamul Hassan Bhuiyan, M. Omair Ahmad, M. N. S. Swamy. 2347-2350 [doi]
- A Nanowatt Successive Approximation ADC with Offset Correction for Implantable Sensor ApplicationsKarim Abdelhalim, Leonard MacEachern, Samy A. Mahmoud. 2351-2354 [doi]
- A Low Power Digital Baseband for Wireless Endoscope CapsuleXinkai Chen, Guolin Li, Xiang Xie, Xiaowen Li, Zhihua Wang, Hong Chen. 2355-2358 [doi]
- A Wide Tuning Range CMOS Oscillator for an Optoelectronic Retinal Prosthesis SystemYan Huang, Emmanuel M. Drakakis, Chris Toumazou. 2359-2362 [doi]
- Ultra Low-Power Sensor Node for Wireless Health Monitoring SystemT. Hui Teo, Gin Kooi Lim, Darwin Sutomo David, Kuo Hwi Tan, Pradeep Kumar Gopalakrishnan, Rajnder Singh. 2363-2366 [doi]
- A Safe Transmission Strategy for Power and Data Recovery in Biomedical Implanted DevicesXiao Liu, Andreas Demosthenous, Nick Donaldson. 2367-2370 [doi]
- Area-Power Efficient Lifting-Based DWT Hardware for Implantable NeuroprostheticsAwais M. Kamboh, Matthew Raetz, Andrew Mason, Karim G. Oweiss. 2371-2374 [doi]
- A Bio-Inspired Adaptive Retinal Processing Neuron with Multiplexed Spiking OutputsDylan Banks, Patrick Degenaar, Chris Toumazou. 2375-2378 [doi]
- A New Handheld Biochip-based MicrosystemPaulo Alexandre Crisóstomo Lopes, J. Germano, T. M. Almeida, Leonel Sousa, Moisés Simões Piedade, Filipe Cardoso, H. A. Ferreira, P. P. Freitas. 2379-2382 [doi]
- An Implantable Long-term Bladder Urine Pressure Measurement System with a 1-atm Canceling Instrumentation AmplifierChua-Chin Wang, Chi-Chun Huang, Jian-Sing Liou, Yan-Jhin Ciou, I-Yu Huang, Chih-Peng Li, Yun-Chin Lee, Wen-Jen Wu. 2383-2386 [doi]
- A Basilar Membrane Resonator for an Active 2-D CochleaTara Julia Hamilton, Craig T. Jin, André van Schaik. 2387-2390 [doi]
- Circuit Techniques for Reducing Low Frequency Noise in Optical MEMS Position and Inertial SensorsRoy H. Olsson, Bianca E. N. Keeler, David A. Czaplewski, Dustin W. Carr. 2391-2394 [doi]
- A CMOS Image Sensor with Focal Plane Discrete Cosine Transform ComputationEdwin J. Tan, Zeljko Ignjatovic, Mark F. Bocko. 2395-2398 [doi]
- A CMOS Image Sensor using Variable Reference Time Domain EncodingMan Kay Law, Amine Bermak. 2399-2402 [doi]
- New Recursive Adaptive Beamforming Algorithms for Uniform Concentric Spherical Arrays with Frequency Invariant CharacteristicsH. H. Chen, Shing-Chow Chan, Ka-Leung Ho. 2403-2406 [doi]
- Complex Phenomena in SEPIC Converter Based on Sliding Mode ControlShi-Bing Wang, Yufei Zhou, Herbert H. C. Iu, Jun-Ning Chen. 2407-2410 [doi]
- A 1.2V-5V High Efficiency CMOS Charge Pump for Non-Volatile MemoriesAnna Richelli, Luca Mensi, Luigi Colalongo, Zsolt Kovács, Pier Luigi Rolandi. 2411-2414 [doi]
- CMOS Integrated Highly Efficient Full Wave RectifierChristian Peters, O. Kessling, Fabian Henrici, Maurits Ortmanns, Yiannos Manoli. 2415-2418 [doi]
- Boundaries Between Fast-and Slow-Scale Bifurcations in Parallel-Connected Buck ConvertersYuehui Huang, Herbert H. C. Iu, C. K. Michael Tse. 2419-2422 [doi]
- General-purpose ripple-based fast-scale instability prediction in switching power regulatorsEnric Rodriguez, Gerard Villar, Francesc Guinjoan, Alberto Poveda, Abdelali El Aroudi, Eduard Alarcón. 2423-2426 [doi]
- Analysis of an Adaptive Filter-bank for Harmonic Measurement and EstimationHanwu Sun, Louis Shue. 2427-2430 [doi]
- Short Circuit Current of Induction GeneratorsT. Sulawa, Zivan Zabar, Dariusz Czarkowski, L. Birenbaum, S. Lee, Y. TenAmi. 2431-2434 [doi]
- A Low-power Sensorless Inverter Controller of Brushless DC MotorsChua-Chin Wang, Gang-Neng Sung, Kuan-Wen Fang, Sheng-Lun Tseng. 2435-2438 [doi]
- Incremental Power Impedance Optimization Using Vector Fitting ModelingWanping Zhang, Chung-Kuan Cheng. 2439-2442 [doi]
- Risk Management - beyond Risk AnalysisLeontina Pinto, Rodrigo Maia, Leandro Tsunechiro, Jacques Szczupak, Bruno Dias. 2443-2446 [doi]
- A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked LoopLi Zhang, Baoyong Chi, Zhihua Wang, Hongyi Chen, Jinke Yao, Ende Wu. 2447-2450 [doi]
- A 5 Meps 100 USB2.0 Address-Event Monitor-Sequencer InterfaceRaphael Berner, Tobi Delbrück, Antón Civit Balcells, Alejandro Linares-Barranco. 2451-2454 [doi]
- A Silicon-on-Sapphire Low-Voltage Temperature Sensor for Energy ScavengersTolga Kaya, Hur Koser, Eugenio Culurciello. 2455-2458 [doi]
- On a novel Hybrid LQ-MCS control strategy and its application to a DC motorMario di Bernardo, Umberto Montanaro, Stefania Santini. 2459-2462 [doi]
- A Converter with Fixed Switching Frequency Adaptive Multi-Mode Control SchemeJaber A. Abu-Qahouq, Lilly Huang. 2463-2465 [doi]
- A General Noncoherent Chaos-Shift-Keying Communication System and its Performance AnalysisHongbin Chen, Jiuchao Feng, Chi K. Michael Tse. 2466-2469 [doi]
- A Method to Reduce the Effect of the Switching Noise in Analog-Mixed CircuitsChunyan Wang. 2470-2473 [doi]
- Occasional Delayed Feedback Control for Switched Autonomous SystemsTetsushi Ueta, Takuji Kousaka, Shigeki Tsuji. 2474-2477 [doi]
- Performance of Multi-User DCSK Communication System Over Multipath Fading ChannelsZhibo Zhou, Tong Zhou, Jinxiang Wang. 2478-2481 [doi]
- A Chaos-Modulated Dual Oscillator-Based Truly Random Number GeneratorSalih Ergün, Serdar Özoguz. 2482-2485 [doi]
- Phase Synchronization in Injection- Un locking Oscillator ArraysKuniyasu Shimizu, Hisa-Aki Tanaka, Osamu Masugata, Tetsuro Endo. 2486-2489 [doi]
- Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technologyRégis Roubadia, Sami Ajram, Guy Cathébras. 2490-2493 [doi]
- Adaptive Pinning Synchronization of A General Complex Dynamical NetworkJin Zhou, Junan Lu, Jinhu Lu. 2494-2497 [doi]
- Vertically-Integrated Three-Dimensional SOI PhotodetectorsEugenio Culurciello, Pujitha Weerakoon. 2498-2501 [doi]
- Distributed Optimization Over Wireless Sensor Networks using Swarm IntelligenceBo Wang, Zhihai He. 2502-2505 [doi]
- Compact, Low Power Wireless Sensor Network System for Line Crossing RecognitionChung-Ching Shen, Roni Kupershtok, Bo Yang, Felice Maria Vanin, Xi Shao, Datta Sheth, Neil Goldsman, Quirino Balzano, Shuvra S. Bhattacharyya. 2506-2509 [doi]
- A New 10 Gbps Traffic Management algorithm for High-speed NetworksFariborz Fereydouni-Forouzandeh, Otmane Aït Mohamed. 2510-2513 [doi]
- An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio ReceiversR. Mahesh, A. Prasad Vinod. 2514-2517 [doi]
- Frequency Response Masking based Reconfigurable Channel Filters for Software Radio ReceiversR. Mahesh, A. Prasad Vinod. 2518-2521 [doi]
- On the Suitability of Discrete-Time Receivers for Software-Defined RadioZhiyu Ru, Eric A. M. Klumperink, Bram Nauta. 2522-2525 [doi]
- Improved Factorization for Sample Rate Conversion In Software Defined RadiosFaheem Sheikh, Shahid Masud. 2526-2529 [doi]
- A Parallel, Multi-Resolution Sensing Technique for Multiple Antenna Cognitive RadiosNathan M. Neihart, Sumit Roy, David J. Allstot. 2530-2533 [doi]
- A CMOS Direct-Digital BPSK Modulator Using an Active Balun and Common-Gate SwitchesBrad R. Jackson, You Zheng, Carlos E. Saavedra. 2534-2537 [doi]
- A 2.5 Gb/s CMOS Burst-Mode Limiting Amplifier for GPON SystemChueh-Hao Yu, Day-Uei Li. 2538-2541 [doi]
- 50GHz Double-Balanced Up-Conversion Mixer Using CMOS 90nm ProcessIvan Chee Hong Lai, Yuki Kambayashi, Minoru Fujishima. 2542-2545 [doi]
- A 3.8-Gb/s CMOS Laser Driver with Automatic Power Control Using ThermistorsDay-Uei Li, Wen-Hui Chen, Long-Xi Chang, Chueh-Hao Yu. 2546-2549 [doi]
- A New CMOS BPSK Modulator with Optimal Transaction Bandwidth ControlA. Tang, F. Yuan, E. Law. 2550-2553 [doi]
- All-CMOS High-Speed CML Gates with Active Shunt-PeakingNader Kalantari, Michael M. Green. 2554-2557 [doi]
- The Wide Input Range Automatic-Threshold Control Circuit for High Definition Digital Audio InterfaceJi-Yong Jeong, Gil-Su Kim, Seung-Hoon Oh, Kyu-Young Kim, Soo-Won Kim. 2558-2561 [doi]
- Process Variation Compensation of a 2.4GHz LNA in 0.18um CMOS Using Digitally Switchable CapacitanceYike Cui, Baoyong Chi, Minjie Liu, Yulei Zhang, Yongming Li, Zhihua Wang, Patrick Chiang. 2562-2565 [doi]
- A Fully Integrated 2.4GHz CMOS Frequency Synthesizer Using a Ring-Based VCO with Inductive PeakingAhmed Saad, Khaled M. Sharaf. 2566-2569 [doi]
- Fault Tolerant Signal Processing for Masking Transient Errors in VLSI Signal ProcessorsW. Kenneth Jenkins, C. Radhakrishnan, S. Pal. 2570-2573 [doi]
- Implementation of Folded Sliding Block Viterbi Decoders for MB-OFDM UWB Communication SystemZhuo Xu, Junyan Ren, Xuejing Wang, Fan Ye. 2574-2577 [doi]
- An Energy-Proportion Synchronization Method for IR-UWB CommunicationsJing Wang, Lang Mai, Yanjie Peng, Jun Han, Xiaoyang Zeng. 2578-2581 [doi]
- Multiuser Detection Based on Particle Swarm Optimation AlgorithmZhen-qing Guo, Yang Xiao, Moon Ho Lee. 2582-2585 [doi]
- Application of a Heterogeneous Reconfigurable Architecture to OFDM Wireless SystemsAfshin Niktash, Hooman Parizi, Nader Bagherzadeh. 2586-2589 [doi]
- Modified SDF Architecture for Mixed DIF/DIT FFTSeungbeom Lee, Sin-Chong Park. 2590-2593 [doi]
- Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication SystemLiang Liu, Junyan Ren, Xuejing Wang, Fan Ye. 2594-2597 [doi]
- Effect of Word-length Precision on the Performance of MIMO SystemsChitranjan K. Singh, Naofal Al-Dhahir, Poras T. Balsara. 2598-2601 [doi]
- A Novel Low-Complexity Rayleigh Fader for Real-Time Channel ModelingChun-Hao Liao, To-Ping Wang, Tzi-Dar Chiueh. 2602-2605 [doi]
- A Real-Time Digital Baseband MIMO Channel Emulation SystemTo-Ping Wang, Chun-Hao Liao, Tzi-Dar Chiueh. 2606-2609 [doi]
- Efficient Complex Matrix Inversion for MIMO Software Defined RadioJohan Eilert, Di Wu, Dake Liu. 2610-2613 [doi]
- CMOS Millimeter-Wave Signal Sources and DetectorsK. K. O, C. Cao, E.-Y. Seok, S. Sankaran. 2614-2617 [doi]
- A 1.5-V Low-Power Common-Gate Low Noise Amplifier for Ultrawideband ReceiversRo-Min Weng, Po-Cheng Lin. 2618-2621 [doi]
- Modeling and Design of Ultrawideband Low Noise Amplifiers with Generalized Impedance Matching NetworksHamid Nejati, Tamer Ragheb, Arthur Nieuwoudt, Yehia Massoud. 2622-2625 [doi]
- A Subharmonic Injection-Locked Self-Oscillating MixerFotis Plessas, A. Papalambrou, Grigorios Kalivas. 2626-2629 [doi]
- Mixing in a 220MHz CMOS-MEMSJ. L. Lopez, Jordi Teva, Arantxa Uranga, F. Torres, Jaume Verd, Gabriel Abadal, Nuria Barniol, Jaume Esteve, Francesc Pérez-Murano. 2630-2633 [doi]
- A Brief Overview of the Complex Biological and Engineering NetworksJinhu Lu, Derong Liu. 2634-2637 [doi]
- On two approaches to analyzing consensus in complex networksChai Wah Wu. 2638-2641 [doi]
- Enhancing Synchronizabilities of Power-Law NetworksJin Fan, Xiao Fan Wang, Xiang Li. 2642-2645 [doi]
- Identification and monitoring of biological neural networkWallace Kit-Sang Tang, Mao Yu, Ljupco Kocarev. 2646-2649 [doi]
- Synchronization of the Time-Varying Discrete Biological NetworksLiang Chen, Jinhu Lu, Junan Lu. 2650-2653 [doi]
- Image Quality Assessment using Foveated Wavelet Error Sensitivity and Isotropic ContrastSusu Yao, Weisi Lin, Ee Ping Ong, Zhongkang Lu, Mei Hwan Loke, Zhengguo Li. 2654-2657 [doi]
- Pixel-Level Image Fusion Scheme based on Linear AlgebraRuth Aguilar-Ponce, J. Luis Tecpanecatl-Xihuitl, Ashok Kumar, Magdy Bayoumi. 2658-2661 [doi]
- Motion Adaptive Deinterlacing via Edge Pattern RecognitionGwo Giun Lee, Hsin-Te Li, Ming-Jiun Wang, He-Yuan Lin. 2662-2665 [doi]
- Background stabilization and debris flagging in launch pad videosKaushik Gopalan, Takis Kasparis. 2666-2669 [doi]
- Low-Complexity and Reliable Moving Objects Detection and Tracking for Aerial Video Surveillance with Small UAVSYu-Chia Chung, Zhihai He. 2670-2673 [doi]
- CNN Implementation of Spin Filters for Electronic Speckle Pattern Interferometry ApplicationsDavid López Vilariño, Victor M. Brea, Vicente Moreno, Diego Cabello. 2674-2677 [doi]
- Evolution of Pixel Level Snakes towards an efficient hardware implementationDavid López Vilariño, Piotr Dudek. 2678-2681 [doi]
- Area and Time Efficient Cellular Non-linear NetworksNatalia A. Fernandez-Garcia, Victor M. Brea, Diego Cabello. 2682-2685 [doi]
- An Organic Computing architecture for visual microprocessors based on Marching PixelsDietmar Fey, Marcus Komann, Frank Schurz, Andreas Loos. 2686-2689 [doi]
- A Focal-Plane Image Processor for Low Power Adaptive Capture and Analysis of the Visual StimulusCarlos M. Domínguez-Matas, Ricardo Carmona-Galán, Francisco J. Sánchez-Fernández, Ángel Rodríguez-Vázquez. 2690-2693 [doi]
- On the Effectiveness of Reducing Large Linear Networks with Many PortsJoão M. S. Silva, L. Miguel Silveira. 2694-2697 [doi]
- Noise Simulation and Modeling for MEMS Varactor Based RF VCOsJanakiram G. Sankaranarayanan, Kartikeya Mayaram. 2698-2701 [doi]
- GAPSYS: A GA-based Tool for Automated Passive Analog Circuit SynthesisAngan Das, Ranga Vemuri. 2702-2705 [doi]
- Fast Transient Simulation of Lossy Transmission LinesHe Peng, Chung-Kuan Cheng. 2706-2709 [doi]
- RLCSYN: RLC Equivalent Circuit Synthesis for Structure-Preserved Reduced-order Model of InterconnectFan Yang, Xuan Zeng, Yangfeng Su, Dian Zhou. 2710-2713 [doi]
- Design of IIR Variable Fractional Delay Digital FiltersHon Keung Kwan, Aimin Jiang. 2714-2717 [doi]
- On Frequency-Weighted l2-Sensitivity Analysis and Minimization of 2-D State-Space Digital Filters Subject to l2-Scaling ConstraintsTakao Hinamoto, Toru Oumi, Osemekhian I. Omoifo, Wu-Sheng Lu. 2718-2721 [doi]
- A Fast Convergence Algorithm for L2-Sensitivity Minimization of 2-D Separable-Denominator State-Space Digital FiltersShunsuke Yamaki, Masahide Abe, Masayuki Kawamata. 2722-2725 [doi]
- Digital Integrator Design Using Recursive Romberg Integration Rule and Fractional Sample DelayC.-C. Tseng. 2726-2729 [doi]
- A Low Power Digital Signal Processor with Adaptive Band Activation for Digital Hearing Aid ChipSeung-Jin Lee, Sunyoung Kim, Hoi-Jun Yoo. 2730-2733 [doi]
- Dynamic Reconfigurability in Embedded System DesignVincenzo Rana, Marco D. Santambrogio, Donatella Sciuto. 2734-2737 [doi]
- System-Level Design for Partially Reconfigurable HardwareYang Qu, Kari Tiensyrjä, Juha-Pekka Soininen, Jari Nurmi. 2738-2741 [doi]
- Dynamically Swappable Hardware Design in Partially Reconfigurable SystemsChun-Hsian Huang, Kai-Jung Shih, Chao-Sheng Lin, Shih-Shiue Chang, Pao-Ann Hsiung. 2742-2745 [doi]
- Modeling and Synthesis of Hardware-Software MorphingDirk Koch, Christian Haubelt, Thilo Streichert, Jürgen Teich. 2746-2749 [doi]
- Automated HDL Generation: Comparative EvaluationYana Yankova, Koen Bertels, Stamatis Vassiliadis, Roel Meeuws, Arcilio Virginia. 2750-2753 [doi]
- A Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC for High-Speed Networking ApplicationsChing-Te Chiu, Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ming-Chang Du, Ping-Ling Yang, Ming-Hao Lu, Fanta Chen, Hung-Yu Lin, Jen-Ming Wu, Shuo-Hung Hsu, Yarsun Hsu. 2754-2757 [doi]
- Performance of Quantized Min-Sum Decoding Algorithms for Irregular LDPC CodesDaesun Oh, Keshab K. Parhi. 2758-2761 [doi]
- Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part II - FPGA ImplementationFrançois Nougarou, Daniel Massicotte, Messaoud Ahmed-Ouameur. 2762-2765 [doi]
- A 1GHz Direct Digital Frequency Synthesizer Based on the Quasi-Linear Interpolation MethodAshkan Ashrafi, Aleksandar Milenkovic, Reza Adhami. 2766-2769 [doi]
- Evaluation of High Throughput Turbo-Decoder ArchitecturesMatthias May, Christian Neeb, Norbert Wehn. 2770-2773 [doi]
- High Read Stability and Low Leakage Cache Memory CellZhiyu Liu, Volkan Kursun. 2774-2777 [doi]
- Sub-1V, Robust and Compact 6T SRAM cell in Double Gate MOS technologyOlivier Thomas, Marina Reyboz, Marc Belleville. 2778-2781 [doi]
- Nonvolatile Flash Memories in Silicon-on-sapphire CMOSChun-Chen Yeh, Eugenio Culurciello. 2782-2785 [doi]
- Hardened by Design Techniques for Implementing Multiple-Bit Upset Tolerant Static MemoriesDaniel R. Blum, José G. Delgado-Frias. 2786-2789 [doi]
- An Adaptive Sleep Transistor Biasing Scheme for Low Leakage SRAMAfshin Nourivand, Chunyan Wang, M. Omair Ahmad. 2790-2793 [doi]
- A Varying Pulse Width Second Order Derivative Gaussian Pulse Generator for UWB Transceivers in CMOSHaolu Xie, Xin Wang, Albert Z. Wang, Bo Qin, Hongyi Chen, Yumei Zhou, Bin Zhao. 2794-2797 [doi]
- An On-Chip Delta-Time-to-Voltage Converter for Real-Time Measurement of Clock JitterKiyotaka Ichiyama, Masahiro Ishida, Takahiro J. Yamaguchi, Mani Soma. 2798-2801 [doi]
- A Multi-band CMOS Low Noise Amplifier for Multi-standard Wireless ReceiversChyuen-Wei Ang, Yuanjin Zheng, Chun-Huat Heng. 2802-2805 [doi]
- A Fully Integrated Inductorless Low Noise Amplifier with 1dB-Step Programmable Gain for FM Radio Receiver Front-EndJingyu Hu, Mike R. May, Matt D. Felder, Len DiSanza, Lawrence H. Ragan. 2806-2809 [doi]
- Exploration of energy requirements at the output of an LNA from a thermodynamic perspectiveMark Tuckwell, Christos Papavassiliou. 2810-2813 [doi]
- State-Space Analysis of Power Complementary Analog FiltersShunsuke Koshita, Masahide Abe, Masayuki Kawamata. 2814-2817 [doi]
- Analytical Design Equations for Class-E Power Amplifiers with Finite DC-Feed Inductance and Switch On-ResistanceMustafa Acar, Anne-Johan Annema, Bram Nauta. 2818-2821 [doi]
- Optimal Synthesis of MITE Translinear LoopsShyam Subramanian, David V. Anderson, Paul E. Hasler, Bradley A. Minch. 2822-2825 [doi]
- Process-Independent Resistor Temperature-Coefficients using Series/Parallel and Parallel/Series Composite ResistorsB. Robert Gregoire, Un-Ku Moon. 2826-2829 [doi]
- Linear Current Division PrinciplesHaibo Fei, Randall L. Geiger. 2830-2833 [doi]
- Low Power CMOS Image Sensors Employing Adaptive Bulk Biasing Control (AB2C) ApproachAlexander Fish, Tomer Rothschild, Avichay Hodes, Yonatan Shoshan, Orly Yadid-Pecht. 2834-2837 [doi]
- A CMOS Front-End for a Lossy Image Compression SensorZhiqiang Lin, Michael W. Hoffman, Walter D. Leon, Nathan Schemm, Sina Balkir. 2838-2841 [doi]
- Low Fixed Pattern Noise Current-mode Imager Using Velocity Saturated Readout TransistorsZheng Yang, Viktor Gruev, Jan Van der Spiegel. 2842-2845 [doi]
- Two Transistor Current Mode Active Pixel SensorViktor Gruev, Zheng Yang, Jan Van der Spiegel, Ralph Etienne-Cummings. 2846-2849 [doi]
- A Self-Biased and FPN-Compensated Digital APS for Hybrid CMOS ImagersFrancisco Serra-Graells, Josep Maria Margarit, Lluís Terés. 2850-2853 [doi]
- Low-Jitter Multi-phase Clock Generation: A Comparison between DLLs and Shift RegistersXiang Gao, Eric A. M. Klumperink, Bram Nauta. 2854-2857 [doi]
- On the Design of Error Cancellation Network for MASH Sigma-Delta-Frequency discriminatorsEssam Atalla, Emad Hegazi, M. Marzouk Ibrahim. 2858-2861 [doi]
- Design of Very Low Noise 4.2GHz Clapp VCOsRaghuram Jonnalagedda, Kartikeya Mayaram. 2862-2865 [doi]
- A 24-GHz CMOS Current-Mode Power Amplifier with High PAE and Output PowerChung-Yu Wu, Shun-Wei Hsu, Wen-Chieh Wang. 2866-2869 [doi]
- Precise RSSI with High Process Variation ToleranceChao Yang, Andrew Mason. 2870-2873 [doi]
- Enabling Technologies in Drug Delivery and Clinical CareAndreas G. Andreou, Jie Chen, Pau-Choo Chung, Stephen T. C. Wong. 2874-2877 [doi]
- Study of CuO Nanoparticle-induced Cell Death by High Content Cellular Fluorescence Imaging and AnalysisXiaobo Zhou, Jian Chen, Jinmin Zhu, Fuhai Li, Xudong Huang, Stephen T. C. Wong. 2878-2881 [doi]
- Gold-Based Nanoparticles for Breast Cancer Diagnosis and TreatmentJames Xing, Jie Zeng, Jing Yang, Tao Kong, Tao Xu, Wilson Roa, Xiaoping Wang, Jie Chen. 2882-2885 [doi]
- Localized closed-loop temperature control and regulation in hybrid silicon/silicone life science microsystemsJennifer Blain Christen, Andreas G. Andreou, Brian Iglehart. 2886-2889 [doi]
- Reliability Analysis of Physiological Phenomena by Cardiac Action Potential ModelChing-Hsing Luo, Po-Yuan Chen, Chun-Hao Teng, Sheng-Nan Wu, Ruey-Jen Sung. 2890-2893 [doi]
- Architecture for Multiple Reference Frame Variable Block Size Motion EstimationStephen Warrington, Subramania Sudharsanan, Wai-Yip Chan. 2894-2897 [doi]
- Memory Access Reduced Software Implementation of H.264/AVC Sub-pixel Motion Estimation Using Differential Data EncodingHyojin Choi, Wonchul Lee, Wonyong Sung. 2898-2901 [doi]
- Video Segmentation with Model-Based Sprite Generation for Panning Surveillance CamerasDer-Chun Cherng, Shao-Yi Chien. 2902-2905 [doi]
- Memory Cache Based Motion Compensation Architecture for HDTV H.264/AVC DecoderYu Li, Yanmei Qu, Yun He. 2906-2909 [doi]
- A Hardware-Efficient Dual-Standard VLSI Architecture for MC Interpolation in AVS and H.264Dajiang Zhou, Peilin Liu. 2910-2913 [doi]
- Models of Lava Flow Through the CNN-Based E^3 ArchitecturePaolo Arena, G. Buscemi, B. Carambia, C. Del Negro, Luigi Fortuna, Mattia Frasca, A. Vicari. 2914-2917 [doi]
- Applying CNN to CheminformaticsChristian Merkwirth, Maciej Ogorzalek. 2918-2921 [doi]
- Modeling of self-adaptive systems with SCADEMatthias Güdemann, Andreas Angerer, Frank Ortmeier, Wolfgang Reif. 2922-2925 [doi]
- Probabilistic Modelling of Phase-tuned Disparity Energy Neuron PopulationsEric K. C. Tsang, Bertram Emil Shi. 2926-2929 [doi]
- On the Implementation of Cellular Wave Computing Methods by Hardware LearningGunter Geis, Frank Gollas, Ronald Tetzlaff. 2930-2933 [doi]
- A Performance Driven Layout Compaction Optimization Algorithm for Analog CircuitsHenry H. Y. Chan, Zeljko Zilic. 2934-2937 [doi]
- Scalable Gate-Level Models for Power and Timing AnalysisMustafa Badaroglu, Geert Van der Plas, Piet Wambacq, Stéphane Donnay, Georges G. E. Gielen, Hugo De Man. 2938-2941 [doi]
- Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling PackingDan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara. 2942-2945 [doi]
- A Methodology for Efficient Space-Time Adapter Design Space Exploration: A Case Study of an Ultra Wide Band InterleaverCyrille Chavet, Philippe Coussy, Pascal Urard, Eric Martin. 2946-2949 [doi]
- A SIMULINK Block Set for the High-Level Simulation of Multistandard Radio ReceiversAlonso Morgado, Rocio del Río, José Manuel de la Rosa. 2950-2953 [doi]
- FRM Filter Design with Group Delay Constraint Using Second-Order Cone ProgrammingZhiping Lin, Yongzhi Liu. 2954-2957 [doi]
- Complexity Reduction of FRM Filters via Multiplication-Free Prefilter-Equalizer StructuresYong Lian, Chun Zhu Yang, Yong Ching Lim. 2958-2961 [doi]
- FRM-Based FIR Filters with Minimum Coefficient SensitivitiesYong Ching Lim, Ya Jun Yu, K. L. Teo, Tapio Saramäki. 2962-2965 [doi]
- Design of Diamond and Circular Filters by Semi-definite ProgrammingT. Q. Hung, H. D. Tuan, T. Q. Nguyen. 2966-2969 [doi]
- An Online Procedure for Linear-Phase 2-D FIR Filters of Smallest Size with Magnitude Error ConstraintXiaoping Lai, Hon Keung Kwan. 2970-2973 [doi]
- Improved Wideband Blind Adaptive System Identification Using Decorrelation Filters for the Localization of Multiple SpeakersAnthony Lombard, Herbert Buchner, Walter Kellermann. 2974-2977 [doi]
- Performance Evaluation of Convolutive Blind Source Separation of Mixtures of Unequal-Level Speech SignalsMalay Gupta, Scott C. Douglas. 2978-2981 [doi]
- On Modelling the Frequency Components of Speech with Norm-Invariant Joint DensitiesIntae Lee, Te-Won Lee. 2982-2985 [doi]
- Robust blind dereverberation of speech signals based on characteristics of short-time speech segmentsTomohiro Nakatani, Takafumi Hikichi, Keisuke Kinoshita, Takuya Yoshioka, Marc Delcroix, Masato Miyoshi, Biing-Hwang Juang. 2986-2989 [doi]
- Joint Source-Channel Modeling and Estimation for Speech DereverberationBiing-Hwang Juang, Tomohiro Nakatani. 2990-2993 [doi]
- Multiple-Width Bus Partitioning Approach to Datapath SynthesisArash Ahmadi, Mark Zwolinski. 2994-2997 [doi]
- High-Speed/Low-Power Mixed Full Adder Chains: Analysis and Comparison versus TechnologyMassimo Alioto, Gaetano Palumbo. 2998-3001 [doi]
- On the Hardware Reduction of z-Datapath of Vectoring CORDICR. Stapenhurst, K. Maharatna, Jimson Mathew, José L. Núñez-Yáñez, Dhiraj K. Pradhan. 3002-3005 [doi]
- Tertiary-Tree 12-GHz 32-bit Adder in 65nm TechnologyAmir Agah, Seid Mehdi Fakhraie, Azita Emami-Neyestanak. 3006-3009 [doi]
- Circuit implementation of floating point range reduction for trigonometric functionsXuehai Qian, Hao Zhang, Jingang Yang, He Huang, Junchao Zhang, Dongrui Fan. 3010-3013 [doi]
- A Low Power Phase-Change Random Access Memory using a Data-Comparison Write SchemeByung-Do Yang, Jae-Eun Lee, Jang-Su Kim, Junghyun Cho, Seung-Yun Lee, Byoung Gon Yu. 3014-3017 [doi]
- Comparison of Dual-Vt Configurations of SRAM Cell Considering Process-Induced Vt VariationsJungseob Lee, Azadeh Davoodi. 3018-3021 [doi]
- A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical VariationBastien Giraud, Amara Amara, Andrei Vladimirescu. 3022-3025 [doi]
- High Speed, Minimal Area, and Low Power SEC Code for DRAMs with Large I/O Data WidthsSang-uhn Cha, Hongil Yoon. 3026-3029 [doi]
- A Self-Biased Charge-Transfer Sense AmplifierSandeep Patil, Michael Wieckowski, Martin Margala. 3030-3033 [doi]
- A 12-mW Fully Integrated Low-IF dual-band GPS Receiver on 0.13-µm CMOSTamer A. Abdelrahim, Tarek Elesseily, Ahmed Saad Abdou, Khaled M. W. Sharaf. 3034-3038 [doi]
- A CMOS Integrated Power Detector for UWBKenneth A. Townsend, James W. Haslett, John Nielsen. 3039-3042 [doi]
- 4.7pJ/pulse 7th Derivative Gaussian Pulse Generator for Impulse Radio UWBTuan-Anh Phan, Vladimir Krizhanovskii, Seok-Kyun Han, Sang-Gug Lee, Hyun-seo Oh, Nae-Soo Kim. 3043-3046 [doi]
- A 40 GHz Quadrature LC VCO and Frequency Divider in 90-nm CMOS TechnologyMuhammad Usama, Tad A. Kwasniewski. 3047-3050 [doi]
- A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency DividerBaoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang. 3051-3054 [doi]
- A Low-Power, Compact, Adaptive Logarithmic Transimpedance Amplifier Operating over Seven Decades of CurrentArindam Basu, Ryan W. Robucci, Paul E. Hasler. 3055-3058 [doi]
- Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor NodesAdnan Gundel, William N. Carr. 3059-3062 [doi]
- An Unconstrained Architecture for High-Order Sigma Delta Force-Feedback Inertial SensorsJohan Raman, Pieter Rombouts, Ludo Weyten. 3063-3066 [doi]
- A Micropower Voltage, Current, and Temperature Reference for a Low-Power Capacitive Sensor InterfaceMatti Paavola, Mikko Saukoski, Mika Laiho, Kari Halonen. 3067-3070 [doi]
- High Precision 16-bit Readout Gas Sensor Interface in 0.13µm CMOSBalaji Jayaraman, Navakanta Bhat. 3071-3074 [doi]
- An AER Contrast Retina with On-Chip CalibrationJesús Costas-Santos, Teresa Serrano-Gotarredona, Rafael Serrano-Gotarredona, Bernabé Linares-Barranco. 3075-3078 [doi]
- Motion Detection Circuits for a Time-To-Travel AlgorithmRico Moeckel, Shih-Chii Liu. 3079-3082 [doi]
- A Spike-Based Saccadic Recognition SystemMatthias Oster, Patrick Lichtsteiner, Tobi Delbrück, Shih-Chii Liu. 3083-3086 [doi]
- A CMOS Expansion/Contraction Motion Sensor with a Retinal Processing Circuit for Z-motion Detection ApplicationsChung-Yu Wu, Chien-Ta Huang. 3087-3090 [doi]
- Dichromatic spectral measurement circuit in vanilla CMOSDaniel Bernhard Fasnacht, Tobi Delbrück. 3091-3094 [doi]
- A Nonlinear Model for Phase Noise and Jitter in LC OscillatorsJeffrey Johnson, Vipul Jain, Payam Heydari. 3095-3098 [doi]
- A Low Power BFSK Super-Regenerative TransceiverJames Ayers, Kartikeya Mayaram, Terri S. Fiez. 3099-3102 [doi]
- A 0.18µm CMOS 2.1GHz Sub-sampling Receiver Front End with Fully Integrated Second- and Fourth-Order Q-Enhanced FiltersHolly Pekau, James W. Haslett. 3103-3106 [doi]
- Diophantine Frequency Synthesis The Mathematical PrinciplesPaul-Peter Sotiriadis. 3107-3110 [doi]
- A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking RangeAdnan Gundel, William N. Carr. 3111-3114 [doi]
- In Vitro Epileptic Seizure Prediction MicrosystemJ. N. Y. Aziz, Rafal Karakiewicz, Roman Genov, A. W. L. Chiu, B. L. Bardakjian, M. Derchansky, P. L. Carlen. 3115-3118 [doi]
- Implantable MEMS Accelerometer Microphone for Cochlear ProsthesisDarrin J. Young, Mark A. Zurcher, Wen H. Ko, Maroun Semaan, Cliff A. Megerian. 3119-3122 [doi]
- Spike discrimination using amplitude measurements with a low-power CMOS neural amplifierTimothy K. Horiuchi, Dorielle Tucker, Kevin Boyle, Pamela Abshire. 3123-3126 [doi]
- Using Pulse Width Modulation for Wireless Transmission of Neural Signals in a Multichannel Neural Recording SystemMing Yin, Maysam Ghovanloo. 3127-3130 [doi]
- A Wireless IC for Wide-Range Neurochemical Monitoring Using Amperometry and Fast-Scan Cyclic VoltammetryMasoud Roham, Pedram Mohseni. 3131-3134 [doi]
- Combined Decoding and Flexible Transform Designs for Effective H.264/AVC DecodersYi-Chih Chao, Shih-Tse Wei, Jar-Ferr Yang, Bin-Da Liu. 3135-3138 [doi]
- A High-Speed/Low-Power Multiplier Using an Advanced Spurious Power Suppression TechniqueKuan-Hung Chen, Yuan-Sun Chu, Yu-Min Chen, Jiun-In Guo. 3139-3142 [doi]
- Statistical Analysis Based H.264 High Profile Deblocking SpeedupJian Lou, Ashish Jagmohan, Dake He, Ligang Lu, Ming-Ting Sun. 3143-3146 [doi]
- Context-based Arithmetic Coding Reexamined for DCT Video CompressionLi Zhang, Xiaolin Wu, Ning Zhang, Wen Gao, Qiang Wang, Debin Zhao. 3147-3150 [doi]
- An Area-efficient VLSI Implementation of CA-2D-VLC Decoder for AVSKe Zhang, Xiaoyang Wu, Lu Yu. 3151-3154 [doi]
- A Study on Convergence of Competitive CNNsMauro Di Marco, Mauro Forti, Massimo Grazzini, Paolo Nistri, Luca Pancioni. 3155-3158 [doi]
- Sufficient Conditions for 1-D CNNs with Opposite-Sign Templates to Perform Connected Component DetectionNorikazu Takahashi, Ken Ishitobi, Tetsuo Nishi. 3159-3162 [doi]
- Limit Cycles and Bifurcations in Nonlinear Oscillatory NetworksFernando Corinto, Valentina Lanza, Marco Gilli. 3163-3166 [doi]
- Small Amplitude, Phase Locked Response in Oscillatory Networks with DelaysMichele Bonnin, Fernando Corinto, Marco Gilli, Pier Paolo Civalleri. 3167-3170 [doi]
- Active Visual Tracking of Heading Direction By Combining Motion Energy NeuronsStanley Y. M. Lam, Bertram Emil Shi. 3171-3174 [doi]
- Use of a Variable Wordlength Technique in an OFDM Receiver to Reduce Energy DissipationShingo Yoshizawa, Yoshikazu Miyanaga. 3175-3178 [doi]
- A Low-Cost Phase-Noise Cancellation Method for OFDM SystemsDengwei Fu. 3179-3182 [doi]
- Fractionally Spaced Orthogonal Frequency Division Multiplexing SystemsChen Meng, Jamal Tuqan. 3183-3186 [doi]
- Adaptive Duplicated Filters and Interference Canceller for DS-CDMA Systems: Part I - AlgorithmFrançois Nougarou, Messaoud Ahmed-Ouameur, Daniel Massicotte. 3187-3190 [doi]
- Breakdown Point Analysis of a New M-Estimator for Robust Multiuser Detection in Non-Gaussian ChannelsT. Anil Kumar, K. Deergha Rao. 3191-3194 [doi]
- A Multiplier Structure Based on a Novel Real-time CSD RecodingYunhua Wang, Linda DeBrunner, Dayong Zhou, Victor E. DeBrunner. 3195-3198 [doi]
- High Speed and Area-Efficient Multiply Accumulate (MAC) Unit for Digital Signal Prossing ApplicationsA. Abdelgawad, Magdy Bayoumi. 3199-3202 [doi]
- Scaled Lifting Scheme and Generalized Reversible Integer TransformSoo-Chang Pei, Jian-Jiun Ding. 3203-3206 [doi]
- Novel Sparse OBC based Distributed Arithmetic Architecture for Matrix TransformsShrutisagar Chandrasekaran, Abbes Amira. 3207-3210 [doi]
- Low-power adaptive filter based on RNS componentsG. L. Bernocchi, Gian-Carlo Cardarilli, Andrea Del Re, Alberto Nannarelli, Marco Re. 3211-3214 [doi]
- Variability in VLSI Circuits: Sources and Design ConsiderationsMohamed H. Abu-Rahma, Mohab Anis. 3215-3218 [doi]
- Variability-Aware Synthesis for Wideband Low Noise AmplifiersYehia Massoud, Arthur Nieuwoudt, Tamer Ragheb. 3219-3222 [doi]
- Attaining Thermal Integrity in Nanometer ChipsJa Chun Ku, Yehea I. Ismail. 3223-3226 [doi]
- Substrate Noise Reduction Based On Noise Aware Cell DesignEmre Salman, Eby G. Friedman, Radu M. Secareanu, Olin L. Hartin. 3227-3230 [doi]
- Leakage-Aware Design of Nanometer SoCVolkan Kursun, Sherif A. Tawfik, Zhiyu Liu. 3231-3234 [doi]
- ECG Cancellation for Surface Electromyography Measurement Using Independent Component AnalysisYong Hu, Joseph Mak, Hongtao Liu, Keith D. K. Luk. 3235-3238 [doi]
- Linear Prediction Based Semi-Blind Channel Estimation for MIMO-OFDM SystemFeng Wan, Wei-Ping Zhu, M. N. S. Swamy. 3239-3242 [doi]
- Noisy Component Extraction (Noice)Wai Yie Leong, Danilo P. Mandic. 3243-3246 [doi]
- Measuring Dependence of Bin-wise Separated Signals for Permutation Alignment in Frequency-domain BSSHiroshi Sawada, Shoko Araki, Shoji Makino. 3247-3250 [doi]
- Closed Form Parameters Estimation for Near Field SourcesKe Deng, Qinye Yin, Huiming Wang. 3251-3254 [doi]
- Design of Fast Large Fan-In CMOS Multiplexers Accounting for InterconnectsMassimo Alioto, Gaetano Palumbo. 3255-3258 [doi]
- Application of Bit-level Pipelining to Delay Insensitive Null Convention AddersA. Neslin Ismailoglu, Murat Askar. 3259-3262 [doi]
- Digital Multiplication using Continuous Valued DigitsMitra Mirhassani, Majid Ahmadi, Graham A. Jullien. 3263-3266 [doi]
- An Asynchronous Dual-Rail Multiplier based on Energy-Efficient STFB TemplatesKok-Leong Chang, Bah-Hwee Gwee, Yuanjin Zheng. 3267-3270 [doi]
- Novel High-Speed Redundant Binary to Binary converter using Prefix NetworksSreehari Veeramachaneni, Kirthi M. Krishna, Lingamneni Avinash, Reddy Puppala Sreekanth, M. B. Srinivas. 3271-3274 [doi]
- A Low Power and Low Quantization Noise Digital Sigma-Delta Modulator for Wireless TransmittersViral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta. 3275-3278 [doi]
- A Low Area and Low Power Digital Band-Pass Sigma-Delta Modulator for Wireless TransmittersViral K. Parikh, Poras T. Balsara, Oren Eliezer, Jaimin Mehta. 3279-3282 [doi]
- CMOS High Power SPDT Switch using Multigate StructureMinsik Ahn, Chang-Ho Lee, Joy Laskar. 3283-3286 [doi]
- A Low Phase Noise Quad-Band CMOS VCO with Minimized Gain Variation for GSM/GPRS/EDGESohrab Samadian. 3287-3290 [doi]
- Injection Spurs due to Reference Frequency Retiming by a Channel Dependent Clock at the ADPLL RF Output and its MitigationKhurram Waheed, Robert B. Staszewski, John L. Wallberg. 3291-3294 [doi]
- An Adaptive Quality-Factor Bandpass FilterKofi M. Odame, Paul E. Hasler. 3295-3298 [doi]
- A Compact On-Chip Capacitive-Coupling Scheme for Very-Low Frequency ApplicationsJader A. De Lima. 3299-3302 [doi]
- A Practical CMOS Companding Sinh Lossy IntegratorAndreas G. Katsiamis, Henry M. D. Ip, Emmanuel M. Drakakis. 3303-3306 [doi]
- A 0.18µm CMOS 300MHz Current-Mode LF Seventh-order Linear Phase Filter for Hard Disk Read ChannelsXi Zhu, Yichuang Sun, James Moritz. 3307-3310 [doi]
- Design of Systems with Prescribed Impulse Response Based on Second-Order Cone ProgrammingMladen Vucic, Goran Molnar. 3311-3314 [doi]
- Single-Wafer Pressure Capacitive SensorR. G. Bolea, A. Luque, J. M. Quero. 3315-3318 [doi]
- CMOS Cantilever-based Oscillator for Attogram Mass SensingJaume Verd, Arantxa Uranga, Jordi Teva, Gabriel Abadal, F. Torres, Nuria Barniol, Francesc Pérez-Murano, Jaume Esteve. 3319-3322 [doi]
- Simultaneous Measurement of Temperature and Lateral Force Using an Arc-Shaped FBG Sensor ModuleZ. Cai, J. Hao, S. Takahashi, J. H. Ng, Y. Gong, P. Varghese. 3323-3326 [doi]
- Leakage-based On-Chip Thermal Sensor for CMOS TechnologyPablo Ituero, José L. Ayala, Marisa López-Vallejo. 3327-3330 [doi]
- A novel voltage-clamped CMOS ISFET sensor interfaceLeila Shepherd, Pantelis Georgiou, Chris Toumazou. 3331-3334 [doi]
- Improvement of Bootstrapped Switch using Track and Precharge PhaseRetdian A. Nicodimus, Shigetaka Takagi, Nobuo Fujii. 3335-3338 [doi]
- High-Voltage Analog Circuit Design using Thin-Oxide MOS Devices onlyDongwon Seo, Yuhua Guo, Manu Mishra. 3339-3342 [doi]
- High-Voltage DMOS Integrated Circuits with Floating Gate Protection TechniqueR. Chebli, Mohamad Sawan, Yvon Savaria, Kamal El-Sankary. 3343-3346 [doi]
- A Circuit-Based Noise Parameter Extraction Technique for MOSFETsReza Navid, Thomas H. Lee, Robert W. Dutton. 3347-3350 [doi]
- Monolithic Spiral Transformers: A Design MethodologyJeffrey S. Walling, David J. Allstot. 3351-3354 [doi]
- Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networksSylvie Renaud, Jean Tomas, Yannick Bornat, Adel Daouzli, Sylvain Saïghi. 3355-3358 [doi]
- Transistor Channel Dendrites implementing HMM classifiersPaul E. Hasler, Scott Kozoil, Ethan Farquhar, Arindam Basu. 3359-3362 [doi]
- Silicon neurons that burst when primedKai M. Hynna, Kwabena Boahen. 3363-3366 [doi]
- Modeling Synaptic Plasticity within Networks of Highly Accelerated I&F NeuronsJohannes Schemmel, Daniel Brüderle, Karlheinz Meier, Boris Ostendorf. 3367-3370 [doi]
- Spike-based learning in VLSI networks of integrate-and-fire neuronsGiacomo Indiveri, Stefano Fusi. 3371-3374 [doi]
- On the Compensation of Magnitude Response Mismatches in M-channel Time-interleaved ADCsStefan Mendel, Christian Vogel. 3375-3378 [doi]
- A 6-bit 2.5GSample/s Flash ADC using Immanent C2MOS Comparator in 0.18um CMOSSoon-Ik Cho, Suki Kim, Shin-Il Lim, Kwang-Hyun Baek. 3379-3382 [doi]
- Improved Background Algorithms for Pipeline ADC Full CalibrationAntonio J. Ginés, Eduardo J. Peralías, Adoración Rueda. 3383-3386 [doi]
- A distortion model for pipeline Analog-to-Digital convertersFrancesco Centurelli, Pietro Monsurrò, Alessandro Trifiletti. 3387-3390 [doi]
- A Pipelined A/D Conversion Technique with Low INL and DNLJingbo Duan, Fule Li, Liyuan Liu, Dongmei Li, Yongming Li, Zhihua Wang. 3391-3394 [doi]
- Area-Driven Decoupling Capacitance Allocation in Noise-Aware Floorplan for Signal IntegrityJin-Tai Yan, Zhi-Wei Chen, Ming-Yuen Wu. 3395-3398 [doi]
- On the Complexity of Three-Dimensional Channel Routing (Extended Abstract)Satoshi Tayu, Shuichi Ueno. 3399-3402 [doi]
- Construction of an (r11, r12, r22)-Tournament from a Score Sequence PairMasaya Takahashi, Takahiro Watanabe, Takeshi Yoshimura. 3403-3406 [doi]
- Application of Fast DC Analysis to Partitioning HypergraphsGaurav Trivedi, H. Narayanan. 3407-3410 [doi]
- Unified Quadratic Programming Approach For 3-D Mixed Mode PlacementHaixia Yan, Zhuoyuan Li, Xianlong Hong, Qiang Zhou. 3411-3414 [doi]
- A Pipelined Architecture Design for Trilateral Noise FilteringWen-Chung Kao, Hong-Shuo Tai, Chia-Pin Shen, Jia-An Ye, Hong-Fa Ho. 3415-3418 [doi]
- A PDP Sub-field Coding Algorithm for the Reduction of Errors due to Line Load VariationJin-Sung Kim, Hyuk-Jae Lee. 3419-3422 [doi]
- An Adaptive Block Size Phase Correlation Motion Estimation Using Adaptive Early Search Termination TechniqueYasser Ismail, Mohsen Shaaban, Magdy Bayoumi. 3423-3426 [doi]
- A Fast and reliable switching median filter for highly corrupted images by impulse noiseWei Ping, Li Junli, Lu Dongming, Chen Gang. 3427-3430 [doi]
- An OWE-based Algorithm for Line Scratches Restoration in Old MoviesJin Xu, Jinghuo Guan, Xingdong Wang, Jun Sun, Guangtao Zhai, Zhengguo Li. 3431-3434 [doi]
- High-Speed and Low-Cost Structures for Implementing Odd-Order Lagrange-Type Variable Fractional-Delay FiltersTian-Bo Deng. 3435-3438 [doi]
- A Simplified Structure for FIR Filters with an Adjustable Fractional DelayJuha Yli-Kaakinen, Tapio Saramäki. 3439-3442 [doi]
- Design of Allpass Fractional Delay Filter and Fractional Hilbert Transformer Using Closed-Form of Cepstral CoefficientsSoo-Chang Pei, Huei-Shan Lin, Peng-Hua Wang. 3443-3446 [doi]
- Closed-Form Design of Variable Fractional Order Integrator Using Complex CepstrumC.-C. Tseng. 3447-3450 [doi]
- A Greedy Common Subexpression Elimination Algorithm for Implementing FIR FiltersS. Vijay, A. Prasad Vinod, Edmund Ming-Kit Lai. 3451-3454 [doi]
- Using H.264/AVC-based Scalable Video Coding (SVC) for Real Time Streaming in Wireless IP NetworksThomas Schierl, Cornelius Hellge, Shpend Mirta, Karsten Grüneberg, Thomas Wiegand. 3455-3458 [doi]
- Fast Mode Decision Algorithms for Adaptive GOP Structure in the Scalable Extension of H.264/AVCChih-Wei Chiou, Chia-Ming Tsai, Chia-Wen Lin. 3459-3462 [doi]
- Scalable Video Streaming over Mobile WiMAXHung-Hui Juan, Hsiang-Chun Huang, ChingYao Huang, Tihao Chiang. 3463-3466 [doi]
- Sliding-Window Digital Fountain Codes for Streaming of Multimedia ContentsMattia C. O. Bogino, Pasquale Cataldi, Marco Grangetto, Enrico Magli, Gabriella Olmo. 3467-3470 [doi]
- Joint Source-Channel-Authentication Resource Allocation for Multimedia overWireless NetworksQibin Sun, Zhi Li, Yong Lian, Chang Wen Chen. 3471-3474 [doi]
- On the Performance of Two Constant Modulus Algorithms in Equalization with non-CM SignalsMaurice G. Bellanger. 3475-3478 [doi]
- Combined Linear Prediction and Subspace Based Blind EqualizersParthapratim De. 3479-3482 [doi]
- A proposal of a new blind equalizer using output signals of decision deviceHiroki Matsumoto, Shuntaro Takasaki, Toshihiro Furukawa. 3483-3485 [doi]
- Eigenvector Algorithms for Blind Deconvolution of MIMO-IIR SystemsMitsuru Kawamoto, Kiyotaka Kohno, Yujiro Inouye. 3486-3489 [doi]
- A Matrix Pseudo-Inversion Lemma and Its Application to Block-Based Adaptive Blind Deconvolution for MIMO SystemsKiyotaka Kohno, Yujiro Inouye, Mitsuru Kawamoto. 3490-3493 [doi]
- Cache Miss-Aware Dynamic Stack AllocationSung-Joon Jang, Moo-Kyoung Chung, Jaemoon Kim, Chong-Min Kyung. 3494-3497 [doi]
- Design of a Massively Parallel Vision Processor based on Multi-SIMD ArchitectureKota Yamaguchi, Yoshihiro Watanabe, Takashi Komuro, Masatoshi Ishikawa. 3498-3501 [doi]
- A Double-Issue Java Processor Design for Embedded ApplicationsHou-Jen Ko, Chun-Jen Tsai. 3502-3505 [doi]
- Latency-Tolerant Virtual Cluster Architecture for VLIW DSPPi-Chen Hsiao, Tay-Jyi Lin, Chih-Wei Liu, Chein-Wei Jen. 3506-3509 [doi]
- A Low-cost and High-performance SoC Design for OMA DRM2 ApplicationsYehua Gu, Xiaoyang Zeng, Jun Han, Jia Zhao. 3510-3513 [doi]
- Simple design equations of gain compression and distortion spectrum in broadband RF transceiversStefano Marsili, Manfred Punzenberger. 3514-3517 [doi]
- Analysis of Spurious Emission and In-Band Phase Noise of an All Digital Phase Locked Loop for RF Synthesis using a Frequency DiscriminatorChristian Wicpalek, T. Mayer, Linus Maurer, U. Vollenbruch, T. Pittorino, Andreas Springer. 3518-3521 [doi]
- Technique for Peak to Average Power Ratio Reduction suited for M-carrier WCDMA Base Station TransmittersStefano Marsili. 3522-3525 [doi]
- Logarithmic Codecs for Adaptive Beamforming in WCDMA Downlink ChannelsC. Litchfield, P. Lee, R. J. Langley, J. C. Batchelor. 3526-3529 [doi]
- Regularized Frequency Domain Equalization Algorithm and its VLSI ImplementationAndreas Burg, Simon Haene, Wolfgang Fichtner, Markus Rupp. 3530-3533 [doi]
- Design of Precise Gain GmC-leapfrog FiltersMikko Kaltiokallio, Saska Lindfors, Ville Saari, Jussi Ryynänen. 3534-3537 [doi]
- A Novel CMOS Envelope Detector StructureJuan Pablo Alegre, Santiago Celma, Belén Calvo, Jose Maria Garcia del Pozo. 3538-3541 [doi]
- A 600mV 3.6mW 68dB DR 4th Order Analog Base Band Filter for WLAN ReceiversMarcello De Matteis, Stefano D Amico, Andrea Baschirotto. 3542-3545 [doi]
- Analysis of Common-Mode Induced Even-Order Distortion in a Pseudo-Differential gm-C FilterVille Saari, Saska Lindfors. 3546-3549 [doi]
- Singly Terminated & Bi-Transversal Transmission Line Filters for High Speed Adaptive EqualizationShanthi Pavan. 3550-3553 [doi]
- A 4×4 Logarithmic Spike Timing Encoding Scheme for Olfactory Sensor ApplicationsBin Guo, Amine Bermak, Maxime Ambard, Dominique Martinez. 3554-3557 [doi]
- Incremental Encoder Based Position and Velocity Measurements VLSI Chip with Serial Peripheral InterfaceNdubuisi Ekekwe, Ralph Etienne-Cummings, Peter Kazanzides. 3558-3561 [doi]
- Amperometric Readout and Electrode Array Chip for Bioelectrochemical SensorsAndrew Mason, Yue Huang, Chao Yang, Jichun Zhang. 3562-3565 [doi]
- Digital Wideband Excitation Technique for Impedance-Based Structural Health Monitoring SystemsJina Kim, Benjamin L. Grisso, Dong S. Ha, Daniel J. Inman. 3566-3569 [doi]
- Bounded state space particle filter for network sensorsSilvana Sanudo, Favio R. Masson, Pedro Julian. 3570-3573 [doi]
- Voltage Elevator using a MEMS ResonatorJose M. Quero. 3574-3577 [doi]
- High-speed front end for LED-Photodiode based fluorescence lifetime measurement systemClement Joseph, Mounir Boukadoum, Joe Charlson, David Starikov, Abdelhak Bensaoula. 3578-3581 [doi]
- A 12.4 ENOB Incremental A/D Converter for High-Linearity Sensors Read-Out ApplicationsVincenzo Ferragina, Massimo Ferri, Marco Grassi, Andrea Baschirotto. 3582-3585 [doi]
- Glass Break Detector Analog Front-End Using Novel Classifier CircuitBrian Gestner, Jason Tanner, David V. Anderson. 3586-3589 [doi]
- An Incomplete Settling Technique for Pipelined Analog-to-Digital ConvertersFule Li, Zhihua Wang, Dongmei Li. 3590-3593 [doi]
- A Low-Cost Triple-Channel 10-bit 250MHz DAC IP in 65nm CMOS ProcessWen-Shen Chou, Shu-Chieh Yang, Fu-Lung Hsueh, Heng-Chang Huang, Chih-Ji Hsiao. 3594-3597 [doi]
- On-Line Histogram Equalization for Flash ADCYanyi Liu Wong, Marc H. Cohen, Pamela Abshire. 3598-3601 [doi]
- Low-Power CMOS Comparator with Embedded Amplification for Ultra-high-speed ADCsJ. P. Oliveira, João Goes, Bruno Esperanca, Nuno F. Paulino, J. Fernandes. 3602-3605 [doi]
- Low-power design technique for flash A/D converters based on reduction of the number of comparatorsTakahide Sato, Shigetaka Takagi, Nobuo Fujii. 3606-3609 [doi]
- A Blind Calibration Technique to Correct Memory Errors in Amplifier-sharing Pipelined ADCsMunkyo Seo, Sopan Joshi, Ian A. Young. 3610-3613 [doi]
- Quadrature Mismatch Shaping Techniques for Fully Differential CircuitsStijn Reekmans, Pieter Rombouts, Ludo Weyten. 3614-3617 [doi]
- Blue-Noise Sigma-Delta Modulator: Improving Substrate Noise and Nonlinear Amplifier Gain EffectsEric C. Moule, Zeljko Ignjatovic. 3618-3621 [doi]
- A 20-Bit Sigma-Delta D/A for Audio Applications in 0.13um CMOSLiyuan Liu, Run Chen, Dongmei Li. 3622-3625 [doi]
- Designing Complex Delta Sigma Modulators with Signal-Transfer Functions having Good Stop-Band AttenuationBupesh Pandita, K. W. Martin. 3626-3629 [doi]
- An Efficient Intra Mode Selection Algorithm For H.264 Based On Fast Edge ClassificationZhenyu Wei, Hongliang Li, King Ngi Ngan. 3630-3633 [doi]
- Improving Video Coding at Scene Cuts using Attention based Adaptive Bit AllocationZhibo Chen, Guoping Qiu, Yang Lu, Lihua Zhu, Quqing Chen, Xiaodong Gu, Charles Wang. 3634-3638 [doi]
- Improved Frame Level MAD Prediction and Bit Allocation Scheme for H.264/AVC Rate ControlXuan Jing, Lap-Pui Chau. 3639-3642 [doi]
- Adaptive Lagrange Multiplier Selection for Intra-Frame Video CodingXiang Li, Norbert Oertel, André Kaup. 3643-3646 [doi]
- Fast H.264 Inter Mode Decision Based on Inter and Intra Block ConditionsHung-Ming Wang, Ji-Kun Lin, Jar-Ferr Yang. 3647-3650 [doi]
- A Content-adaptive Fast Multiple Reference Frames Motion Estimation in H.264Qichao Sun, Xin-Hao Chen, Xiaoyang Wu, Lu Yu. 3651-3654 [doi]
- A Genetic Rhombus Pattern Search for Block Motion EstimationJang-Jer Tsai, Hsueh-Ming Hang. 3655-3658 [doi]
- Enhanced Strict Multilevel Successive Elimination Algorithm for Fast Motion EstimationYang Song, Zhenyu Liu, Takeshi Ikenaga, Satoshi Goto. 3659-3662 [doi]
- Low power variable block size motion estimation using pixel truncationAsral Bahari, Tughrul Arslan, Ahmet T. Erdogan. 3663-3666 [doi]
- Motion Detection by Using Entropy Image and Adaptive State-Labeling TechniqueMeng-chou Chang, Yong-Jie Cheng. 3667-3670 [doi]
- SAT-based ATPG for Path Delay Faults in Sequential CircuitsStephan Eggersglüß, Görschwin Fey, Rolf Drechsler. 3671-3674 [doi]
- CAD-Directed SEU Susceptibility Reduction in FPGA Circuits DesignsHamid R. Zarandi, Seyed Ghassem Miremadi, Dhiraj K. Pradhan, Jimson Mathew. 3675-3678 [doi]
- Reducing Test-bus Power Consumption in Huffman Coding Based Test Data Compression for SOCsChandan Giri, Santanu Chattopadhyay. 3679-3682 [doi]
- Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don t-Care FillingSying-Jyan Wang, Yan-Ting Chen, Katherine Shu-Min Li. 3683-3686 [doi]
- Watermarking for IP Protection through Template Substitution at Logic Synthesis LevelAijiao Cui, Chip-Hong Chang. 3687-3690 [doi]
- Design and Implementation of FPGA-based Systolic Array for LZ Data CompressionMohamed A. Abd El ghany, Aly E. Salama, Ahmed H. Khalil. 3691-3695 [doi]
- CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAsHamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan. 3696-3699 [doi]
- Collaborative Routing Architecture for FPGAYaling Ma, Mingjie Lin. 3700-3703 [doi]
- A Parallel Face Detection System Implemented on FPGANicolas Farrugia, Franck Mamalet, Sébastien Roux, Fan Yang, Michel Paindavoine. 3704-3707 [doi]
- A design framework for FPGA-based dynamically reconfigurable digital controllersCarlos Paiz, Boris Kettelhoit, Mario Porrmann. 3708-3711 [doi]
- An Efficient Error Control Scheme for Chip-to-Chip Optical InterconnectsJun Wang, Ge Zhang, Weiwu Hu. 3712-3715 [doi]
- Power Consumption Analysis of Flip-flop Based Interconnect PipeliningJingye Xu, Abinash Roy, Masud H. Chowdhury. 3716-3719 [doi]
- Asynchronous Adiabatic LogicMuhammad Arsalan, Maitham Shams. 3720-3723 [doi]
- A Dual-Threshold FPGA Routing Design for Subthreshold Leakage ReductionRodrigo Jaramillo-Ramirez, Mohab Anis. 3724-3727 [doi]
- Capacitively-Biased Floating-Gate CMOS: a New Logic FamilyRichard B. Wunderlich, Brian P. Degnan, Paul E. Hasler. 3728-3731 [doi]
- Delay Variability Due to Supply Variations in Transmission-Gate Full AddersMassimo Alioto, Gaetano Palumbo. 3732-3735 [doi]
- A Compact and Accurate Temperature-Dependent Model for CMOS Circuit DelayJa Chun Ku, Yehea I. Ismail. 3736-3739 [doi]
- New Power Gating Structure with Low Voltage Fluctuations by Bulk Controller in Transition ModeChung-Yu Chang, Wei-Bin Yang, Ching-Ji Huang, Cheng-Hsing Chien. 3740-3743 [doi]
- Comparative Analysis of Process Variation Impact on Flip-Flop Power-PerformanceMartin Hansson, Atila Alvandpour. 3744-3747 [doi]
- Floating millivolt reference for PTAT current generation in Subthreshold MOS LSIsKen Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya. 3748-3751 [doi]
- Application-Specific Instruction Generation for SOC ProcessorsShengjyi Yang, Chijie Lin, Chiuyun Hung, Jiying Wu, Yiwen Wang. 3752-3755 [doi]
- A Flexible Embedded SRAM IP CompilerYi Xu, Zhiqiang Gao, Xiangqing He. 3756-3759 [doi]
- A New Approach for Design and Verification of Transaction Level ModelsMohammad Reza Kakoee, Hamid Shojaei, Hassan Ghasemzadeh, Marjan Sirjani, Zainalabedin Navabi. 3760-3763 [doi]
- Low Power ASIP Architecture Optimization based on Target Application ProfilingSung Dae Kim, Myung Hoon Sunwoo. 3764-3767 [doi]
- A Hold Friendly Flip-Flop For Area RecoveryRubil Ahmadi. 3768-3771 [doi]
- On the Timing Uncertainty in Delay-Line-based Time Measurement Applications Targeting FPGAsAmir M. Amiri, Abdelhakim Khouas, Mounir Boukadoum. 3772-3775 [doi]
- Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAsHenrique C. Freitas, Dalton M. Colombo, Fernanda Lima Kastensmidt, Philippe Olivier Alexandre Navaux. 3776-3779 [doi]
- A New Montgomery Modular Multiplication Algorithm and its VLSI Design for RSA CryptosystemJun-Hong Chen, Haw-Shiuan Wu, Ming-Der Shieh, Wen-Ching Lin. 3780-3783 [doi]
- Approximate Frequency Response Models for RLC Power GridsDiaaEldin Khalil, Yehea I. Ismail. 3784-3787 [doi]
- Mismatch Compensated Design Techniques under Packaging-Induced Die StressDongwon Seo, Yuhua Guo. 3788-3791 [doi]
- 1-V Linear CMOS Transconductor with 65 dB THD in Nano-Scale CMOS TechnologyTien-Yu Lo, Chung-Chih Hung. 3792-3795 [doi]
- Dual-Output Trans-Impedance Amplifier of Cost-effective CMOS Optical Receiver for Digital Audio InterfacesKyu-Young Kim, Kwansu Shon, Soo-Won Kim, Jae-Tack Yoo. 3796-3799 [doi]
- New squaring circuit with reduced sensitivity to element mismatches using differentially driven translinear cellsT. M. Abdelrahman, Serdar Özoguz, Ahmed S. Elwakil. 3800-3803 [doi]
- A 109 nW, 44 ppm/°C CMOS Current Reference with Low Sensitivity to Process VariationsGiuseppe de Vita, Giuseppe Iannaccone. 3804-3807 [doi]
- Dynamic Eccentric Error Compensation for Track Following Control of Optical Disk DriverJeong Hun Kim, Kyu-sam Lim, Suki Kim. 3808-3811 [doi]
- CMOS Gyrator-C Active TransformersF. Yuan. 3812-3815 [doi]
- Run-Time Programming of Analog Circuits Using Floating-Gate TransistorsDavid W. Graham, Paul E. Hasler. 3816-3819 [doi]
- An Undersampling Digital MicrophoneSven Soell, Bernd Porr. 3820-3823 [doi]
- Fractional-Rate FM-to-Digital Delta-Sigma-ConvertersFrancesco Cannillo, Chris Toumazou. 3824-3827 [doi]
- Design of High-Performance Voltage Regulators Based on Frequency-Dependent Feedback FactorLiangguo Shen, Zushu Yan, Xing Zhang, Yuanfu Zhao, Yuan Wang. 3828-3831 [doi]
- A Reduced-Area, Low-Power CMOS Bandgap Reference CircuitSavvas Koudounas, Julius Georgiou. 3832-3835 [doi]
- Low-Voltage Temperature-Independent Current Reference with no External ComponentsBurak Kelleci, Aydin I. Karsilayan. 3836-3839 [doi]
- A new CMOS voltage reference scheme based on Vth-difference principleLuis E. Toledo, Walter J. Lancioni, Pablo A. Petrashin, Carlos Dualibe, Carlos Vázquez. 3840-3843 [doi]
- A Low-Power CMOS Voltage Reference Circuit Based On Subthreshold OperationChia-Wei Chang, Tien-Yu Lo, Chia-Min Chen, Kuo-Hsi Wu, Chung-Chih Hung. 3844-3847 [doi]
- A Sub-1V Low-Power High-Speed Static Frequency DividerKuo-Hsing Cheng, Cheng-Liang Hung, Chia-Wei Su. 3848-3851 [doi]
- Design of a 1-Volt and µ-power SARADC for Sensor Network ApplicationSang-Hyun Cho, Chang-Kyo Lee, Jong-In Song. 3852-3855 [doi]
- A Novel Low Power BPSK DemodulatorZhenying Luo, Sameer R. Sonkusale. 3856-3859 [doi]
- Deterministic DEM DAC Performance AnalysisHanjun Jiang, Degang Chen, Randall L. Geiger. 3860-3863 [doi]
- Process and Temperature Calibration of PLLs with BiST CapabilitiesRichard Geisler, John Liobe, Martin Margala. 3864-3867 [doi]
- Low frequency, current mode programmable KHN filters using large-valued active resistorsCarlos Muniz-Montero, Ramón González Carvajal, Alejandro Díaz-Sánchez, J. Miguel Rocha. 3868-3871 [doi]
- A Fully Programmable Analog Window ComparatorRui Xiao, Amit Laknaur, Haibo Wang. 3872-3875 [doi]
- Design of the Basic Building Block of a High-Speed Flexible and Modular Pipelined ADCAthon Zanikopoulos, Pieter Harpe, Hans Hegt, Arthur H. M. van Roermund. 3876-3879 [doi]
- Analog Implementation of a Mean Field Detector for Multiple Antenna SystemsJosep Soler Garrido, Robert J. Piechocki. 3880-3883 [doi]
- Fast Peak Detector with Improved Accuracy and Linearity for High-Frequency Waveform ProcessingCalogero D. Presti, Francesco Carrara, Antonino Scuderi, Giuseppe Palmisano. 3884-3887 [doi]
- A 2.24GHz Wide Range Low Jitter DLL-Based Frequency Multiplier using PMOS Active Load for Communication ApplicationsChih-Hsing Lin, Ching-Te Chiu. 3888-3891 [doi]
- A Wideband CMOS Mixer with Feedforward Compensated Differential TransconductorPei-Zong Rao, Tang-Yuan Chang, Ching-Piau Liang, Shyh-Jong Chung. 3892-3895 [doi]
- High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS GeneratorShubha Bommalingaiahnapallya, Kin-Joe Sham, Mahmoud Reza Ahmadi, Ramesh Harjani. 3896-3899 [doi]
- A CMOS class-E Power Amplifiers with Power ControlTongqiang Gao, Dongmei Li, Baoyong Chi, Zhihua Wang. 3900-3903 [doi]
- A Low-Area, 0.18µm CMOS, 10Gb/s Optical Receiver Analog Front EndMohsen Maadani, Seyed Mojtaba Atarodi. 3904-3907 [doi]
- Dual Band Antenna Equalizer Realized by Utilizing 0.18µm Si-Processing Technology for a Pifa-900Naoyuki Unno, Takashi Fujita, Peter Lindberg, B. Siddik Yarman, Nobuo Fujii. 3908-3911 [doi]
- A LO-leakage auto-calibrated CMOS IEEE802.11b/g WLAN transceiverHaiyong Wang, Guoliang Shou, Nanjian Wu. 3912-3915 [doi]
- A Power Efficient HBT Pulse Generator for UWB RadarsAlessio Cacciatori, Laura Lorenzi, Luigi Colalongo. 3916-3919 [doi]
- Inductive ESD Protection For Narrow Band and Ultra-Wideband CMOS Low Noise AmplifiersYanjie Wang, Anthony Ho, Kris Iniewski, Vincent C. Gaudet. 3920-3923 [doi]
- A dual-slope PFD/CP frequency synthesizer architecture with an adaptive self-tuning algorithmShuilong Huang, Zhihua Wang. 3924-3927 [doi]
- A 32-point FFT based Noise Reduction Algorithm for Single Channel Speech SignalsKunal Mukherjee, Bah-Hwee Gwee. 3928-3931 [doi]
- Optimization of Gabor Features for Text-Independent Speaker IdentificationVolker Mildner, Stefan Goetze, Karl-Dirk Kammeyer, Alfred Mertins. 3932-3935 [doi]
- A NMR Optimized Bitrate Transcoder for MPEG-2/4 LC-AACTe-Hsueh Lai, Chung-Neng Wang, Tihao Chiang. 3936-3939 [doi]
- A Pitch Estimation Algorithm Based on the Smooth Harmonic Average Peak-to-Valley EnvelopeArturo Camacho, John G. Harris. 3940-3943 [doi]
- An Approach for Voiced/Unvoiced Decision of Colored Noise-Corrupted SpeechCelia Shahnaz, Wei-Ping Zhu, M. Omair Ahmad. 3944-3947 [doi]
- Color Image Enhancement Based on Single-Scale Retinex With a JND-Based Nonlinear FilterDoo-Hyun Choi, Ick Hoon Jang, Mi Hye Kim, Nam Chul Kim. 3948-3951 [doi]
- Efficient Intra Prediction in H.264 Based on Intensity Gradient ApproachAn-Chao Tsai, Anand Paul, Jia-Ching Wang, Jhing-Fa Wang. 3952-3955 [doi]
- Adaptive Search Range Motion Estimation Algorithm for H.264/AVCTian Song, Kazuhiro Ogata 0002, Kosuke Saito, Takashi Shimamoto. 3956-3959 [doi]
- Extraction and Integration of Human Body Parts for 3-D Motion Analysis of Golf Swing from Single-Camera Video SequencesIbrahim Karliga, Jenq-Neng Hwang. 3960-3963 [doi]
- A 3D Integrated Feature-Extracting Image SensorZhengming Fu, Eugenio Culurciello. 3964-3967 [doi]
- A modular VLIW ProcessorVincent Brost, Fan Yang, Michel Paindavoine. 3968-3971 [doi]
- Accelerating Vector Operations by Utilizing Reconfigurable Coprocessor ArchitecturesHenrik Svensson, Thomas Lenart, Viktor Öwall. 3972-3975 [doi]
- Decoder-Friendly Adaptive Deblocking Filter (DF-ADF) Mode Decision in H.264/AVCYu Hu, Qing Li, Siwei Ma, C. C. Jay Kuo. 3976-3979 [doi]
- A VLSI Architecture for a Fast Computation of the 2-D Discrete Wavelet TransformChengjun Zhang, Chunyan Wang, M. Omair Ahmad. 3980-3983 [doi]
- Tiled Interleaving for Multi-Level 2-D Discrete Wavelet TransformJung-Wook Kim, Jinook Song, Seokho Lee, In-Cheol Park. 3984-3987 [doi]
- On the Angular Decomposition Technique for Computing the Discrete Fractional Fourier TransformMagdy T. Hanna. 3988-3991 [doi]
- 2-D Tridiagonal IIR Filters/Systems: State Space and Circuit RealizationsGeorge E. Antoniou. 3992-3995 [doi]
- Optimal Synthesis of State-Estimate Feedback Controllers with Minimum l2-Sensitivity and No Overflow OscillationsTakao Hinamoto, Takuro Kawagoe. 3996-3999 [doi]
- Image Denoising using Shiftable Directional Pyramid and Scale Mixtures of Complex GaussiansAn P. N. Vo, Truong T. Nguyen, Soontorn Oraintara. 4000-4003 [doi]
- Sampling at Minimum Sampling Rate for Signals in Shift Invariant SpacesBeilei Huang, Edmund Ming-Kit Lai, A. Prasad Vinod. 4004-4007 [doi]
- A Low Power Sinc3 Filter for Sigma-Delta ModulatorsA. Lombardi, Edoardo Bonizzoni, Piero Malcovati, Franco Maloberti. 4008-4011 [doi]
- Higher Clock Rate at Comparable IPC Through Reduced Circuit Complexity in Instruction Format Based Pipeline ClusteringJatan P. Shah, Rama Sangireddy. 4012-4015 [doi]
- An Adaptive Cross-Correlation Derivative Algorithm for Ultra-Low Power Time Delay MeasurementF. N. Martin Pirchio, Pedro Julián, Pablo Sergio Mandolesi, Alfonso Chacon-Rodriguez. 4016-4019 [doi]
- A Novel Fast Algorithm for Speech and Audio CodingÜmit Güz, Hakan Gürkan, B. Siddik Yarman. 4020-4023 [doi]