Katsumi Dosaka - researchr alias

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Viewing Publication 1 - 31 from 31

2013

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOSIsamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai. jssc, 48(11):2671-2680, 2013. [doi]

2010

A Complete Charge Recycling TCAM with Checkerboard Array Arrangement for Low Power ApplicationsKatsumi Dosaka, Daisuke Ogawa, Takahito Kusumoto, Masayuki Miyama, Yoshio Matsuda. ieicet, 93-C(5):685-695, 2010. [doi]

2009

On-Chip Memory Power-Cut Scheme Suitable for Low Power SoC PlatformHiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto. ieicet, 92-C(3):356-363, 2009. [doi]

2008

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia ProcessorTakeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. ieicet, 91-C(9):1409-1418, 2008. [doi]

2007

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPsKazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi. jssc, 42(11):2611-2619, 2007. [doi]

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing EngineTakeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. iscas 2007: 525-528 [doi]

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix ProcessorTakeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. ieicet, 90-D(8):1312-1315, 2007. [doi]

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table OptimizerTakeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. ieicet, 90-D(1):334-345, 2007. [doi]

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOIFukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto. ieicet, 90-C(4):765-771, 2007. [doi]

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified MemoryFukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto. jssc, 42(4):853-861, 2007. [doi]

The Design and Implementation of the Massively Parallel Processor Based on the Matrix ArchitectureHideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu. jssc, 42(1):183-192, 2007. [doi]

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix ArchitectureHideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto. jssc, 42(4):804-812, 2007. [doi]

A Voltage Scalable Advanced DFM RAM with Accelerated Screening for Low Power SoC PlatformHiroki Shimano, Fukashi Morishita, Katsumi Dosaka, Kazutami Arimoto. ieicet, 90-C(10):1927-1935, 2007. [doi]

2006

A Scalable ET2RAM (SETRAM) with Verify Control for SoC Platform Memory IP on SOIKazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Tetsushi Tanizaki, Takashi Ipposhi, Katsumi Dosaka. cicc 2006: 429-432 [doi]

An On-Chip Supply-Voltage Control System Considering PVT Variations for Worst-Caseless Lower Voltage SoC DesignTakayuki Gyohten, Fukashi Morishita, Isamu Hayashi, Mako Okamoto, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Yasutaka Horiba. ieicet, 89-C(11):1519-1525, 2006. [doi]

A 40GOPS 250mW massively parallel processor based on matrix architectureMasami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu. isscc 2006: 1616-1625 [doi]

A Reliability-Enhanced TCAM Architecture with Associated Embedded DRAM and ECCHideyuki Noda, Katsumi Dosaka, Hans Jürgen Mattausch, Tetsushi Koide, Fukashi Morishita, Kazutami Arimoto. ieicet, 89-C(11):1612-1619, 2006. [doi]

2005

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. iscas 2005: 5202-5205 [doi]

A capacitorless twin-transistor random access memory (TTRAM) on SOIFukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto. cicc 2005: 435-438 [doi]

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAMHideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto. cicc 2005: 451-454 [doi]

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled RefreshHideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara. ieicet, 88-C(4):622-629, 2005. [doi]

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM MacrosAkira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara. ieicet, 88-C(10):2020-2027, 2005. [doi]

2001

2000

Design methodology of the embedded DRAM with the virtual socket architectureMitsuya Kinoshita, Tadaaki Yamauchi, Teruhiko Amano, Katsumi Dosaka, Kenshin Arimoto. cicc 2000: 271-274 [doi]

1992

A 100-MHz 4-Mb cache DRAM with fast copy-back schemeKatsumi Dosaka, Yasuhiro Konishi, Kouji Hayano, Katsumitsu Himukashi, Akira Yamazaki, Hisashi Iwamoto, Masaki Kumanoya, Hisanori Hamano, Tsutomu Yoshihara. jssc, 27(11):1534-1539, November 1992. [doi]

1990

A 38-ns 4-Mb DRAM with a battery-backup (BBU) modeYasuhiro Konishi, Katsumi Dosaka, Takahiro Komatsu, Yoshinori Inoue, Masaki Kumanoya, Youichi Tobita, Hideki Genjyo, Masao Nagatomo, Tsutomu Yoshihara. jssc, 25(5):1112-1117, October 1990. [doi]

1989

Analysis of coupling noise between adjacent bit lines in megabit DRAMsYasuhiro Konishi, Masaki Kumanoya, Hiroyuki Yamasaki, Katsumi Dosaka, Tsutomu Yoshihara. jssc, 24(1):35-42, February 1989. [doi]

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