Hideyuki Noda - researchr alias

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Viewing Publication 1 - 26 from 26

2019

A Cost-Effective 1T-4MTJ Embedded MRAM Architecture with Voltage Offset Self-Reference Sensing Scheme for IoT ApplicationsMasanori Hayashikoshi, Hiroaki Tanizaki, Yasumitsu Murai, Takaharu Tsuji, Kiyoshi Kawabata, Koji Nii, Hideyuki Noda, Hiroyuki Kondo, Yoshio Matsuda, Hideto Hidaka. ieicet, 102-C(4):287-295, 2019. [doi]

2018

Low-Power Multi-Sensor System with Power Management and Nonvolatile Memory Access Control for IoT ApplicationsMasanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Yasumitsu Murai, Sugako Otani, Koji Nii, Yoshio Matsuda, Hiroyuki Kondo. tmscs, 4(4):784-792, 2018. [doi]

2017

2016

Low-power multi-sensor system with normally-off sensing technology for IoT applicationsMasanori Hayashikoshi, Hideyuki Noda, Hiroyuki Kawai, Hiroyuki Kondo. isocc 2016: 195-196 [doi]

2013

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOSIsamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai. jssc, 48(11):2671-2680, 2013. [doi]

2011

2008

Integration Architecture of Content Addressable Memory and Massive-Parallel Memory-Embedded SIMD Matrix for Versatile Multimedia ProcessorTakeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Takayuki Gyohten, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. ieicet, 91-C(9):1409-1418, 2008. [doi]

2007

Efficient Vertical/Horizontal-Space 1D-DCT Processing Based on Massive-Parallel Matrix-Processing EngineTakeshi Kumaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. iscas 2007: 525-528 [doi]

Acceleration of DCT Processing with Massive-Parallel Memory-Embedded SIMD Matrix ProcessorTakeshi Kumaki, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Yasuto Kuroda, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. ieicet, 90-D(8):1312-1315, 2007. [doi]

Real-Time Huffman Encoder with Pipelined CAM-Based Data Path and Code-Word-Table OptimizerTakeshi Kumaki, Yasuto Kuroda, Masakatsu Ishizaki, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. ieicet, 90-D(1):334-345, 2007. [doi]

A Capacitorless Twin-Transistor Random Access Memory (TTRAM) on SOIFukashi Morishita, Hideyuki Noda, Isamu Hayashi, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto. ieicet, 90-C(4):765-771, 2007. [doi]

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified MemoryFukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto. jssc, 42(4):853-861, 2007. [doi]

The Design and Implementation of the Massively Parallel Processor Based on the Matrix ArchitectureHideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu. jssc, 42(1):183-192, 2007. [doi]

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix ArchitectureHideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto. jssc, 42(4):804-812, 2007. [doi]

2006

2005

A CAM-Based Signature-Matching Co-processor with Application-Driven Power-Reduction FeaturesKazunari Inoue, Hideyuki Noda, Kazutami Arimoto, Hans Jürgen Mattausch, Tetsushi Koide. ieicet, 88-C(6):1332-1342, 2005. [doi]

CAM-based VLSI architecture for Huffman coding with real-time optimization of the code word table [image coding example]Takeshi Kumaki, Yasuto Kuroda, Tetsushi Koide, Hans Jürgen Mattausch, Hideyuki Noda, Katsumi Dosaka, Kazutami Arimoto, Kazunori Saito. iscas 2005: 5202-5205 [doi]

A capacitorless twin-transistor random access memory (TTRAM) on SOIFukashi Morishita, Hideyuki Noda, Takayuki Gyohten, Mako Okamoto, Takashi Ipposhi, Shigeto Maegawa, Katsumi Dosaka, Kazutami Arimoto. cicc 2005: 435-438 [doi]

A soft-error-immune maintenance-free TCAM architecture with associated embedded DRAMHideyuki Noda, Katsumi Dosaka, Fukashi Morishita, Kazutami Arimoto. cicc 2005: 451-454 [doi]

Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled RefreshHideyuki Noda, Kazunari Inoue, Hans Jürgen Mattausch, Tetsushi Koide, Katsumi Dosaka, Kazutami Arimoto, Kazuyasu Fujishima, Kenji Anami, Tsutomu Yoshihara. ieicet, 88-C(4):622-629, 2005. [doi]

A Study of Sense-Voltage Margins in Low-Voltage-Operating Embedded DRAM MacrosAkira Yamazaki, Fukashi Morishita, Naoya Watanabe, Teruhiko Amano, Masaru Haraguchi, Hideyuki Noda, Atsushi Hachisuka, Katsumi Dosaka, Kazutami Arimoto, Setsuo Wake, Hideyuki Ozaki, Tsutomu Yoshihara. ieicet, 88-C(10):2020-2027, 2005. [doi]

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