Table of Contents

• ReflectionsLaura Chizuko Fujino. 4 [doi]
• Foreword: Intelligent Chips for a Smart WorldBoris Murmann. 5 [doi]
• Session 1 overview: Plenary SessionAnantha Chandrakasan, Boris Murmann. 6-7 [doi]
• 1.1 A smart design paradigm for smart chipsCliff Hou. 8-13 [doi]
• 1.2 Dynamics of exponentials in circuits and systemsAhmad Bahai. 14-20 [doi]
• 1.3 The development of high-speed DNA sequencing: Jurassic Park, Neanderthal, Moore, and youJonathan Rothberg. 23 [doi]
• 1.4 Quantum computing - the next challenge in circuit and system designLieven M. K. Vandersypen, Antoni van Leeuwenhoek. 24-29 [doi]
• Session 2 overview: Power amplifiersKohei Onizuka, Abbas Komijani, Piet Wambacq. 30-31 [doi]
• 2.1 A 28GHz/37GHz/39GHz multiband linear Doherty power amplifier for 5G massive MIMO applicationsSong Hu, Fei Wang, Hua Wang. 32-33 [doi]
• 2.2 A fully integrated reconfigurable wideband envelope-tracking SoC for high-bandwidth WLAN applications in a 28nm CMOS technologyDebopriyo Chowdhury, Sraavan R. Mundlapudi, Ali Afsahi. 34-35 [doi]
• 2.3 A single-inductor dual-output converter with linear-amplifier-driven cross regulation for prioritized energy-distribution control of envelope-tracking supply modulatorShang-Hsien Yang, Yen-Ting Lin, Yu-Sheng Ma, Hung-Wei Chen, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 36-37 [doi]
• 2.4 A 2.4V 23.9dBm 35.7%-PAE -32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PAXun Liu, Heng Zhang, Min Zhao, Xuan Chen, Philip K. T. Mok, Howard C. Luong. 38-39 [doi]
• 2.5 A high-efficiency multiband Class-F power amplifier in 0.153µm bulk CMOS for WCDMA/LTE applicationsJenwei Ko, Xiaochuan Guo, Changhua Cao, Saravanan Rajapandian, Solti Peng, Jing Li, Wenchang Lee, Narayanan Baskaran, Caiyi Wang. 40-41 [doi]
• 2.6 A SiGe BiCMOS E-band power amplifier with 22% PAE at 18dBm OP1dB and 8.5% at 6dB back-off leveraging current clamping in a common-base stageJunlei Zhao, Elham Rahimi, Francesco Svelto, Andrea Mazzanti. 42-43 [doi]
• 2.7 A wideband 28GHz power amplifier supporting 8×100MHz carrier aggregation for 5G in 40nm CMOSSherif Shakib, Mohamed Elkholy, Jeremy Dunworth, Vladimir Aparin, Kamran Entesari. 44-45 [doi]
• 2.8 A Class-G voltage-mode Doherty power amplifierVoravit Vorapipat, Cooper S. Levy, Peter M. Asbeck. 46-47 [doi]
• Session 3 overview: Digital processorsThomas Burd, James Myers, Byeong-Gyu Nam. 48-49 [doi]
• 3.1 POWER9™: A processor family optimized for cognitive computing with 25Gb/s accelerator links and 16Gb/s PCIe Gen4Christopher J. Gonzalez, Eric Fluhr, Daniel Dreps, David Hogenmiller, Rahul M. Rao, Jose Paredes, Michael S. Floyd, Michael A. Sperling, Ryan Kruse, Vinod Ramadurai, Ryan Nett, Md. Saiful Islam, Juergen Pille, Donald W. Plass. 50-51 [doi]
• 3.2 Zen: A next-generation high-performance ×86 coreTeja Singh, Sundar Rangarajan, Deepesh John, Carson Henrion, Shane Southard, Hugh McIntyre, Amy Novak, Stephen Kosonocky, Ravi Jotwani, Alex Schaefer, Edward Chang, Joshua Bell, Michael Co. 52-53 [doi]
• 3.3 A 14nm 1GHz FPGA with 2.5D transceiver integrationDavid Greenhill, Ron Ho, David M. Lewis, Herman Schmit, Kok Hong Chan, Andy Tong, Sean Atsatt, Dana How, Peter McElheny, Keith Duwel, Jeffrey Schulz, Darren Faulkner, Gopal Iyer, George Chen, Hee Kong Phoon, Han Wooi Lim, Wei-Yee Koay, Ty Garibay. 54-55 [doi]
• 3.4 A 10nm FinFET 2.8GHz tri-gear deca-core CPU complex with optimized power-delivery network for mobile SoC performanceHugh Mair, Ericbill Wang, Alice Wang, Ping Kao, Yuwen Tsai, Sumanth Gururajarao, Rolf Lagerquist, Jin Son, Gordon Gammie, Gordon Lin, Achuta Thippana, Kent Li, Manzur Rahman, Wuan Kuo, David Yen, Yi-Chang Zhuang, Ue Fu, Hung-Wei Wang, Mark Peng, Cheng-Yuh Wu, Taner Dosluoglu, Anatoly Gelman, Daniel Dia, Girishankar Gurumurthy, Tony Hsieh, W. X. Lin, Ray Tzeng, Jengding Wu, C. H. Wang, Uming Ko. 56-57 [doi]
• 3.5 A 40nm flash microcontroller with 0.80µs field-oriented-control intelligent motor timer and functional safety system for next-generation EV/HEVHayato Kimura, Hideyuki Noda, Hisaaki Watanabe, Takashi Higuchi, Ryosaku Kobayashi, Masayuki Utsuno, Fumitake Takami, Sugako Otani, Masayuki Ito, Yasuhisa Shimazaki, Naoki Yada, Hiroyuki Kondo. 58-59 [doi]
• 3.6 A 60pJ/b 300Mb/s 128×8 Massive MIMO precoder-detector in 28nm FD-SOIHemanth Prabhu, Joachim Neves Rodrigues, Liang Liu, Ove Edfors. 60-61 [doi]
• 3.7 A 1920×1080 30fps 2.3TOPS/W stereo-depth processor for robust autonomous navigationZiyun Li, Qing Dong, Mehdi Saligane, Benjamin P. Kempke, Shijia Yang, Zhengya Zhang, Ronald G. Dreslinski, Dennis Sylvester, David Blaauw, Hun-Seok Kim. 62-63 [doi]
• Session 4 overview: ImagersHayato Wakabayashi, Jun Deguchi, Makoto Ikeda. 64-65 [doi]
• 4.1 A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representationBongki Son, Yunjae Suh, Sungho Kim, Heejae Jung, Jun-Seok Kim, Chang-Woo Shin, Keunju Park, Kyoobin Lee, Jin Man Park, Jooyeon Woo, Yohan Roh, Hyunku Lee, Yibing Michelle Wang, Ilia A. Ovsiannikov, Hyunsurk Ryu. 66-67 [doi]
• 4.2 A fully integrated CMOS fluorescence biochip for multiplex polymerase chain-reaction (PCR) processesArjang Hassibi, Rituraj Singh, Arun Manickam, Ruma Sinha, Bob Kuimelis, Sara Bolouki, Pejman Naraghi-Arani, Kirsten Johnson, Mark McDermott, Nicholas Wood, Piyush Savalia, Nader Gamini. 68-69 [doi]
• 4.3 A programmable sub-nanosecond time-gated 4-tap lock-in pixel CMOS image sensor for real-time fluorescence lifetime imaging microscopyMin-Woong Seo, Yuya Shirakawa, Yuriko Masuda, Yoshimasa Kawata, Keiichiro Kagawa, Keita Yasutomi, Shoji Kawahito. 70-71 [doi]
• 4.4 A sub-nW 80mlx-to-1.26Mlx self-referencing light-to-digital converter with AlGaAs photodiodeWootaek Lim, Dennis Sylvester, David Blaauw. 72-73 [doi]
• - temporal noise over 110dB dynamic range 3.4µm pixel pitch global shutter CMOS image sensor with dual-gain amplifiers, SS-ADC and multiple-accumulation shutterMasahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa. 74-75 [doi]
• 4.6 A 1/2.3inch 20Mpixel 3-layer stacked CMOS Image Sensor with DRAMTsutomu Haruta, Tsutomu Nakajima, Jun Hashizume, Taku Umebayashi, Hiroshi Takahashi, Kazuo Taniguchi, Masami Kuroda, Hiroshi Sumihiro, Koji Enoki, Takatsugu Yamasaki, Katsuya Ikezawa, Atsushi Kitahara, Masao Zen, Masafumi Oyama, Hiroki Koga, Hidenobu Tsugawa, Tomoharu Ogita, Takashi Nagano, Satoshi Takano, Tetsuo Nomoto. 76-77 [doi]
• 4.7 A 2.1Mpixel organic-film stacked RGB-IR image sensor with electrically controllable IR sensitivityShin'ichi Machida, Sanshiro Shishido, Takeyoshi Tokuhara, Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue. 78-79 [doi]
• -rms read-noise 32fps 0.5Mpixel high-sensitivity RG-less-pixel CMOS image sensor using bootstrapping resetMin-Woong Seo, Tongxi Wang, Sung-Wook Jun, Tomoyuki Akahori, Shoji Kawahito. 80-81 [doi]
• 4.9 A 1ms high-speed vision chip with 3D-stacked 140GOPS column-parallel PEs for spatio-temporal image processingTomohiro Yamazaki, Hironobu Katayama, Shuji Uehara, Atsushi Nose, Masatsugu Kobayashi, Sayaka Shida, Masaki Odahara, Kenichi Takamiya, Yasuaki Hisamatsu, Shizunori Matsumoto, Leo Miyashita, Yoshihiro Watanabe, Takashi Izawa, Yoshinori Muramatsu, Masatoshi Ishikawa. 82-83 [doi]
• Session 5 overview: Analog techniquesTim Piessens, Vadim Ivanov, Axel Thomsen. 84-85 [doi]
• 5.1 A 5×80W 0.004% THD+N automotive multiphase Class-D audio amplifier with integrated low-latency ΔΣ ADCs for digitized feedback after the output filterFred Mostert, Daniël Schinkel, Wouter Groothedde, Lucien J. Breems, Remko van Heeswijk, Marto-Jan Koerts, Eric van Iersel, Daniel Groeneveld, Gertjan van Holland, Patrick Zeelen, Derk-Jan Hissink, Martin Pos, Paul Wielage, Fre Jorritsma, Marc Klein Middelink. 86-87 [doi]
• 5.2 An 8Ω 10W 91%-power-efficiency 0.0023%-THD+N multi-level Class-D audio amplifier with folded PWMJi-Hun Lee, Jun-Suk Bang, Kiduk Kim, Hui-Dong Gwon, Sang-Hui Park, Yeunhee Huh, Kye-Seok Yoon, Jong-Beom Baek, Yong-Min Ju, Gibbeum Lee, Homin Park, Hyeon-Min Bae, Gyu-Hyeong Cho. 88-89 [doi]
• 5.3 A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted loadMing Ding, Yao-Hong Liu, Yan Zhang 0018, Chuang Lu, Peng Zhang, Benjamin Busze, Christian Bachmann, Kathleen Philips. 90-91 [doi]
• 5.4 Frequency-locked-loop ring oscillator with 3ns peak-to-peak accumulated jitter in 1ms time window for high-resolution frequency countingKarthik Pappu, George Pieter Reitsma, Sumant Bapat. 92-93 [doi]
• 5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loopJahyun Koo, Kyoung-sik Moon, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 94-95 [doi]
• 5.6 A 0.68nW/kHz supply-independent Relaxation Oscillator with ±0.49%/V and 96ppm/°C stabilityAnand Savanth, James Myers, Alex S. Weddell, David Flynn, Bashir M. Al-Hashimi. 96-97 [doi]
• 5.7 A 19nV/√Hz-noise 2µV-offset 75µA low-drift capacitive-gain amplifier with switched-capacitor ADC driving capabilityHanqing Wang, Gerard Mora-Puchalt, Colin Lyden, Roberto Maurino, Christian Birk. 98-99 [doi]
• 5.8 A 9.3nW all-in-one bandgap voltage and current reference circuitYoungwoo Ji, Cheonhoo Jeon, Hyunwoo Son, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 100-101 [doi]
• 2 areaYing-Chih Hsu, Chia-Liang Tai, Mei-Chen Chuang, Alan Roth, Eric G. Soenen. 102-103 [doi]
• 2 Class-D controllerWeiwei Xu, Prasanna Upadhyaya, Xiaoyue Wang, Randy Tsang, Li Lin. 104-105 [doi]
• 5.11 A 65nm inverter-based low-dropout regulator with rail-to-rail regulation and over -20dB PSR at 0.2V lowest supply voltageFan Yang, Philip K. T. Mok. 106-107 [doi]
• Session 6 overview: Ultra-high-speed wirelineSimone Erba, Takayuki Shibasaki, Frank O'Mahony. 108-109 [doi]
• 6.1 A 56Gb/s PAM-4/NRZ transceiver in 40nm CMOSPen-Jui Peng, Jeng-Feng Li, Li-Yang Chen, Jri Lee. 110-111 [doi]
• 6.2 A 60Gb/s 288mW NRZ transceiver with adaptive equalization and baud-rate clock and data recovery in 65nm CMOS technologyJaeduk Han, Yue Lu, Nicholas Sutardja, Elad Alon. 112-113 [doi]
• 6.3 A 40-to-56Gb/s PAM-4 receiver with 10-tap direct decision-feedback equalization in 16nm FinFETJay Im, Dave Freitas, Arianne Roldan, Ronan Casey, Stanley Chen, Adam Chou, Tim Cronin, Kevin Geary, Scott McLeod, Lei Zhou, Ian Zhuang, Jaeduk Han, Sen Lin, Parag Upadhyaya, Geoff Zhang, Yohan Frans, Ken Chang. 114-115 [doi]
• 6.4 A 64Gb/s PAM-4 transmitter with 4-Tap FFE and 2.26pJ/b energy efficiency in 28nm CMOS FDSOIGiovanni Steffan, Emanuele Depaoli, Enrico Monaco, Nicolo Sabatino, Walter Audoglio, Augusto Andrea Rossi, Simone Erba, Matteo Bassi, Andrea Mazzanti. 116-117 [doi]
• 6.5 A 1.8pJ/b 56Gb/s PAM-4 transmitter with fractionally spaced FFE in 14nm CMOSTimothy O. Dickson, Herschel A. Ainspan, Mounir Meghelli. 118-119 [doi]
• 6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOSWahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi. 120-121 [doi]
• 6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter toleranceJoshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi. 122-123 [doi]
• Session 7 overview: Wireless transceiversYuu Watanabe, Danielle Griffith, Aarno Pärssinen. 124-125 [doi]
• 7.1 An 802.11ac dual-band reconfigurable transceiver supporting up to four VHT80 spatial streams with 116fsrms-jitter frequency synthesizer and integrated LNA/PA delivering 256QAM 19dBm per stream achieving 1.733Gb/s PHY rateTsung-Ming Chen, Yi Lu, Pang-Ning Chen, Yu-hsien Chang, Ming-Chung Liu, Po-Yu Chang, Chia-Jen Liang, Yi-Chu Chen, Hsi-Liang Lu, Jian-Yu Ding, Chin-Chung Wang, YuLi Hsueh, Jen-Che Tsai, Min-Shun Hsu, Yuan-Hung Chung, George Chien. 126-127 [doi]
• 7.2 A 28GHz 32-element phased-array transceiver IC with concurrent dual polarized beams and 1.4 degree beam-steering resolution for 5G communicationBodhisatwa Sadhu, Yahya M. Tousi, Joakim Hallin, Stefan Sahl, Scott K. Reynolds, Orjan Renstrom, Kristoffer Sjogren, Olov Haapalahti, Nadav Mazor, Bo Bokinge, Gustaf Weibull, Hakan Bengtsson, Anders Carlinger, Eric Westesson, Jan-Erik Thillberg, Leonard Rexberg, Mark Yeck, Xiaoxiong Gu, Daniel J. Friedman, Alberto Valdes-Garcia. 128-129 [doi]
• 7.3 A 40nm low-power transceiver for LTE-A Carrier AggregationChinq-Shiun Chiu, Shih-Chieh Yen, Chi-Yao Yu, Tzung-Han Wu, Chung-Yun Chou, Sheng-Che Tseng, Chih-Hsien Shen, Yu-Tsung Lu, Hsinhung Chen, Song-Yu Yang, Yen-Tso Chen, Guang-Kaai Dehng, Yangjian Chen, Christophe Beghein, Dimitris Nalbantis, Manel Collados, Bernard Tenbroek, Jonathan Strange, Caiyi Wang. 130-131 [doi]
• 3 wireless sensor node with 20m non-line-of-sight communicationLi-Xuan Chuo, Yao Shi, Zhihong Luo, Nikolaos Chiotellis, Zhiyoong Foo, Gyouho Kim, Yejoong Kim, Anthony Grbic, David D. Wentzloff, Hun-Seok Kim, David Blaauw. 132-133 [doi]
• 7.5 A TCXO-less 100Hz-minimum-bandwidth transceiver for ultra-narrow-band sub-GHz IoT cellular networksDavid Lachartre, Francois Dehmas, Carolynn Bernier, Christophe Fourtet, Laurent Ouvry, Florent Lepin, Eric Mercier, Steve Hamard, Lionel Zirphile, Sebastien Thuries, Fabrice Chaix. 134-135 [doi]
• 7.6 A +8dBm BLE/BT transceiver with automatically calibrated integrated RF bandpass filter and -58dBc TX HD2Wei Yang, De-yong Hu, Chun Kit Lam, Ji Qing Cui, Lip Kai Soh, De-Cheng Song, Xiao Wei Zhong, Hon Cheong Hor, Chee-Lee Heng. 136-137 [doi]
• 7.7 A 118mW 23.3GS/s dual-band 7.3GHz and 8.7GHz impulse-based direct RF sampling radar SoC in 55nm CMOSNikolaj Andersen, Kristian Granhaug, Jørgen Andreas Michaelsen, Sumit Bagga, Håkon A. Hjortland, Mats Risopatron Knutsen, Tor Sverre Lande, Dag T. Wisland. 138-139 [doi]
• Session 8 overview: Digital PLLs and security circuitsYasuhisa Shimazaki, John Maneatis, Edith Beigné. 140-141 [doi]
• 8.1 Improved power-side-channel-attack resistance of an AES-128 core via a security-aware integrated buck voltage regulatorMonodeep Kar, Arvind Singh, Sanu Mathew, Anand Rajan, Vivek De, Saibal Mukhopadhyay. 142-143 [doi]
• 8.2 8Mb/s 28Mb/mJ robust true-random-number generator in 65nm CMOS based on differential ring oscillator with feedback resistorsEunhwan Kim, Minah Lee, Jae-Joon Kim. 144-145 [doi]
• 2 2-transistor amplifier-based Physically Unclonable Function (PUF) with 1.67% native instabilityKaiyuan Yang, Qing Dong, David Blaauw, Dennis Sylvester. 146-147 [doi]
• 8.4 A 2.5ps 0.8-to-3.2GHz bang-bang phase- and frequency-detector-based all-digital PLL with noise self-adjustmentTae-Kwang Jang, Seokhyeon Jeong, Dongsuk Jeon, Kyojin David Choo, Dennis Sylvester, David Blaauw. 148-149 [doi]
• 8.5 A 0.42ps-jitter -241.7dB-FOM synthesizable injection-locked PLL with noise-isolation LDOHuy Cu Ngo, Kengo Nakata, Toru Yoshioka, Yuki Terashima, Kenichi Okada, Akira Matsuzawa. 150-151 [doi]
• 8.6 A 2.5-to-5.75GHz 5mW 0.3psrms-jitter cascaded ring-based digital injection-locked clock multiplier in 65nm CMOSDaniel Coombs, Ahmed Elkholy, Romesh Kumar Nandwana, Ahmed Elmallah, Pavan Kumar Hanumolu. 152-153 [doi]
• 2 highly synthesizable TDC- and DCO-less fractional-N PLL with a seamless lock range of fREF to 1GHzHwasuk Cho, Kihwan Seong, Kwang-Hee Choi, Jin Hyeok Choi, Byungsub Kim, Hong June Park, Jae-Yoon Sim. 154-155 [doi]
• Session 9 overview: SensorsPedram Lajevardi, Masayuki Miyamoto, Makoto Ikeda. 156-157 [doi]
• 2 resolution FOMSining Pan, Yanquan Luo, Saleh Heidary Shalmany, Kofi A. A. Makinwa. 158-159 [doi]
• 9.2 A 0.6nJ -0.22/+0.19°C inaccuracy temperature sensor using exponential subthreshold oscillation dependenceKaiyuan Yang, Qing Dong, Wanyeong Jung, Yiqun Zhang 0002, Myungjoon Choi, David Blaauw, Dennis Sylvester. 160-161 [doi]
• 9.3 A BJT-based temperature sensor with a packaging-robust inaccuracy of ±0.3°C (3σ) from -55°C to +125°C after heater-assisted voltage calibrationBahman Yousefzadeh, Kofi A. A. Makinwa. 162-163 [doi]
• 2 background resonance frequency tuning circuit based on noise observation for a 1.71mW CT-ΔΣ MEMS gyroscope readout system with 0.9°/h bias instabilityMaximilian Marx, Daniel DeDorigo, Sebastian Nessler, Stefan Rombach, Michael Maurer, Yiannos Manoli. 164-165 [doi]
• 9.5 A 1.8V true-differential 140dB SPL full-scale standard CMOS MEMS digital microphone exhibiting 67dB SNRElmar Bach, Richard Gaggl, Luca Sant, Cesare Buffa, Snezana Stojanovic, Dietmar Straeussnigg, Andreas Wiesbauer. 166-167 [doi]
• 9.6 A 3.9kHz-frame-rate capacitive touch system with pressure/tilt angle expressions of active stylus using multiple-frequency driving method for 65″ 104×64 touch screen panelJae-Sung An, Sang-Hyun Han, Ju Eon Kim, Dong Hyun Yoon, Young-Hwan Kim, Han-Hee Hong, Jae-Hun Ye, Sung-Jin Jung, Seung Hwan Lee, Ji-Yong Jeong, Kwang-Hyun Baek, Seong-Kwan Hong, Oh-Kyong Kwon. 168-169 [doi]
• 9.7 A 6.9mW 120fps 28×50 capacitive touch sensor with 41.7dB SNR for 1mm stylus using current-driven ΔΣ ADCsHyunseok Hwang, Hyeyeon Lee, Hongchae Kim, Youngcheol Chae. 170-171 [doi]
• 9.8 An energy-efficient 3.7nV/√Hz bridge-readout IC with a stable bridge offset compensation schemeHui Jiang, Kofi A. A. Makinwa, Stoyan Nihtianov. 172-173 [doi]
• 9.9 A 0.6nm resolution 19.8mW eddy-current displacement sensor interface with 126MHz excitationVikram Chaturvedi, Mohammad Reza Nabavi, Johan Vogel, Kofi A. A. Makinwa, Stoyan Nihtianov. 174-175 [doi]
• Session 10 overview: DC-DC convertersHoi Lee, Gerard Villar Pique, Axel Thomsen. 176-177 [doi]
• 2-power-density 82%-efficiency fully integrated 3∶1 Switched-Capacitor DC-DC converter in baseline 28nm CMOS using Stage Outphasing and Multiphase Soft-ChargingNicolas Butzen, Michiel Steyaert. 178-179 [doi]
• 10.2 A digitally controlled 94.8%-peak-efficiency hybrid switched-capacitor converter for bidirectional balancing and impedance-based diagnostics of lithium-ion battery arraysChristopher Schaef, Eric Din, Jason T. Stauth. 180-181 [doi]
• 10.3 A 94.2%-peak-efficiency 1.53A direct-battery-hook-up hybrid Dickson switched-capacitor DC-DC converter with wide continuous conversion ratio in 65nm CMOSWen-Chuen Liu, Pourya Assem, Yutian Lei, Pavan Kumar Hanumolu, Robert C. N. Pilawa-Podgurski. 182-183 [doi]
• 10.4 A hybrid inductor-based flying-capacitor-assisted step-up/step-down DC-DC converter with 96.56% efficiencyYong-Min Ju, Se-un Shin, Yeunhee Huh, Sang-Hui Park, Jun-Suk Bang, Kiduk Kim, Sung-Won Choi, Ji-Hun Lee, Gyu-Hyeong Cho. 184-185 [doi]
• 10.5 A three-level single-inductor triple-output converter with an adjustable flying-capacitor technique for low output ripple and fast transient responseLi-Cheng Chu, Wen-Hau Yang, Xiao-Qing Zhang, Yan-Jiun Lai, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 186-187 [doi]
• 10.6 A 30MHz hybrid buck converter with 36mV droop and 125ns 1% settling time for a 1.25A/2ns load transientLin Cheng, Wing-Hung Ki. 188-189 [doi]
• 10.7 A 25MHz 4-phase SAW hysteretic DC-DC converter with 1-cycle APC achieving 190ns tsettle to 4A load transient and above 80% efficiency in 96.7% of the power rangeBumkil Lee, Min Kyu Song, Ashis Maity, D. Brian Ma. 190-191 [doi]
• 6 dynamic rangeArun Paidimarri, Anantha P. Chandrakasan. 192-193 [doi]
• Session 11 overview: Nonvolatile memory solutionsTakashi Kono, Ki Tae Park, Leland Chang. 194-195 [doi]
• 11.1 A 512Gb 3b/cell flash memory on 64-word-line-layer BiCS technologyRyuji Yamashita, Sagar Magia, Tsutomu Higuchi, Kazuhide Yoneya, Toshio Yamamura, Hiroyuki Mizukoshi, Shingo Zaitsu, Minoru Yamashita, Shunichi Toyama, Norihiro Kamae, Juan Lee, Shuo Chen, Jiawei Tao, William Mak, Xiaohua Zhang, Ying Yu, Yuko Utsunomiya, Yosuke Kato, Manabu Sakai, Masahide Matsumoto, Hardwell Chibvongodze, Naoki Ookuma, Hiroki Yabe, Subodh Taigor, Rangarao Samineni, Takuyo Kodama, Yoshihiko Kamata, Yuzuru Namai, Jonathan Huynh, Sung-En Wang, Yankang He, Trung Pham, Vivek Saraf, Akshay Petkar, Mitsuyuki Watanabe, Koichiro Hayashi, Prashant Swarnkar, Hitoshi Miwa, Aditya Pradhan, Sulagna Dey, Debasish Dwibedy, Thushara Xavier, Muralikrishna Balaga, Samiksha Agarwal, Swaroop Kulkarni, Zameer Papasaheb, Sahil Deora, Patrick Hong, Meiling Wei, Gopinath Balakrishnan, Takuya Ariki, Kapil Verma, Chang Hua Siau, Yingda Dong, Ching-Huang Lu, Toru Miwa, Farookh Moogat. 196-197 [doi]
• 11.2 A 1Mb embedded NOR flash memory with 39µW program power for mm-scale high-temperature sensor nodesQing Dong, Yejoong Kim, Inhee Lee, Myungjoon Choi, Ziyun Li, Jingcheng Wang, Kaiyuan Yang, Yen-Po Chen, Junjie Dong, Minchang Cho, Gyouho Kim, Wei-Keng Chang, Yun-Sheng Chen, Yu-Der Chih, David Blaauw, Dennis Sylvester. 198-199 [doi]
• 11.3 A 10nm 32Kb low-voltage logic-compatible anti-fuse one-time-programmable memory with anti-tampering sensing schemeShau-Yu Chou, Yu-Shiang Chen, Jun-Hao Chang, Yu-Der Chih, Tsung-Yung Jonathan Chang. 200-201 [doi]
• 11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memoryChulbum Kim, Ji-Ho Cho, Woopyo Jeong, Il Han Park, Hyun Wook Park, Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-Lo Ahn, Jiyoung Lee, Jong-Hoon Lee, SeungBum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, Byunghoon Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung Hoon Kim, Dongkyu Yoon, Ki-Sung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-yub Lee, Ki Tae Park, Kyehyun Kyung. 202-203 [doi]
• Session 12 overview: SRAMFatih Hamzaoglu, Chun Shiah, Leland Chang. 204-205 [doi]
• 12.1 A 7nm 256Mb SRAM in high-k metal-gate FinFET technology with write-assist circuitry for low-VMIN applicationsJonathan Chang, Yen-Huei Chen, Wei-Min Chan, Sahil Preet Singh, Hank Cheng, Hidehiro Fujiwara, Jih-Yu Lin, Kao-Cheng Lin, John Hung, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Quincy Li, Chih-Yung Lin, Mu-Chi Chiang, Shien-Yang Wu. 206-207 [doi]
• 12.2 A 7nm FinFET SRAM macro using EUV lithography for peripheral repair analysisTaejoong Song, Hoonki Kim, Woojin Rim, Yongho Kim, Sunghyun Park, Changnam Park, Minsun Hong, Giyong Yang, Jeongho Do, Jinyoung Lim, Seungyoung Lee, Ingyum Kim, Sanghoon Baek, Jonghoon Jung, Daewon Ha, Hyungsoon Jang, Taejung Lee, Chul-Hong Park, Bongjae Kwon, Hyuntaek Jung, Sungwee Cho, Yongjae Choo, Jaeseung Choi. 208-209 [doi]
• 12.3 A low-power and high-performance 10nm SRAM architecture for mobile applicationsMichael Clinton, Hank Cheng, H. J. Liao, Robin Lee, Ching-Wei Wu, Johnny Yang, Hau-Tai Hsieh, Frank Wu, Jung-Ping Yang, Atul Katoch, Arun Achyuthan, Donald Mikan, Bryan Sheffield, Jonathan Chang. 210-211 [doi]
• 2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%Igor Arsovski, Michael Fragano, Robert M. Houle, Akhilesh Patil, Van Butler, Raymond Kim, Ramon Rodriguez, Tom Maffitt, Joseph J. Oler, John Goss, Christopher Parkinson, Michael A. Ziegerhofer, Steven Burns. 212-213 [doi]
• Session 13 overview: High-performance transmittersGuang-Kaai Dehng, Kyoohyun Lim, Aarno Pärssinen. 214-215 [doi]
• 13.1 A fully integrated multimode front-end module for GSM/EDGE/TD-SCDMA/TD-LTE applications using a Class-F CMOS power amplifierMing-Da Tsai, Chien-Cheng Lin, Ping-Yu Chen, Tao-Yao Chang, Chien-Wei Tseng, Lai-Ching Lin, Chris Beale, Bosen Tseng, Bernard Tenbroek, Chinq-Shiun Chiu, Guang-Kaai Dehng, George Chien. 216-217 [doi]
• 13.2 A digital multimode polar transmitter supporting 40MHz LTE Carrier Aggregation in 28nm CMOSMichael Fulde, Alexander Belitzer, Zdravko Boos, Michael Bruennert, Jonas Fritzin, Hans Geltinger, Marcus Groinig, Daniel Gruber, Simon Gruenberger, Thomas Hartig, Vahur Kampus, Boris Kapfelsperger, Franz Kuttner, Stephan Leuschner, Thomas Maletz, Andreas Menkhoff, Jose Moreira, Alan Paussa, Davide Ponton, Harald Pretl, Daniel Sira, Ulrich Steinacker, Nenad Stevanovic. 218-219 [doi]
• 13.3 A SAW-less reconfigurable multimode transmitter with a voltage-mode harmonic-reject mixer in 14nm FinFET CMOSVenumadhav Bhagavatula, Dae Hyun Kwon, Jaehun Lee, Quang-Diep Bui, Jeong-Hyun Choi, Siuchuang-Ivan Lu, Sang-Won Son. 220-221 [doi]
• 13.4 All-digital RF transmitter in 28nm CMOS with programmable RX-band noise shapingEnrico Roverato, Marko Kosunen, Koen Cornelissens, Sofia Vatti, Paul Stynen, Kaoutar Bertrand, Teuvo Korhonen, Hans Samsom, Patrick Vandenameele, Jussi Ryynänen. 222-223 [doi]
• 13.5 A 0.35-to-2.6GHz multilevel outphasing transmitter with a digital interpolating phase modulator enabling up to 400MHz instantaneous bandwidthMarko Kosunen, Jerry Lemberg, Mikko Martelius, Enrico Roverato, Tero Nieminen, Mikko Englund, Kari Stadius, Lauri Anttila, Jorma Pallonen, Mikko Valkama, Jussi Ryynänen. 224-225 [doi]
• 13.6 A 2.4GHz WLAN digital polar transmitter with synthesized digital-to-time converter in 14nm trigate/FinFET technology for IoT and wearable applicationsPaolo Madoglio, Hongtao Xu, Kailash Chandrashekar, Luis Cuellar, Muhammad Faisal, Yee William Li, Hyung Seok Kim, Khoa Minh Nguyen, Yulin Tan, Brent R. Carlton, Vaibhav Vaidya, Yanjie Wang, Thomas Tetzlaff, Satoshi Suzuki, Amr Fahim, Parmoon Seddighrad, Jianyong Xie, Zhichao Zhang, Divya Shree Vemparala, Ashoke Ravi, Stefano Pellerano, Yorgos Palaskas. 226-227 [doi]
• 2 digital power amplifier with hybrid time/amplitude control achieving 22.5dBm at 28% PAE for 802.11gDavid Cousinard, Renaldi Winoto, Hao Li, Yuan Fang, Amir Ghaffari, Ashkan Olyaei, Ovidiu Carnu, Philip Godoy, Alden Wong, Xingliang Zhao, Jiexi Liu, Arnab Mitra, Randy Tsang, Li Lin. 228-229 [doi]
• 13.8 A 24dBm 2-to-4.3GHz wideband digital Power Amplifier with built-in AM-PM distortion self-compensationJong Seok Park, Yanjie Wang, Stefano Pellerano, Christopher D. Hull, Hua Wang. 230-231 [doi]
• 13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAEAntonio Passamani, Davide Ponton, Edwin Thaller, Gerhard Knoblinger, Andrea Neviani, Andrea Bevilacqua. 232-233 [doi]
• 13.10 A >1W 2.2GHz switched-capacitor digital power amplifier with wideband mixed-domain multi-tap FIR filtering of OOB noise floorRitesh Bhat, Jin Zhou, Harish Krishnaswamy. 234-235 [doi]
• Session 14 overview: Deep-learning processorsTakashi Hashimoto, Mahesh Mehendale, Byeong-Gyu Nam. 236-237 [doi]
• 14.1 A 2.9TOPS/W deep convolutional neural network SoC in FD-SOI 28nm for intelligent embedded systemsGiuseppe Desoli, Nitin Chawla, Thomas Boesch, Surinder-pal Singh, Elio Guidetti, Fabio De Ambroggi, Tommaso Majo, Paolo Zambotti, Manuj Ayodhyawasi, Harvinder Singh, Nalin Aggarwal. 238-239 [doi]
• 14.2 DNPU: An 8.1TOPS/W reconfigurable CNN-RNN processor for general-purpose deep neural networksDongjoo Shin, Jinmook Lee, Jinsu Lee, Hoi-Jun Yoo. 240-241 [doi]
• 14.3 A 28nm SoC with a 1.2GHz 568nJ/prediction sparse deep-neural-network engine with >0.1 timing error rate tolerance for IoT applicationsPaul N. Whatmough, Sae Kyu Lee, Hyunkwang Lee, Saketh Rama, David M. Brooks, Gu-Yeon Wei. 242-243 [doi]
• 14.4 A scalable speech recognizer with deep-neural-network acoustic models and voice-activated power gatingMichael Price, James R. Glass, Anantha P. Chandrakasan. 244-245 [doi]
• 14.5 Envision: A 0.26-to-10TOPS/W subword-parallel dynamic-voltage-accuracy-frequency-scalable Convolutional Neural Network processor in 28nm FDSOIBert Moons, Roel Uytterhoeven, Wim Dehaene, Marian Verhelst. 246-247 [doi]
• 14.6 A 0.62mW ultra-low-power convolutional-neural-network face-recognition processor and a CIS integrated with always-on haar-like face detectorKyeongryeol Bong, Sungpill Choi, Changhyeon Kim, Sanghoon Kang, Youchang Kim, Hoi-Jun Yoo. 248-249 [doi]
• 14.7 A 288µW programmable deep-learning processor with 270KB on-chip weight storage using non-uniform memory hierarchy for mobile intelligenceSuyoung Bang, Jingcheng Wang, Ziyun Li, Cao Gao, Yejoong Kim, Qing Dong, Yen-Po Chen, Laura Fick, Xun Sun, Ronald G. Dreslinski, Trevor N. Mudge, Hun-Seok Kim, David Blaauw, Dennis Sylvester. 250-251 [doi]
• 14.8 A 135mW fully integrated data processor for next-generation sequencingYi-Chung Wu, Jui-Hung Hung, Chia-Hsiang Yang. 252-253 [doi]
• Session 15 overview: Innovations in technologies and circuitsJan Genoe, Hiroshi Fuketa, Eugenio Cantatore. 254-255 [doi]
• 15.1 Large-scale acquisition of large-area sensors using an array of frequency-hopping ZnO thin-film-transistor oscillatorsYasmin Afsar, Tiffany Moy, Nicholas Brady, Sigurd Wagner, James C. Sturm, Naveen Verma. 256-257 [doi]
• 15.2 A flexible ISO14443-A compliant 7.5mW 128b metal-oxide NFC barcode tag with direct clock division circuit from 13.56MHz carrierKris Myny, Yi-Cheng Lai, Nikolaos Papadopoulos, Florian De Roose, Marc Ameys, Myriam Willegems, Steve Smout, Soeren Steudel, Wim Dehaene, Jan Genoe. 258-259 [doi]
• 15.3 An a-IGZO asynchronous delta-sigma modulator on foil achieving up to 43dB SNR and 40dB SNDR in 300Hz bandwidthCarmine Garripoli, Jan-Laurens P. J. van der Steen, Edsger Smits, Gerwin H. Gelinck, Arthur H. M. van Roermund, Eugenio Cantatore. 260-261 [doi]
• 15.4 A 1024-element scalable optical phased array in 0.18µm SOI CMOSSungwon Chung, Hooman Abediasl, Hossein Hashemi. 262-263 [doi]
• 15.5 Cryo-CMOS circuits and systems for scalable quantum computingEdoardo Charbon, Fabio Sebastiano, Masoud Babaie, Andrei Vladimirescu, Mina Shahmohammadi, Robert Bogdan Staszewski, Harald A. R. Homulle, Bishnu Patra, Jeroen P. G. van Dijk, Rosario M. Incandela, Lin Song, Bahador Valizadehpasha. 264-265 [doi]
• 15.6 A 30-to-80MHz simultaneous dual-mode heterodyne oscillator targeting NEMS array gravimetric sensing applications with a 300zg mass resolutionGuillaume Gourlat, Marc Sansa, Patrick Villard, Gilles Sicard, Guillaume Jourdan, Issam Ouerghi, Gérard Billiot, Sebastien Hentz. 266-267 [doi]
• 15.7 Heterogeneous integrated CMOS-graphene sensor array for dopamine detectionBayan Nasri, Ting Wu, Abdullah Alharbi, Mayank Gupta, RamKumar RanjithKumar, Sunit P. Sebastian, Yue Wang, Roozbeh Kiani, Davood Shahrjerdi. 268-269 [doi]
• 2 x-point multi-layer metal nano-dot structureNoriyuki Miura, Shijia Liu, Tsuyoshi Watanabe, Shigeki Imai, Makoto Nagata. 270-271 [doi]
• 15.9 An integrated optical physically unclonable function using process-sensitive sub-wavelength photonic crystals in 65nm CMOSXuyang Lu, Lingyu Hong, Kaushik Sengupta. 272-273 [doi]
• Session 16 overview: Gigahertz data convertersJan Mulder, Paul Ferguson, Un-Ku Moon. 274-275 [doi]
• 16.1 A 13b 4GS/s digitally assisted dynamic 3-stage asynchronous pipelined-SAR ADCBruno Vaz, Adrian Lynam, Bob Verbruggen, Asma Laraba, Conrado Mesadri, Ali Boumaalif, John McGrath, Umanath Kamath, Ronnie De La Torre, Alvin Manlapat, Daire Breathnach, Christophe Erdmann, Brendan Farley. 276-277 [doi]
• 16.2 A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving -161dBFS/Hz NSDHajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson. 278-279 [doi]
• 16.3 A 330mW 14b 6.8GS/s dual-mode RF DAC in 16nm FinFET achieving -70.8dBc ACPR in a 20MHz channel at 5.2GHzChristophe Erdmann, Edward Cullen, Damien Brouard, Roberto Pelliconi, Bob Verbruggen, John McGrath, Diarmuid Collins, Marites De La Torre, Pierrick Gay, Patrick Lynch, Peng Lim, Anthony Collins, Brendan Farley. 280-281 [doi]
• 16.4 A 5mW 7b 2.4GS/s 1-then-2b/cycle SAR ADC with background offset calibrationChi-Hang Chan, Yan Zhu 0001, Iok-Meng Ho, Wai-Hong Zhang, Seng-Pan U, Rui Paulo Martins. 282-283 [doi]
• 16.5 An 8GS/s time-interleaved SAR ADC with unresolved decision detection achieving -58dBFS noise and 4GHz bandwidth in 28nm CMOSJohn P. Keane, Nathaniel J. Guilar, Dusan Stepanovic, Bernd Wuppermann, Charles Wu, Cheongyuen W. Tsang, Robert Neff, Ken Nishimura. 284-285 [doi]
• 16.6 A 10b DC-to-20GHz multiple-return-to-zero DAC with >48dB SFDRLucas Duncan, Brian Dupaix, Jamin J. McCue, Brandon Mathieu, Matthew LaRue, Mesfin Teshome, Myung-Jun Choe, Waleed Khalil. 286-287 [doi]
• 16.7 A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technologySiddharth Devarajan, Larry Singer, Dan Kelly, Steve Kosic, Tao Pan, José B. Silva, Janet Brunsilius, Daniel Rey-Losada, Frank Murden, Carroll Speir, Jeff Bray, Eric Otte, Nevena Rakuljic, Phil Brown, Todd Weigandt, Qicheng Yu, Donald Paterson, Corey Petersen, Jeffrey C. Gealow. 288-289 [doi]
• Session 17 overview: TX and RX building blocksBrian Ginsburg, Payam Heydari, Piet Wambacq. 290-291 [doi]
• 17.1 A digitally assisted CMOS WiFi 802.11ac/11ax front-end module achieving 12% PA efficiency at 20dBm output power with 160MHz 256-QAM OFDM signalYuen-Hui Chee, Fatih Golcuk, Toru Matsuura, Christopher Beale, James F. Wang, Osama Shanaa. 292-293 [doi]
• 17.2 A 28GHz magnetic-free non-reciprocal passive CMOS circulator based on spatio-temporal conductance modulationTolga Dinc, Harish Krishnaswamy. 294-295 [doi]
• 17.3 A 60GHz on-chip linear radiator with single-element 27.9dBm Psat and 33.1dBm peak EIRP using multifeed antenna for direct on-antenna power combiningTaiyun Chi, Fei Wang, Sensen Li, Min-Yu Huang, Jong Seok Park, Hua Wang. 296-297 [doi]
• 17.4 A sub-mW antenna-impedance detection using electrical balance for single-step on-chip tunable matching in wearable/implantable applicationsChuang Lu, Ao Ba, Yao-Hong Liu, Xiaoyan Wang, Christian Bachmann, Kathleen Philips. 298-299 [doi]
• 17.5 An intrinsically linear wideband digital polar PA featuring AM-AM and AM-PM corrections through nonlinear sizing, overdrive-voltage control, and multiphase RF clockingMohsen Hashemi, Yiyu Shen, Mohammadreza Mehrpoo, Mustafa Acar, Rene van Leuken, Morteza S. Alavi, Leonardus de Vreede. 300-301 [doi]
• 17.6 Rapid and energy-efficient molecular sensing using dual mm-Wave combs in 65nm CMOS: A 220-to-320GHz spectrometer with 5.2mW radiated power and 14.6-to-19.5dB noise figureCheng Wang, Ruonan Han. 302-303 [doi]
• 17.7 A packaged 90-to-300GHz transmitter and 115-to-325GHz coherent receiver in CMOS for full-band continuous-wave mm-wave hyperspectral imagingTaiyun Chi, Min-Yu Huang, Sensen Li, Hua Wang. 304-305 [doi]
• 17.8 A compact 130GHz fully packaged point-to-point wireless system with 3D-printed 26dBi lens antenna achieving 12.5Gb/s at 1.55pJ/b/mNemat Dolatsha, Baptiste Grave, Mahmoud Sawaby, Cheng Chen, Afshin Babveyh, Siavash Kananian, Aimeric Bisognin, Cyril Luxey, Frederic Gianesello, Jörge Costa, Carlos Fernandes, Amin Arbabian. 306-307 [doi]
• 17.9 A 105Gb/s 300GHz CMOS transmitterKyoya Takano, Shuhei Amakawa, Kosuke Katayama, Shinsuke Hara, Ruibing Dong, Akifumi Kasamatsu, Iwao Hosako, Koichi Mizuno, Kazuaki Takahashi, Takeshi Yoshida, Minoru Fujishima. 308-309 [doi]
• 17.10 A 318-to-370GHz standing-wave 2D phased array in 0.13µm BiCMOSHossein Jalili, Omeed Momeni. 310-311 [doi]
• Session 18 overview: Full duplex wireless front-endsAlyosha Molnar, Jan Craninckx, Aarno Pärssinen. 312-313 [doi]
• 18.1 A 1.7-to-2.2GHz full-duplex transceiver system with >50dB self-interference cancellation over 42MHz bandwidthTong Zhang, Ali Najafi, Chenxin Su, Jacques C. Rudell. 314-315 [doi]
• 18.2 Highly-linear integrated magnetic-free circulator-receiver for full-duplex wirelessNegar Reiskarimian, Mahmood Baraani Dastjerdi, Jin Zhou, Harish Krishnaswamy. 316-317 [doi]
• 18.3 A single-port duplex RF front-end for X-band single-antenna FMCW radar in 65nm CMOSYu-Hsien Kao, Hao-Chung Chou, Chun-Chieh Peng, Yu-Jiu Wang, Borching Su, Ta-Shun Chu. 318-319 [doi]
• Session 19 overview: Frequency generationAndrea Mazzanti, Xiang Gao, Piet Wambacq. 320-321 [doi]
• 19.1 A fundamental-frequency 114GHz circular-polarized radiating element with 14dBm EIRP, -99.3dBc/Hz phase-noise at 1MHz offset and 3.7% peak efficiencyPeyman Nazari, Saman Jafarlou, Payam Heydari. 322-323 [doi]
• 19.2 A PVT-robust -39dBc 1kHz-to-100MHz integrated-phase-noise 29GHz injection-locked frequency multiplier with a 600µW frequency-tracking loop using the averages of phase deviations for mm-band 5G transceiversSeyeon Yoo, Seojin Choi, Juyeop Kim, Heein Yoon, Yongsun Lee, Jaehyouk Choi. 324-325 [doi]
• 19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitterAhmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh. 326-327 [doi]
• 19.4 A 0.0049mm2 2.3GHz sub-sampling ring-oscillator PLL with time-based loop filter achieving -236.2dB jitter-FOMJeffrey Chuang, Harish Krishnaswamy. 328-329 [doi]
• 19.5 A 2.4GHz RF fractional-N synthesizer with 0.25fREF BWLong Kong, Behzad Razavi. 330-331 [doi]
• 19.6 A 0.2V trifilar-coil DCO with DC-DC converter in 16nm FinFET CMOS with 188dB FOM, 1.3kHz resolution, and frequency pushing of 38MHz/V for energy harvesting applicationsChao-Chieh Li, Min-Shueh Yuan, Chih-Hsien Chang, Yu-Tso Lin, Chia-Chun Liao, Kenny Hsieh, Mark Chen, Robert Bogdan Staszewski. 332-333 [doi]
• Session 20 overview: Digital voltage regulators and low-power techniquesAtsuki Inoue, Dennis Sylvester, Edith Beigné. 334-335 [doi]
• 20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOSHarish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De. 336-337 [doi]
• 20.2 Digital low-dropout regulator with anti PVT-variation technique for dynamic voltage scaling and adaptive voltage scaling multicore processorWen-Jie Tsou, Wen-Hau Yang, Jian-He Lin, Hsin Chen, Ke-Horng Chen, Chin-Long Wey, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai. 338-339 [doi]
• 20.3 A 100nA-to-2mA successive-approximation digital LDO with PD compensation and sub-LSB duty control achieving a 15.1ns response time at 0.5VLoai G. Salem, Julian Warchall, Patrick P. Mercier. 340-341 [doi]
• 20.4 An output-capacitor-free analog-assisted digital low-dropout regulator with tri-loop controlMo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins. 342-343 [doi]
• 20.5 A dual-symmetrical-output switched-capacitor converter with dynamic power cells and minimized cross regulation for application processors in 28nm CMOSJunmin Jiang, Yan Lu, Wing-Hung Ki, Seng-Pan U, Rui Paulo Martins. 344-345 [doi]
• 20.6 A 0.5V-VIN 1.44mA-class event-driven digital LDO with a fully integrated 100pF output capacitorDoyun Kim, Jonghwan Kim, Hyunju Ham, Mingoo Seok. 346-347 [doi]
• 20.7 A 13.8µW binaural dual-microphone digital ANSI S1.11 filter bank for hearing aids with zero-short-circuit-current logic in 65nm CMOSHsi-Shou Wu, Zhengya Zhang, Marios C. Papaefthymiou. 348-349 [doi]
• Session 21 overview: Smart SoCs for innovative applicationsAntoine Dupret, Pui-In Mak, Eugenio Cantatore. 350-351 [doi]
• 21.1 Nanowatt circuit interface to whole-cell bacterial sensorsPhillip M. Nadeau, Mark Mimee, Sean Carim, Timothy K. Lu, Anantha P. Chandrakasan. 352-353 [doi]
• 21.2 A 1.4mΩ-sensitivity 94dB-dynamic-range electrical impedance tomography SoC and 48-channel Hub SoC for 3D lung ventilation monitoring systemMinseo Kim, Hyunki Kim, Jaeeun Jang, Jihee Lee, Jaehyuk Lee, Jiwon Lee, Kyungrog Lee, Kwantae Kim, Yongsu Lee, Hoi-Jun Yoo. 354-355 [doi]
• 3 wireless implantable intraocular pressure monitor microsystemHansraj Bhamra, Jui-Wei Tsai, Yu-Wen Huang, Quan Yuan, Pedro P. Irazoqui. 356-357 [doi]
• 21.4 A reduced-order sliding-mode controller with an auxiliary PLL frequency discriminator for ultrasonic electric scalpelsXiaosen Liu, Adrian I. Colli-Menchi, Edgar Sánchez-Sinencio. 358-359 [doi]
• 21.5 A 3-to-5V input 100Vpp output 57.7mW 0.42% THD+N highly integrated piezoelectric actuator driverSimon Chaput, David M. Brooks, Gu-Yeon Wei. 360-361 [doi]
• 21.6 A 12nW always-on acoustic sensing and object recognition microsystem using frequency-domain feature extraction and SVM classificationSeokhyeon Jeong, Yu Chen, Tae-Kwang Jang, Julius Tsai, David Blaauw, Hun-Seok Kim, Dennis Sylvester. 362-363 [doi]
• 21.7 2pJ/MAC 14b 8×8 linear transform mixed-signal spatial filter in 65nm CMOS with 84dB interference suppressionSiddharth Joshi, Chul Kim, Sohmyung Ha, Yu Mike Chi, Gert Cauwenberghs. 364-365 [doi]
• 21.8 An actively detuned wireless power receiver with public key cryptographic authentication and dynamic power allocationNachiket V. Desai, Chiraag Juvekar, Shubham Chandak, Anantha P. Chandrakasan. 366-367 [doi]
• Session 22 overview: Harvesting and wireless powerStefano Stanzione, Edgar Sánchez-Sinencio, Axel Thomsen. 368-369 [doi]
• 22.1 A self-tuning resonant inductive link transmit driver using quadrature-symmetric phase-switched fractional capacitanceHenry R. H. Kennedy, Rares Bodnar, Teerasak Lee, William Redman-White. 370-371 [doi]
• 2 inductorless fully integrated flipping-capacitor rectifier (FCR) for piezoelectric energy harvesting with 483% power-extraction enhancementZhiyuan Chen 0002, Man Kay Law, Pui-In Mak, Wing-Hung Ki, Rui Paulo Martins. 372-373 [doi]
• 22.3 Adaptive reconfigurable voltage/current-mode power management with self-regulation for extended-range inductive power transmissionHesam Sadeghi Gougheri, Mehdi Kiani. 374-375 [doi]
• 22.4 A reconfigurable bidirectional wireless power transceiver with maximum-current charging mode and 58.6% battery-to-battery efficiencyMo Huang, Yan Lu, Seng-Pan U, Rui Paulo Martins. 376-377 [doi]
• 22.5 A 93%-power-efficiency photovoltaic energy harvester with irradiance-aware auto-reconfigurable MPPT scheme achieving >95% MPPT efficiency across 650µW to 1W and 2.9ms FOCV MPPT transient timeSandip Uprety, Hoi Lee. 378-379 [doi]
• 22.6 A fully integrated counter-flow energy reservoir for 70%-efficient peak-power delivery in ultra-low-power systemsXiao Wu, Kyojin David Choo, Yao Shi, Li-Xuan Chuo, Dennis Sylvester, David Blaauw. 380-381 [doi]
• 22.7 An inductively-coupled wireless power-transfer system that is immune to distance and load variationsJiacheng Pan, Asad A. Abidi, Dejan Rozgic, Hariprasad Chandrakumar, Dejan Markovic. 382-383 [doi]
• 22.8 An AC-input inductorless LED driver for visible-light-communication applications with 8Mb/s data-rate and 6.4% low-frequency flickerYuan Gao, Lisong Li, Philip K. T. Mok. 384-385 [doi]
• Session 23 overview: DRAM, MRAM & DRAM interfacesTakefumi Yoshikawa, Seung-Jun Bae, Leland Chang. 386-387 [doi]
• 23.1 An 8Gb 12Gb/s/pin GDDR5X DRAM for cost-effective high-performance applicationsMartin Brox, Mani Balakrishnan, Martin Broschwitz, Cristian Chetreanu, Stefan Dietrich, Fabien Funfrock, Marcos Alvarez Gonzalez, Thomas Hein, Eugen Huber, Daniel Lauber, Milena Ivanov, Maksim Kuzmenka, Chris Mohr, Francisco Emiliano Munoz, Juan Ocon Garrido, Swetha Padaraju, Sven Piatkowski, Jan Pottgiesser, Peter Pfefferl, Manfred Plan, Jens Polney, Stefan Rau, Michael Richter, Ronny Schneider, Ralf Oliver Seitter, Wolfgang Spirkl, Marc Walter, Jörg Weller, Filippo Vitale. 388-389 [doi]
• 23.2 A 5Gb/s/pin 8Gb LPDDR4X SDRAM with power-isolated LVSTL and split-die architecture with 2-die ZQ calibration schemeChang-Kyo Lee, Yoon-Joo Eom, Jin-Hee Park, Junha Lee, Hye-Ran Kim, Kihan Kim, Young Choi, Ho-Jun Chang, Jonghyuk Kim, Jong-Min Bang, Seungjun Shin, Hanna Park, Su-Jin Park, Young-Ryeol Choi, Hoon Lee, Kyong-Ho Jeon, Jae Young Lee, Hyo-Joo Ahn, Kyoung-Ho Kim, Jung Sik Kim, Soobong Chang, Hyong-Ryol Hwang, Duyeul Kim, Yoon-Hwan Yoon, Seok-Hun Hyun, Joon Young Park, Yoon-Gyu Song, Youn-Sik Park, Hyuck-Joon Kwon, Seung-Jun Bae, Tae-young Oh, Indal Song, Yong-Cheol Bae, Jung Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin. 390-391 [doi]
• 23.3 A 4.8Gb/s/pin 2Gb LPDDR4 SDRAM with sub-100µA self-refresh current for IoT applicationsNohhyup Kwak, Saeng-Hwan Kim, Kyong-Ha Lee, Chang-Ki Baek, Mun Seon Jang, Yongsuk Joo, Seung Hun Lee, Wooyoung Lee, Eunryeong Lee, Donghee Han, Jaeyeol Kang, Jung Ho Lim, Jae-Beom Park, Kyung Tae Kim, Sunki Cho, Sung Woo Han, Jee Yeon Keh, Jun Hyun Chun, Jonghoon Oh, Seok Hee Lee. 392-393 [doi]
• 23.4 An extremely low-standby-power 3.733Gb/s/pin 2Gb LPDDR4 SDRAM for wearable devicesHye-Jung Kwon, Eunsung Seo, Changyong Lee, Young Hun Seo, Gong-Heum Han, Hye-Ran Kim, Jong-Ho Lee, Min-Su Jang, Sung-Geun Do, Seung Hyun Cho, Jae-Koo Park, Su-Yeon Doo, Jung-Bum Shin, Sang-Hoon Jung, Hyoung-Ju Kim, In-Ho Im, Beob-Rae Cho, Jae Woong Lee, Jae-Youl Lee, Ki-Hun Yu, Hyung Kyu Kim, Chul-Hee Jeon, Hyun Soo Park, Sang-Sun Kim, Seok Ho Lee, Jong-Wook Park, Seung-Sub Lee, Bo-Tak Lim, Jun-Young Park, Yoon-Sik Park, Hyuk-jun Kwon, Seung-Jun Bae, Jung Hwan Choi, Kwang-Il Park, Seong-Jin Jang, Gyo-Young Jin. 394-395 [doi]
• 23.5 A 4Gb LPDDR2 STT-MRAM with compact 9F2 1T1MTJ cell and hierarchical bitline architectureKwangMyoung Rho, Kenji Tsuchida, Dongkeun Kim, Yutaka Shirai, Jihyae Bae, Tsuneo Inaba, Hiromi Noro, Hyunin Moon, Sungwoong Chung, Kazumasa Sunouchi, Jinwon Park, Kiseon Park, Akihito Yamamoto, Seoungju Chung, Hyeongon Kim, Hisato Oyamatsu, Jonghoon Oh. 396-397 [doi]
• 23.6 A 0.6V 4.266Gb/s/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controllerSoo-Min Lee, Jihun Oh, Jinho Choi, Seokkyun Ko, Daero Kim, Kyounghoi Koo, JongRyun Choi, Yoonjee Nam, Sangsoo Park, Hyungkweon Lee, Eunsu Kim, Sukhyun Jung, Kwanyeob Chae, SuHo Kim, Sanghune Park, Sanghyun Lee, Sungho Park. 398-399 [doi]
• 23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOSIl-Min Yi, Min-Kyun Chae, Seok-Hun Hyun, Seung-Jun Bae, Jung Hwan Choi, Seong-Jin Jang, Byungsub Kim, Jae-Yoon Sim, Hong June Park. 400-401 [doi]
• 23.8 A 1V 7.8mW 15.6Gb/s C-PHY transceiver using tri-level signaling for post-LPDDR4Woojun Choi, Taewoong Kim, Jongjoo Shim, Hyungsoo Kim, Gunhee Han, Youngcheol Chae. 402-403 [doi]
• 23.9 An 8-channel 4.5Gb 180GB/s 18ns-row-latency RAM for the last level cacheTah-Kang Joseph Ting, Gyh-Bin Wang, Ming-Hung Wang, Chun-Peng Wu, Chun-Kai Wang, Chun-Wei Lo, Li-Chin Tien, Der-Min Yuan, Yung-Ching Hsieh, Jenn-Shiang Lai, Wen-Pin Hsu, Chien-Chih Huang, Chi-Kang Chen, Yung-Fa Chou, Ding-Ming Kwai, Zhe Wang, Wei Wu, Shigeki Tomishima, Patrick Stolt, Shih-Lien Lu. 404-405 [doi]
• Session 24 overview: Wireless receivers and synthesizersChun-Huat Heng, Ken Yamamoto, Aarno Pärssinen. 406-407 [doi]
• 2 DCO-based phase-tracking RX featuring direct demodulation and data-aided carrier tracking for IoT applicationsYao-Hong Liu, Vijaya Kumar Purushothaman, Chuang Lu, Johan Dijkhuis, Robert Bogdan Staszewski, Christian Bachmann, Kathleen Philips. 408-409 [doi]
• 24.2 A 0.1-to-3.1GHz 4-element MIMO receiver array supporting analog/RF arbitrary spatial filteringLinxiao Zhang, Harish Krishnaswamy. 410-411 [doi]
• 24.3 A high-linearity CMOS receiver achieving +44dBm IIP3 and +13dBm B1dB for SAW-less LTE radioYuanching Lien, Eric A. M. Klumperink, Bernard Tenbroek, Jon Strange, Bram Nauta. 412-413 [doi]
• 24.4 A 0.18V 382µW bluetooth low-energy (BLE) receiver with 1.33nW sleep power for energy-harvesting applications in 28nm CMOSWei-Han Yu, Haidong Yi, Pui-In Mak, Jun Yin, Rui Paulo Martins. 414-415 [doi]
• 24.5 A 4.5nW wake-up radio with -69dBm sensitivityHaowei Jiang, Po-Han Peter Wang, Li Gao, Pinar Sen, Young Han Kim, Gabriel M. Rebeiz, Drew A. Hall, Patrick P. Mercier. 416-417 [doi]
• 24.6 A time-interleaved filtering-by-aliasing receiver front-end with >70dB suppression at <4× bandwidth frequency offsetSameed Hameed, Sudhakar Pamarti. 418-419 [doi]
• 24.7 A 673µW 1.8-to-2.5GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applicationsYuming He, Yao-Hong Liu, Takashi Kuramochi, Johan H. C. van den Heuvel, Benjamin Busze, Nereo Markulic, Christian Bachmann, Kathleen Philips. 420-421 [doi]
• 24.8 A 14nm fractional-N digital PLL with 0.14psrms jitter and -78dBc fractional spur for cellular RFICsChih-Wei Yao, Wing-Fai Loke, Ronghua Ni, Yongping Han, Haoyang Li, Kunal Godbole, Yongrong Zuo, Sangsoo Ko, Nam-Seog Kim, Sangwook Han, Ikkyun Jo, Joonhee Lee, Juyoung Han, Daehyeon Kwon, Chulho Kim, Shinwoong Kim, Sang-Won Son, Thomas Byunghak Cho. 422-423 [doi]
• 24.9 A 128-QAM 60GHz CMOS transceiver for IEEE802.11ay with calibration of LO feedthrough and I/Q imbalanceJian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa. 424-425 [doi]
• Session 25 overview: GaN drivers and galvanic isolatorsShuichi Nagai, Yogesh E. Ramadass, Eugenio Cantatore. 426-427 [doi]
• 25.1 A 50.7% peak efficiency subharmonic resonant isolated capacitive power transfer system with 62mW output power for low-power industrial sensor interfacesLei Chen, Joseph Sankman, Rajarshi Mukhopadhyay, Mark Morgan, D. Brian Ma. 428-429 [doi]
• 25.2 A 10MHz 3-to-40V VIN tri-slope gate driving GaN DC-DC converter with 40.5dBµV spurious noise compression and 79.3% ringing suppression for automotive applicationsXugang Ke, Joseph Sankman, Yingping Chen, Lenian He, D. Brian Ma. 430-431 [doi]
• 25.3 A 1.3A gate driver for GaN with fully integrated gate charge buffer capacitor delivering 11nC enabled by high-voltage energy storingAchim Seidel, Bernhard Wicht. 432-433 [doi]
• 25.4 A 500Mb/s 200pJ/b die-to-die bidirectional link with 24kV surge isolation and 50kV/µs CMR using resonant inductive coupling in 0.18µm CMOSSubhashish Mukherjee, Anoop Narayan Bhat, Kumar Anurag Shrivastava, Madhulatha Bonu, Benjamin Sutton, Venugopal Gopinathan, Ganesan Thiagarajan, Abhijit Patki, Jhankar Malakar, Nagendra Krishnapura. 434-435 [doi]
• Session 26 overview: Processor-power management and clockingKathy Wilcox, Youngmin Shin, Edith Beigné. 436-437 [doi]
• 26.2 Power supply noise in a 22nm z13™ microprocessorPierce I-Jen Chuang, Christos Vezyrtzis, Divya Pathak, Richard F. Rizzolo, Tobias Webel, Thomas Strach, Otto A. Torreiter, Preetham Lobo, Alper Buyuktosunoglu, Ramon Bertran, Michael S. Floyd, Malcolm S. Ware, Gerard Salem, Sean M. Carey, Phillip Restle. 438-439 [doi]
• 26.3 Reconfigurable clock networks for random skew mitigation from subthreshold to nominal voltageLongyang Lin, Saurabh Jain, Massimo Alioto. 440-441 [doi]
• 26.4 A 0.4-to-1V 1MHz-to-2GHz switched-capacitor adiabatic clock driver achieving 55.6% clock power reductionLoai G. Salem, Patrick P. Mercier. 442-443 [doi]
• 26.5 Adaptive clocking in the POWER9™ processor for voltage droop protectionMichael S. Floyd, Phillip J. Restle, Michael A. Sperling, Pawel Owczarczyk, Eric J. Fluhr, Joshua Friedrich, Paul Muench, Timothy Diemoz, Pierce Chuang, Christos Vezyrtzis. 444-445 [doi]
• Session 27 overview: Biomedical circuitsGert Cauwenberghs, Michiel Pertijs, Makoto Ikeda. 446-447 [doi]
• 27.1 A 2.8µW 80mVpp-linear-input-range 1.6GΩ-input impedance bio-signal chopper amplifier tolerant to common-mode interference up to 650mVppHariprasad Chandrakumar, Dejan Markovic. 448-449 [doi]
• 27.2 A 25.2mW EEG-NIRS multimodal SoC for accurate anesthesia depth monitoringUnsoo Ha, Jaehyuk Lee, Jihee Lee, Kwantae Kim, Minseo Kim, Taehwan Roh, Sangsik Choi, Hoi-Jun Yoo. 450-451 [doi]
• 2/ch closed-loop neurostimulator with rail-to-rail DC offset removalHossein Kassiri, Reza Pazhouhandeh, Nima Soltani, Muhammad Tariqus Salam, Peter L. Carlen, José Luis Pérez Velazquez, Roman Genov. 452-453 [doi]
• 27.4 A sub-1dB NF dual-channel on-coil CMOS receiver for Magnetic Resonance ImagingBenjamin Sporrer, Lianbo Wu, Luca Bettini, Christian Vogt, Jonas Reber, Josip Marjanovic, Thomas Burger, David O. Brunner, Klaas Paul Pruessmann, Gerhard Tröster, Qiuting Huang. 454-455 [doi]
• 27.5 A pixel-pitch-matched ultrasound receiver for 3D photoacoustic imaging with integrated delta-sigma beamformer in 28nm UTBB FDSOIMan-Chia Chen, Aldo Pena-Perez, Sri-Rajasekhar Kothapalli, Philippe Cathelin, Andreia Cathelin, Sanjiv Sam Gambhir, Boris Murmann. 456-457 [doi]
• 27.6 Single-chip 3072ch 2D array IC with RX analog and all-digital TX beamformer for 3D ultrasound imagingYusaku Katsube, Shinya Kajiyama, Takuma Nishimoto, Tatsuo Nakagawa, Yasuyuki Okuma, Yohei Nakamura, Takahide Terada, Yutaka Igarashi, Taizo Yamawaki, Toru Yazaki, Yoshihiro Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka. 458-459 [doi]
• -4 BER at 8.5cm depthTing-Chia Chang, Max L. Wang, Jayant Charthad, Marcus J. Weber, Amin Arbabian. 460-461 [doi]
• 27.8 Fully integrated optical spectrometer with 500-to-830nm range in 65nm CMOSLingyu Hong, Kaushik Sengupta. 462-463 [doi]
• Session 28 overview: Hybrid ADCsTai-Cheng Lee, Bob Verbruggen, Un-Ku Moon. 464-465 [doi]
• 28.1 A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filterChun-Cheng Liu, Mu-Chen Huang. 466-467 [doi]
• 28.2 An 11.4mW 80.4dB-SNDR 15MHz-BW CT delta-sigma modulator using 6b double-noise-shaped quantizerTaewook Kim, Changsok Han, Nima Maghari. 468-469 [doi]
• 28.3 A 125MHz-BW 71.9dB-SNDR VCO-based CT ΔΣ ADC with segmented phase-domain ELD compensation in 16nm CMOSSheng-Jui Huang, Nathan Egan, Divya Kesharwani, Frank Opteynde, Michael Ashburn. 470-471 [doi]
• 28.4 A 12b 330MS/s pipelined-SAR ADC with PVT-stabilized dynamic amplifier achieving <1dB SNDR variationHai Huang, Sudipta Sarkar, Brian Elies, Yun Chiu. 472-473 [doi]
• 28.5 A 10b 1.5GS/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14nm CMOS FinFETLukas Kull, Danny Luu, Christian Menolfi, Matthias Braendli, Pier Andrea Francese, Thomas Morf, Marcel A. Kossel, Hazar Yueksel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl. 474-475 [doi]
• 28.6 A 78.5dB-SNDR radiation- and metastability-tolerant two-step split SAR ADC operating up to 75MS/s with 24.9mW power consumption in 65nm CMOSHongda Xu, Yongda Cai, Ling Du, Yuan Zhou, Benwei Xu, Datao Gong, Jingbo Ye, Yun Chiu. 476-477 [doi]
• 28.7 A 0.7V 12b 160MS/s 12.8fJ/conv-step pipelined-SAR ADC in 28nm CMOS with digital amplifier techniqueKentaro Yoshioka, Tomohiko Sugimoto, Naoya Waki, SinNyoung Kim, Daisuke Kurose, Hirotomo Ishii, Masanori Furuta, Akihide Sai, Tetsuro Itakura. 478-479 [doi]
• Session 29 overview: Optical- and electrical-link innovationsSamuel Palermo, Hideyuki Nosaka, Frank O'Mahony. 480-481 [doi]
• 29.1 A 64Gb/s 1.4pJ/b NRZ optical-receiver data-path in 14nm CMOS FinFETAlessandro Cevrero, Ilter Özkaya, Pier Andrea Francese, Christian Menolfi, Thomas Morf, Matthias Braendli, Daniel M. Kuchta, Lukas Kull, Jonathan Proesel, Marcel A. Kossel, Danny Luu, Benjamin G. Lee, Fuad E. Doany, Mounir Meghelli, Yusuf Leblebici, Thomas Toifl. 482-483 [doi]
• 29.2 A transmitter and receiver for 100Gb/s coherent networks with integrated 4×64GS/s 8b ADCs and DACs in 20nm CMOSJun Cao, Delong Cui, Ali Nazemi, Tim He, Guansheng Li, Burak Çatli, Mehdi Khanpour, Kangmin Hu, Tamer A. Ali, Heng Zhang, Hairong Yu, Ben Rhew, Shiwei Sheng, Yonghyun Shim, Bo Zhang, Afshin Momtaz. 484-485 [doi]
• 29.3 A 40Gb/s PAM-4 transmitter based on a ring-resonator optical DAC in 45nm SOI CMOSSajjad Moazeni, Sen Lin, Mark T. Wade, Luca Alloatti, Rajeev J. Ram, Milos A. Popovic, Vladimir Stojanovic. 486-487 [doi]
• 29.4 A 16Gb/s 3.6pJ/b wireline transceiver with phase domain equalization scheme: Integrated pulse width modulation (iPWM) in 65nm CMOSAshwin Ramachandran, Arun Natarajan, Tejasvi Anand. 488-489 [doi]
• 29.5 12Gb/s over four balanced lines utilizing NRZ braid clock signaling with 100% data payload and spread transition scheme for 8K UHD intra-panel interfacesYeonho Lee, Yoonjae Choi, Sang-Geun Bae, Jaehun Jun, Junyoung Song, Sewook Hwang, Chulwoo Kim. 490-491 [doi]
• 29.6 A 3-to-10Gb/s 5.75pJ/b transceiver with flexible clocking in 65nm CMOSRomesh Kumar Nandwana, Saurabh Saxena, Ahmed Elkholy, Mrunmay Talegaonkar, Junheng Zhu, Woo-seok Choi, Ahmed Elmallah, Pavan Kumar Hanumolu. 492-493 [doi]
• 29.7 A 2.5GHz injection-locked ADPLL with 197fsrms integrated jitter and -65dBc reference spur using time-division dual calibrationSungWoo Kim, Han-Gon Ko, Sung-Yong Cho, Jinhyung Lee, Soyeong Shin, Min-Seong Choo, Hankyu Chi, Deog Kyoon Jeong. 494-495 [doi]
• TutorialsAli Sheikholeslami. 498-499 [doi]
• F1: Integrated voltage regulators for SoC and emerging IoT systemsMakoto Takamiya, Yogesh K. Ramadass, Keith Bowman, Gerard Villar Pique, Shuichi Nagai, Dennis Sylvester. 500-502 [doi]
• F2: High-performance frequency generation for wireless and wireline systemsJiayoon Ru, Kohei Onizuka, Pavan Hanumolu, Roberto Nonis, Howard Luong, Jan Craninckx. 503-505 [doi]
• F3: Beyond the horizon of conventional computing: From deep learning to neuromorphic systemsMeng-Fan Chang, Jun Deguchi, Vivek De, Masato Motomura, Shinichiro Shiratake, Marian Verhelst. 506-508 [doi]
• F4: Wireless low-power transceivers for local and wide-area networksJan van Sinderen, Danielle Griffith, Ken Yamamoto, Antonio Liscidini, Young-sub Yuk. 509-511 [doi]
• F5: Wireline transceivers for Mega Data Centers: 50Gb/s and beyondYohan Frans, Ichiro Fujimori, Seung-Jun Bae, Samuel Palermo, Hideyuki Nosaka, Simone Erba. 512-514 [doi]
• F6: Pushing the performance limit in data converters organizers: Venkatesh Srinivasan, Texas Instruments, Dallas, TXKostas Doris, David Robertson, Seung-Tak Ryu, U. Seng-Pan. 515-517 [doi]
• EE1: Student Research PreviewSeongHwan Cho, Denis Daly. 518-520 [doi]
• EE2: Intelligent machines: Will the technological singularity happen?Stefano Pellerano, Sungdae Choi, Jan Rabaey. 521 [doi]
• EE3: Quantum engineering: Hype, spin or reality?Edoardo Charbon. 522 [doi]
• EE4: Semiconductor economics: How business decisions are engineeredIchiro Fujimori, Pavan Hanumolu, Ichiro Fujimori. 523 [doi]
• EE5: When will we stop driving our cars?Martin Brox, Jonathan Chang, Howard Luong, Paul Liang, Riccardo Mariani. 524 [doi]
• EE6: Return of survey says!Harry Lee, Matt Straayer, Chris Mangelsdorf. 525 [doi]
• Ultra-low-power analog designDaniel Friedman. 526-527 [doi]