Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh. 19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. pages 326-327, IEEE, 2017. [doi]
Abstract is missing.