Ahmed I. Hussein, Sriharsha Vasadi, Mazen Soliman, Jeyanandh Paramesh. 19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. pages 326-327, IEEE, 2017. [doi]
@inproceedings{HusseinVSP17,
title = {19.3 A 50-to-66GHz 65nm CMOS all-digital fractional-N PLL with 220fsrms jitter},
author = {Ahmed I. Hussein and Sriharsha Vasadi and Mazen Soliman and Jeyanandh Paramesh},
year = {2017},
doi = {10.1109/ISSCC.2017.7870393},
url = {http://dx.doi.org/10.1109/ISSCC.2017.7870393},
researchr = {https://researchr.org/publication/HusseinVSP17},
cites = {0},
citedby = {0},
pages = {326-327},
booktitle = {2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017},
publisher = {IEEE},
isbn = {978-1-5090-3758-2},
}