Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi. 6.7 A 28Gb/s digital CDR with adaptive loop gain for optimum jitter tolerance. In 2017 IEEE International Solid-State Circuits Conference, ISSCC 2017, San Francisco, CA, USA, February 5-9, 2017. pages 122-123, IEEE, 2017. [doi]
Abstract is missing.