Chul-Hong Park - researchr alias

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Viewing Publication 1 - 17 from 17

2024

PROBE3.0: A Systematic Framework for Design-Technology Pathfinding With Improved Design EnablementSuhyeong Choi, Jinwook Jung, Andrew B. Kahng, Minsoo Kim, Chul-Hong Park, Bodhisatta Pramanik, Dooseok Yoon. tcad, 43(4):1218-1231, April 2024. [doi]

2017

2014

Interface test of local control center simulator for validation of improved train control system using on-board controlChul-Hong Park, Jong-Hyen Baek, Doh Chul Yang. ictc 2014: 577-578 [doi]

2011

Exploration of VLSI CAD researches for early design rule evaluationChul-Hong Park, David Z. Pan, Kevin Lucas. aspdac 2011: 405-406 [doi]

2010

2009

Lens aberration aware placement for timing yieldAndrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang. todaes, 14(1), 2009. [doi]

2008

2007

Detailed Placement for Enhanced Control of Resist and Etch CDsPuneet Gupta, Andrew B. Kahng, Chul-Hong Park. tcad, 26(12):2144-2157, 2007. [doi]

2006

Wafer Topography-Aware Optical Proximity CorrectionPuneet Gupta, Andrew B. Kahng, Chul-Hong Park, Kambiz Samadi, Xu Xu. tcad, 25(12):2747-2756, 2006. [doi]

Lens aberration aware timing-driven placementAndrew B. Kahng, Chul-Hong Park, Puneet Sharma, Qinke Wang. date 2006: 890-895 [doi]

2005

Detailed placement for improved depth of focus and CD controlPuneet Gupta, Andrew B. Kahng, Chul-Hong Park. aspdac 2005: 343-348 [doi]

2002

A Hybrid PPC Method Based on the Empirical Etch Model for the 0.14µm DRAM Generation and BeyondChul-Hong Park, Soo-Han Choi, Sang-Uhk Rhie, Dong-hyun Kim, Jun-Seong Park, Tae-Hwang Jang, Ji-Soong Park, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong. isqed 2002: 143-147 [doi]

2000

An Efficient Rule-Based OPC Approach Using a DRC Tool for 0.18mum ASICJi-Soong Park, Chul-Hong Park, Sang-Uhk Rhie, Yoo-Hyon Kim, Moon-Hyun Yoo, Jeong-Taek Kong, Hyung-Woo Kim, Sun-Il Yoo. isqed 2000: 81-86 [doi]

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