Table of Contents

• CAD for displays!Mary Lou Jepsen. 1 [doi]
• Network flow-based power optimization under timing constraints in MSV-driven floorplanningQiang Ma, Evangeline F. Y. Young. 1-8 [doi]
• What can brain researchers learn from computer engineers and vice versa?Dmitri Mitya Chklovskii. 2 [doi]
• Reliable system design: models, metrics and design techniquesSubhasish Mitra, Ravishankar K. Iyer, Kishor S. Trivedi, James W. Tschanz. 3 [doi]
• Architecting parallel programsJoel Phillips, Kurt Keutzer, Michael Wrinn. 4 [doi]
• Embedded software verification: challenges and solutionsMalay K. Ganai, Chao Wang, Shuvendu K. Lahiri, Daniel Kroening. 5 [doi]
• Nanolithography and CAD challenges for 32nm/22nm and beyondDavid Z. Pan, Stephen Renwick, Vivek Singh, Judy Huckabay. 6 [doi]
• Challenges at 45nm and beyondDan Bailey, Eric Soenen, Puneet Gupta, Paul G. Villarrubia, Sang H. Dhong. 7 [doi]
• Mixed-signal simulation challenges and solutionsHenry Chang, William Walker, John G. Maneatis, John F. Croix. 8 [doi]
• More Moore: foolish, feasible, or fundamentally different?Rob Aitken, Jerry Bautista, Wojciech Maly, Jan M. Rabaey. 9 [doi]
• Linear constraint graph for floorplan optimization with soft blocksJia Wang, Hai Zhou. 9-15 [doi]
• A novel fixed-outline floorplanner with zero deadspace for hierarchical designOu He, Sheqin Dong, Jinian Bian, Satoshi Goto, Chung-Kuan Cheng. 16-23 [doi]
• Synthesis from multi-cycle atomic actions as a solution to the timing closure problemMichal Karczmarek, Arvind. 24-31 [doi]
• To SAT or not to SAT: Ashenhurst decomposition in a large scaleHsuan-Po Lin, Jie-Hong Roland Jiang, Ruei-Rung Lee. 32-37 [doi]
• Boolean factoring and decomposition of logic networksAlan Mishchenko, Robert K. Brayton, Satrajit Chatterjee. 38-44 [doi]
• On the numbers of variables to represent sparse logic functionsTsutomu Sasao. 45-51 [doi]
• Effective IR-drop reduction in at-speed scan testing using Distribution-Controlling X-IdentificationKohei Miyase, Kenji Noda, Hideaki Ito, Kazumi Hatayama, Takashi Aikyo, Yuta Yamato, Hiroshi Furukawa, Xiaoqing Wen, Seiji Kajihara. 52-58 [doi]
• Temperature-aware test scheduling for multiprocessor systems-on-chipDavid R. Bild, Sanchit Misra, Thidapat Chantem, Prabhat Kumar, Robert P. Dick, Xiaobo Sharon Hu, Li Shang, Alok N. Choudhary. 59-66 [doi]
• On capture power-aware test data compression for scan-based testingJia Li, Xiao Liu, Yubin Zhang, Yu Hu, Xiaowei Li, Qiang Xu. 67-72 [doi]
• MAPS: multi-algorithm parallel circuit simulationXiaoji Ye, Wei Dong, Peng Li, Sani R. Nassif. 73-78 [doi]
• Yield-aware hierarchical optimization of large analog integrated circuitsGuo Yu, Peng Li. 79-84 [doi]
• Model reduction via projection onto nonlinear manifolds, with applications to analog circuits and biochemical systemsChenjie Gu, Jaijeet S. Roychowdhury. 85-92 [doi]
• Algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closureHuan Ren, Shantanu Dutt. 93-100 [doi]
• Delay-optimal simultaneous technology mapping and placement with applications to timing optimizationYifang Liu, Rupesh S. Shelar, Jiang Hu. 101-106 [doi]
• PaRS: fast and near-optimal grid-based cell sizing for library-based designTai-Hsuan Wu, Azadeh Davoodi. 107-111 [doi]
• A polynomial time approximation scheme for timing constrained minimum cost layer assignmentShiyan Hu, Zhuo Li, Charles J. Alpert. 112-115 [doi]
• On the decreasing significance of large standard cells in technology mappingJae-sun Seo, Igor L. Markov, Dennis Sylvester, David Blaauw. 116-121 [doi]
• Verification of arithmetic datapaths using polynomial function models and congruence solvingNeal Tew, Priyank Kalla, Namrata Shekhar, Sivaram Gopalakrishnan. 122-128 [doi]
• Automated abstraction by incremental refinement in interpolant-based model checkingGianpiero Cabodi, Paolo Camurati, Marco Murciano. 129-136 [doi]
• A succinct memory model for automated design debuggingBrian Keng, Hratch Mangassarian, Andreas G. Veneris. 137-142 [doi]
• The analysis of cyclic circuits with Boolean satisfiabilityJohn Backes, Brian Fett, Marc D. Riedel. 143-148 [doi]
• System-level power estimation using an on-chip bus performance monitoring unitYoungjin Cho, Younghyun Kim, Sangyoung Park, Naehyuck Chang. 149-154 [doi]
• Minimizing the energy cost of throughput in a linear pipeline by opportunistic time borrowingMohammad Ghasemazar, Massoud Pedram. 155-160 [doi]
• Accurate energy breakeven time estimation for run-time power gatingHao Xu, Wen-Ben Jone, Ranga Vemuri. 161-168 [doi]
• Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuitsYongho Lee, Deog Kyoon Jeong, Taewhan Kim. 169-172 [doi]
• Efficient block-based parameterized timing analysis covering all potentially critical pathsKhaled R. Heloue, Sari Onaissi, Farid N. Najm. 173-180 [doi]
• Adjustment-based modeling for statistical static timing analysis with high dimension of variabilityLin Xie, Azadeh Davoodi, Jun Zhang, Tai-Hsuan Wu. 181-184 [doi]
• Post-silicon timing characterization by compressed sensingFarinaz Koushanfar, Petros Boufounos, Davood Shamsi. 185-189 [doi]
• Practical, fast Monte Carlo statistical static timing analysis: why and howAmith Singhee, Sonia Singhal, Rob A. Rutenbar. 190-195 [doi]
• On efficient Monte Carlo-based statistical static timing analysis of digital circuitsJavid Jaffari, Mohab Anis. 196-203 [doi]
• Pyramids: an efficient computational geometry-based approach for timing-driven placementTao Luo, David A. Papa, Zhuo Li, Chin-Ngai Sze, Charles J. Alpert, David Z. Pan. 204-211 [doi]
• Guiding global placement with wire densityKalliopi Tsota, Cheng-Kok Koh, Venkataramanan Balakrishnan. 212-217 [doi]
• Constraint graph-based macro placement for modern mixed-size circuit designsHsin-Chen Chen, Yi-Lin Chuang, Yao-Wen Chang, Yung-Chung Chang. 218-223 [doi]
• Pulse width allocation with clock skew scheduling for optimizing pulsed latch-based sequential circuitsHyein Lee, Seungwhun Paik, Youngsoo Shin. 224-229 [doi]
• A novel sequential circuit optimization with clock gating logicYu-Min Kuo, Shih-Hung Weng, Shih-Chieh Chang. 230-233 [doi]
• Scalable and scalably-verifiable sequential synthesisAlan Mishchenko, Michael L. Case, Robert K. Brayton, Stephen Jang. 234-241 [doi]
• System-level thermal aware design of applications with uncertain execution timeSushu Zhang, Karam S. Chatha. 242-249 [doi]
• Proactive temperature balancing for low cost thermal management in MPSoCsAyse Kivilcim Coskun, Tajana Simunic Rosing, Kenny C. Gross. 250-257 [doi]
• A framework for predictive dynamic temperature management of microprocessor systemsOmer Khan, Sandip Kundu. 258-263 [doi]
• A voltage-frequency island aware energy optimization framework for networks-on-chipWooyoung Jang, Duo Ding, David Z. Pan. 264-269 [doi]
• Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit designHamed F. Dadgour, Vivek De, Kaustav Banerjee. 270-277 [doi]
• Large-scale atomistic approach to random-dopant-induced characteristic variability in nanoscale CMOS digital and high-frequency integrated circuitsYiming Li, Chih-Hong Hwang, Ta-Ching Yeh, Tien-Yeh Li. 278-285 [doi]
• A new method to improve accuracy of leakage current estimation for transistors with non-rectangular gates due to sub-wavelength lithography effectsKuen-Yu Tsai, Meng-Fu You, Yi-Chang Lu, Philip C. W. Ng. 286-291 [doi]
• Linear analysis of random process variabilityVictoria Wang, Dejan Markovic. 292-296 [doi]
• Design and optimization of a digital microfluidic biochip for protein crystallizationTao Xu, Krishnendu Chakrabarty, Vamsee K. Pamula. 297-301 [doi]
• Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reductionHushrav Mogal, Kia Bazargan. 302-305 [doi]
• Deterministic analog circuit placement using hierarchically bounded enumeration and enhanced shape functionsMartin Strasser, Michael Eick, Helmut Gräb, Ulf Schlichtmann, Frank M. Johannes. 306-313 [doi]
• Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link exampleRanko Sredojevic, Vladimir Stojanovic. 314-321 [doi]
• Breaking the simulation barrier: SRAM evaluation through norm minimizationLara Dolecek, Masood Qazi, Devavrat Shah, Anantha Chandrakasan. 322-329 [doi]
• Power supply noise aware workload assignment for multi-core systemsAida Todri, Malgorzata Marek-Sadowska, Joseph N. Kozhaya. 330-337 [doi]
• NTHU-Route 2.0: a fast and stable global routerYen-Jung Chang, Yu-Ting Lee, Ting-Chi Wang. 338-343 [doi]
• FastRoute3.0: a fast and high quality global router based on virtual capacityYanheng Zhang, Yue Xu, Chris Chu. 344-349 [doi]
• Multi-layer global routing considering via and wire capacitiesChin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang. 350-355 [doi]
• Race analysis for SystemC using model checkingNicolas Blanc, Daniel Kroening. 356-363 [doi]
• MC-Sim: an efficient simulation tool for MPSoC designsJason Cong, Karthik Gururaj, Guoling Han, Adam Kaplan, Mishali Naik, Glenn Reinman. 364-371 [doi]
• Verifying external interrupts of embedded microprocessor in SoC with on-chip busFu-Ching Yang, Jing-Kun Zhong, Ing-Jer Huang. 372-377 [doi]
• SRAM dynamic stability: theory, variability and analysisWei Dong, Peng Li, Garng M. Huang. 378-385 [doi]
• Impulse sensitivity function analysis of periodic circuitsJaeha Kim, Brian S. Leibowitz, Metha Jeeradit. 386-391 [doi]
• Automated extraction of expert knowledge in analog topology selection and sizingTrent McConaghy, Pieter Palmers, Georges G. E. Gielen, Michiel Steyaert. 392-395 [doi]
• Importance sampled circuit learning ensembles for robust analog IC designPeng Gao, Trent McConaghy, Georges G. E. Gielen. 396-399 [doi]
• Physical models for electron transport in graphene nanoribbons and their junctionsAzad Naeemi, James D. Meindl. 400-405 [doi]
• Characterization and modeling of graphene field-effect devicesKenneth L. Shepard, I. Meric, P. Kim. 406-411 [doi]
• Graphene nanoribbon FETs: technology exploration and CADKartik Mohanram, Jing Guo. 412-415 [doi]
• Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimizationYesin Ryu, Taewhan Kim. 416-419 [doi]
• Decoupling capacitance allocation for timing with statistical noise model and timing analysisTakashi Enami, Masanori Hashimoto, Takashi Sato. 420-425 [doi]
• Transition-aware decoupling-capacitor allocation in power noise reductionPo-Yuan Chen, Che-Yu Liu, TingTing Hwang. 426-429 [doi]
• Placement based multiplier rewiring for cell-based designsFan Mo, Robert K. Brayton. 430-433 [doi]
• Correct-by-construction microarchitectural pipeliningTimothy Kam, Michael Kishinevsky, Jordi Cortadella, Marc Galceran Oms. 434-441 [doi]
• Performance optimization of elastic systems using buffer resizing and buffer insertionDmitry Bufistov, Jorge Júlvez, Jordi Cortadella. 442-448 [doi]
• Performance estimation and slack matching for pipelined asynchronous architectures with choiceGennette Gill, Vishal Gupta, Montek Singh. 449-456 [doi]
• Diastolic arrays: throughput-driven reconfigurable computingMyong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas. 457-464 [doi]
• Layout decomposition for double patterning lithographyAndrew B. Kahng, Chul-Hong Park, Xu Xu, Hailong Yao. 465-472 [doi]
• Electrically driven optical proximity correction based on linear programmingShayak Banerjee, Praveen Elakkumanan, Lars Liebmann, Michael Orshansky. 473-479 [doi]
• A highly efficient optimization algorithm for pixel manipulation in inverse lithography techniqueJinyu Zhang, Wei Xiong, Yan Wang, Zhiping Yu, Min-Chun Tsai. 480-487 [doi]
• Overlay aware interconnect and timing variation modeling for double patterning technologyJae-Seok Yang, David Z. Pan. 488-493 [doi]
• Exact basic geometric operations on arbitrary angle polygons using only fixed size integer coordinatesAlexey Lvov, Ulrich Finkler. 494-498 [doi]
• BSG-Route: a length-matching router for general topologyTan Yan, Martin D. F. Wong. 499-505 [doi]
• Double patterning technology friendly detailed routingMinsik Cho, Yongchan Ban, David Z. Pan. 506-511 [doi]
• Routing for chip-package-board co-design considering differential pairsJia-Wei Fang, Kuan-Hsien Ho, Yao-Wen Chang. 512-517 [doi]
• Area-I/O flip-chip routing for chip-package co-designJia-Wei Fang, Yao-Wen Chang. 518-522 [doi]
• Obstacle-avoiding rectilinear Steiner tree constructionLiang Li, Evangeline F. Y. Young. 523-528 [doi]
• Evaluation of voltage interpolation to address process variationsKevin Brownell, Gu-Yeon Wei, David Brooks. 529-536 [doi]
• Efficient online computation of core speeds to maximize the throughput of thermally constrained multi-core processorsRavishankar Rao, Sarma B. K. Vrudhula. 537-542 [doi]
• ROAdNoC: runtime observability for an adaptive network on chip architectureMohammad Abdullah Al Faruque, Thomas Ebi, Jörg Henkel. 543-548 [doi]
• FBT: filled buffer technique to reduce code size for VLIW processorsTalal Bonny, Jörg Henkel. 549-554 [doi]
• Advancing supercomputer performance through interconnection topology synthesisYi Zhu, Michael Taylor, Scott B. Baden, Chung-Kuan Cheng. 555-558 [doi]
• Texture filter memory: a power-efficient and scalable texture memory architecture for mobile graphics processorsB. V. N. Silpa, Anjul Patney, Tushar Krishna, Preeti Ranjan Panda, G. S. Visweswaran. 559-564 [doi]
• SPM management using Markov chain based data access predictionTaylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Ozcan Ozturk. 565-569 [doi]
• Process variation aware system-level task allocation using stochastic ordering of delay distributionsLove Singhal, Elaheh Bozorgzadeh. 570-574 [doi]
• Game-theoretic timing analysisSanjit A. Seshia, Alexander Rakhlin. 575-582 [doi]
• Integrated code and data placement in two-dimensional mesh based chip multiprocessorsTaylan Yemliha, Shekhar Srikantaiah, Mahmut T. Kandemir, Mustafa Karaköy, Mary Jane Irwin. 583-588 [doi]
• Hybrid CMOS-STTRAM non-volatile FPGA: design challenges and optimization approachesSomnath Paul, Saibal Mukhopadhyay, Swarup Bhunia. 589-592 [doi]
• On the modeling of resistance in graphene nanoribbon (GNR) for future interconnect applicationsTamer Ragheb, Yehia Massoud. 593-597 [doi]
• A low-overhead fault tolerance scheme for TSV-based 3D network on chip linksIgor Loi, Subhasish Mitra, Thomas H. Lee, Shinobu Fujita, Luca Benini. 598-602 [doi]
• ThermalScope: multi-scale thermal analysis for nanometer-scale integrated circuitsNicholas Allec, Zyad Hassan, Li Shang, Robert P. Dick, Ronggui Yang. 603-610 [doi]
• Parameterized transient thermal behavioral modeling for chip multiprocessorsDuo Li, Sheldon X.-D. Tan, Eduardo H. Pacheco, Murli Tirumala. 611-617 [doi]
• Temperature aware task sequencing and voltage scalingRamkumar Jayaseelan, Tulika Mitra. 618-623 [doi]
• Statistical path selection for at-speed testVladimir Zolotov, Jinjun Xiong, Hanif Fatemi, Chandu Visweswariah. 624-631 [doi]
• Power supply signal calibration techniques for improving detection resolution to hardware TrojansReza M. Rad, Xiaoxiao Wang, Mohammad Tehranipoor, Jim Plusquellic. 632-639 [doi]
• Path-RO: a novel on-chip critical path delay measurement under process variationsXiaoxiao Wang, Mohammad Tehranipoor, Ramyanshu Datta. 640-646 [doi]
• Multigrid on GPU: tackling power grid analysis on parallel SIMT platformsZhuo Feng, Peng Li. 647-654 [doi]
• Efficient and accurate eye diagram prediction for high speed signalingRui Shi, Wenjian Yu, Yi Zhu, Chung-Kuan Cheng, Ernest S. Kuh. 655-661 [doi]
• A capacitance solver for incremental variation-aware extractionTarek A. El-Moselhy, Ibrahim M. Elfadel, Luca Daniel. 662-669 [doi]
• Lightweight secure PUFsMehrdad Majzoobi, Farinaz Koushanfar, Miodrag Potkonjak. 670-673 [doi]
• Hardware protection and authentication through netlist level obfuscationRajat Subhra Chakraborty, Swarup Bhunia. 674-677 [doi]
• MUTE-AES: a multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithmJude Angelo Ambrose, Sri Parameswaran, Aleksandar Ignjatovic. 678-684 [doi]
• Process variability-aware transient fault modeling and analysisNatasa Miskov-Zivanov, Kai-Chiang Wu, Diana Marculescu. 685-690 [doi]
• STEEL: a technique for stress-enhanced standard cell library designBrian Cline, Vivek Joshi, Dennis Sylvester, David Blaauw. 691-697 [doi]
• A statistical approach for full-chip gate-oxide reliability analysisKaviraj Chopra, Cheng Zhuo, David Blaauw, Dennis Sylvester. 698-705 [doi]
• Robust FPGA resynthesis based on fault-tolerant Boolean matchingYu Hu, Zhe Feng 0002, Lei He, Rupak Majumdar. 706-713 [doi]
• Fault tolerant placement and defect reconfiguration for nano-FPGAsAmit Agarwal, Jason Cong, Brian Tagiku. 714-721 [doi]
• Thermal-aware reliability analysis for platform FPGAsPrasanth Mangalagiri, Sungmin Bae, Krishnan Ramakrishnan, Yuan Xie, Vijaykrishnan Narayanan. 722-727 [doi]
• Guaranteed stable projection-based model reduction for indefinite and unstable linear systemsBradley N. Bond, Luca Daniel. 728-735 [doi]
• Sparse implicit projection (SIP) for reduction of general many-terminal networksZuochang Ye, Dmitry Vasilyev, Zhenhai Zhu, Joel R. Phillips. 736-743 [doi]
• Modeling and simulation for on-chip power grid networks by locally dominant Krylov subspace methodBoyuan Yan, Sheldon X.-D. Tan, Gengsheng Chen, Lifeng Wu. 744-749 [doi]
• Integrated circuit design with NEM relaysFred Chen, Hei Kam, Dejan Markovic, Tsu-Jae King Liu, Vladimir Stojanovic, Elad Alon. 750-757 [doi]
• Module locking in biochemical synthesisBrian Fett, Marc D. Riedel. 758-764 [doi]
• Robust reconfigurable filter design using analytic variability quantification techniquesArthur Nieuwoudt, Jamil Kawa, Yehia Massoud. 765-770 [doi]
• Using test data to improve IC quality and yieldAnne Gattiker. 771-777 [doi]
• Silicon feedback to improve frequency of high-performance microprocessors: an overviewChandramouli V. Kashyap, Pouria Bastani, Kip Killpack, Chirayu S. Amin. 778-782 [doi]
• Incorporating logic exclusivity (LE) constraints in noise analysis using gain guided backtracking methodRuiming Li, An-Jui Shey, Michel Laudes. 783-789 [doi]
• Constrained aggressor set selection for maximum coupling noiseDebjit Sinha, Gregory Schaeffer, Soroush Abbaspour, Alex Rubin, Frank Borkam. 790-796 [doi]
• Context-sensitive static transistor-level IR analysisWeiqing Guo, Yu Zhong, Tom Burd. 797-802 [doi]
• Frequency-aware PPV: a robust phase macromodel for accurate oscillator noise analysisXiaolue Lai. 803-806 [doi]
• Smoothed form of nonlinear phase macromodel for oscillatorsMark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Brian J. Mulvaney, Kiran K. Gullapalli. 807-814 [doi]
• Comprehensive procedure for fast and accurate coupled oscillator network simulationPrateek Bhansali, Shweta Srivastava, Xiaolue Lai, Jaijeet S. Roychowdhury. 815-820 [doi]