James D. Meindl - researchr alias

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Viewing Publication 1 - 59 from 59

2010

Nanoelectronics in retrospect, prospect and principleJames D. Meindl, Azad Naeemi, Muhannad S. Bakir, R. Murali. isscc 2010: 31-35 [doi]

2008

2007

2006

Prospects for Wafer-Level Testing of Gigascale Chips with Electrical and Optical I/O InterconnectsHiren D. Thacker, James D. Meindl. itc 2006: 1-7 [doi]

2004

Global interconnect design in a three-dimensional system-on-a-chipJames W. Joyner, Payman Zarkesh-Ha, James D. Meindl. tvlsi, 12(4):367-372, 2004.

Relative inductance extraction methodKaveh Shakeri, James D. Meindl. cicc 2004: 481-484 [doi]

Coaxial polymer pillars: ultra-low inductance compliant wafer-level electrical input/output interconnects for power distributionKaveh Shakeri, Muhannad S. Bakir, James D. Meindl. socc 2004: 78-81 [doi]

2003

Modeling technology impact on cluster microprocessor performanceLucian Codrescu, S. Nugent, James D. Meindl, D. Scott Wills. tvlsi, 11(5):909-920, 2003. [doi]

Interconnect Opportunities for Gigascale IntegrationJames D. Meindl. micro, 23(3):28-35, 2003. [doi]

Beyond Moore's Law: the interconnect eraJames D. Meindl. cse, 5(1):20-24, 2003. [doi]

2002

Sea of leads (SoL) characterization and design for compatibility with board-level optical waveguide interconnectionMuhannad S. Bakir, Hollie A. Reed, Anthony V. Mule, Paul A. Kohl, Kevin P. Martin, James D. Meindl. cicc 2002: 491-494 [doi]

Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integrationKeith A. Bowman, Steven G. Duvall, James D. Meindl. jssc, 37(2):183-190, 2002. [doi]

Interconnect opportunities for gigascale integrationJames D. Meindl, Jeffrey A. Davis, Payman Zarkesh-Ha, Chirag S. Patel, Kevin P. Martin, Paul A. Kohl. ibmrd, 46(2-3):245-264, 2002. [doi]

Electrical and optical clock distribution networks for gigascale microprocessorsA. V. Mule, Elias N. Glytsis, Thomas K. Gaylord, James D. Meindl. tvlsi, 10(5):582-594, 2002. [doi]

Low-power circuit advantages of the scaled accumulation FETR. Murali, Lihui Wang, Blanca Austin, James D. Meindl. iscas 2002: 201-204 [doi]

Temperature Variable Supply Voltage for Power ReductionKaveh Shakeri, James D. Meindl. isvlsi 2002: 71-74 [doi]

A compact delay model for series-connected MOSFETsKaveh Shakeri, James D. Meindl. glvlsi 2002: 37-40 [doi]

A physical model for the transient response of capacitively loaded distributed rlc interconnectsRaguraman Venkatesan, Jeffrey A. Davis, James D. Meindl. dac 2002: 763-766 [doi]

2001

Interconnect-centric Array Architectures for Minimum SRAM Access TimeAzeez J. Bhavnagarwala, Stephen V. Kosonocky, James D. Meindl. iccd 2001: 400-405

The impact of intrinsic device fluctuations on CMOS SRAM cell stabilityAzeez J. Bhavnagarwala, Xinghai Tang, James D. Meindl. jssc, 36(4):658-665, 2001. [doi]

Impact of within-die parameter fluctuations on future maximum clock frequency distributionsKeith A. Bowman, James D. Meindl. cicc 2001: 229-232 [doi]

Architecture of the Atlas Chip-Multiprocessor: Dynamically Parallelizing Irregular ApplicationsLucian Codrescu, D. Scott Wills, James D. Meindl. TC, 50(1):67-82, 2001. [doi]

Interconnect limits on gigascale integration (GSI) in the 21st centuryJeffery A. Davis, Raguraman Venkatesan, Alan Kaloyeros, Michael Beylansky, Shukri J. Souri, Kaustav Banerjee, Krishna C. Saraswat, Arifur Rahman, Rafael Reif, James D. Meindl. pieee, 89(3):305-324, 2001. [doi]

Impact of three-dimensional architectures on interconnects in gigascale integrationJames W. Joyner, Raguraman Venkatesan, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl. tvlsi, 9(6):922-928, 2001. [doi]

Special issue on limits of semiconductor technologyJames D. Meindl. pieee, 89(3):223-226, 2001. [doi]

On The Micro-architectural Impact of Clock Distribution Using Multiple PLLsMartin Saint-Laurent, Madhavan Swaminathan, James D. Meindl. iccd 2001: 214-220

Optimal n-tier multilevel interconnect architectures for gigascale integration (GSI)Raguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl. tvlsi, 9(6):899-912, 2001. [doi]

2000

CMOS system-on-a-chip voltage scaling beyond 50nmAzeez J. Bhavnagarwala, Blanca Austin, Ashok Kapoor, James D. Meindl. glvlsi 2000: 7-12 [doi]

A minimum total power methodology for projecting limits on CMOS GSIAzeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl. tvlsi, 8(3):235-251, 2000. [doi]

Heterogeneous architecture models for interconnect-motivated system designSek M. Chai, Tarek M. Taha, D. Scott Wills, James D. Meindl. tvlsi, 8(6):660-670, 2000. [doi]

A compact physical via blockage modelQiang Chen, Jeffrey A. Davis, Payman Zarkesh-Ha, James D. Meindl. tvlsi, 8(6):689-692, 2000. [doi]

Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session)Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl. slip 2000: 147-148 [doi]

Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architecturesJames W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl. slip 2000: 123-127 [doi]

The fundamental limit on binary switching energy for terascale integration (TSI)James D. Meindl, Jeffrey A. Davis. jssc, 35(10):1515-1516, 2000. [doi]

Minimum power and area n-tier multilevel interconnect architectures using optimal repeater insertionRaguraman Venkatesan, Jeffrey A. Davis, Keith A. Bowman, James D. Meindl. islped 2000: 167-172 [doi]

Prediction of net-length distribution for global interconnects in a heterogeneous system-on-a-chipPayman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl. tvlsi, 8(6):649-659, 2000. [doi]

Prediction of interconnect fan-out distribution using Rent s rulePayman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl. slip 2000: 107-112 [doi]

1999

1998

Minimum supply voltage for bulk Si CMOS GSIAzeez J. Bhavnagarwala, Blanca Austin, James D. Meindl. islped 1998: 100-102 [doi]

On a pin versus gate relationship for heterogeneous systems: heterogeneous Rent's rulePayman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl. cicc 1998: 93-96 [doi]

1997

A history of low power electronics: how it began and where it s headedJames D. Meindl. islped 1997: 149-151 [doi]

Intrinsic MOSFET parameter fluctuations due to random dopant placementXinghai Tang, Vivek De, James D. Meindl. tvlsi, 5(4):369-376, 1997. [doi]

1996

Circuit techniques for low-power CMOS GSIAzeez J. Bhavnagarwala, Vivek De, Blanca Austin, James D. Meindl. islped 1996: 193-196 [doi]

A dynamic energy recycling logic family for ultra-low-power gigascale integration (GSI)Vivek De, James D. Meindl. islped 1996: 371-375 [doi]

Effects of random MOSFET parameter fluctuations on total power consumptionXinghai Tang, Vivek De, James D. Meindl. islped 1996: 233-236 [doi]

1995

Low power microelectronics: retrospect and prospectJames D. Meindl. pieee, 83(4):619-635, 1995. [doi]

1994

Short channel models and scaling limits of SOI and bulk MOSFETsBhavna Agrawal, Vivek K. De, Joseph M. Pimbley, James D. Meindl. jssc, 29(2):122-125, February 1994. [doi]

1991

Design and Test Automation-Gigascale Integration (GSI) in the 21st CenturyJames D. Meindl. iccd 1991: 438

Gigascale integration (GSI) technologyJames D. Meindl. sc 1991: 534-538 [doi]

1986

Scanning the issueKenneth A. Pickar, James D. Meindl. pieee, 74(12):1603-1604, 1986. [doi]

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2010

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1986

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