Table of Contents

• Survey of low power techniques for ROMsEdwin de Angel, Earl E. Swartzlander Jr.. 7-11 [doi]
• High-performance, low-power design techniques for dynamic to static logic interfaceJune Jiang, Kan Lu, Uming Ko. 12-17 [doi]
• LVDCSL: low voltage differential current switch logic, a robust low power DCSL familyDinesh Somasekhar, Kaushik Roy. 18-23 [doi]
• System-level power optimization of special purpose applications: the beach solutionLuca Benini, Giovanni De Micheli, Enrico Macii, Massimo Poncino, Stefano Quer. 24-29 [doi]
• Formalized methodology for data reuse exploration in hierarchical memory mappingsJean-Philippe Diguet, Sven Wuytack, Francky Catthoor, Hugo De Man. 30-35 [doi]
• A low-power design method using multiple supply voltagesMutsunori Igarashi, Kimiyoshi Usami, Kazutaka Nogami, Fumihiro Minami, Yukio Kawasaki, Takahiro Aoki, Midori Takano, Chiharo Mizuno, Takashi Ishikawa, Masahiro Kanazawa, Shinji Sonoda, Makoto Ichida, Naoyuki Hatanaka. 36-41 [doi]
• Minimizing power dissipation of cellular phonesSven Mattisson. 42-45 [doi]
• A 1V, 5mW, 1.8GHz balanced voltage-controlled oscillator with an integrated resonatorDonald A. Hitko, Theodore L. Tewksbury, Charles Sodini. 46-51 [doi]
• Delta Sigma frequency-to-time conversion by triangularly weighted ZC counterMats Erling Høvin, S. Kiaei, Tor Sverre Lande. 52-55 [doi]
• A symbolic algorithm for low-power sequential synthesisBalakrishna Kumthekar, In-Ho Moon, Fabio Somenzi. 56-61 [doi]
• Low power high level synthesis by increasing data correlationDongwan Shin, Kiyoung Choi. 62-67 [doi]
• A programmable power-efficient decimation filter for software radiosEmad N. Farag, Ran-Hong Yan, Mohamed I. Elmasry. 68-71 [doi]
• Techniques for low energy softwareHuzefa Mehta, Robert Michael Owens, Mary Jane Irwin, Rita Yu Chen, Debashree Ghosh. 72-75 [doi]
• Low power multiplication for FIR filtersChris J. Nicol, Patrik Larsson. 76-79 [doi]
• Low-power H.263 video CoDec dedicated to mobile computingMorgan Hirosuke Miki, Gen Fujita, Takao Onoye, Isao Shirakawa. 80-83 [doi]
• Scheduling for power reduction in a real-time systemJason J. Brown, Danny Z. Chen, Garrison W. Greenwood, Xiaobo Hu, Richard W. Taylor. 84-87 [doi]
• Engineering change for power optimization using global sensitivity and synthesis flexibilityPremal Buch, Christopher K. Lennard, A. Richard Newton. 88-91 [doi]
• Synthesis of low-power asynchronous circuits in a specified environmentSteven M. Nowick, Michael Theobald. 92-95 [doi]
• Quasi-static energy recovery logic and supply-clock generation circuitsYibin Ye, Kaushik Roy, Georgios I. Stamoulis. 96-99 [doi]
• A new 4-2 adder and booth selector for low power MAC unitBum-Sik Kim, Dae-Hyum Chung, Lee-Sup Kim. 100-103 [doi]
• Enhanced prediction of energy losses during adiabatic chargingA. Schlaffer, Josef A. Nossek. 104-107 [doi]
• Charge-pump assisted low-power/low-voltage CMOS opamp designJ. Zhou, R. M. Ziazadeh, H.-H. Ng, H.-T. Ng, David J. Allstot. 108-109 [doi]
• A low voltage CMOS current sourceDetlev Schmitt, Terri S. Fiez. 110-113 [doi]
• New stability criteria for the design of low-pass sigma-delta modulatorsJ. A. E. P. van Engelen, Rudy J. van de Plassche. 114-118 [doi]
• A capacitor-based D/A converter with continuous time output for low-power applicationsLapoe Lynn, Paul Ferguson Jr.. 119-124 [doi]
• Cycle-accurate macro-models for RT-level power analysisQinru Qiu, Qing Wu, Massoud Pedram, Chih-Shun Ding. 125-130 [doi]
• A method of redundant clocking detection and power reduction at RT level designMitsuhisa Ohnishi, Akihisa Yamada, Hiroaki Noda, Takashi Kambe. 131-136 [doi]
• Power analysis of a 32-bit RISC microcontroller integrated with a 16-bit DSPR. S. Bajwa, N. Schumann, H. Kojima. 137-142 [doi]
• Analytical energy dissipation models for low-power cachesMilind B. Kamble, Kanad Ghose. 143-148 [doi]
• A history of low power electronics: how it began and where it s headedJames D. Meindl. 149-151 [doi]
• Issues and directions in low power design tools: an industrial perspectiveJerry Frenkil. 152-157 [doi]
• System-level power estimation and optimization - challenges and perspectivesJan M. Rabaey. 158-160 [doi]
• Dynamic algorithm transformation (DAT) for low-power adaptive signal processingManish Goel, Naresh R. Shanbhag. 161-166 [doi]
• Low power motion estimation design using adaptive pixel truncationZhong-Li He, Kai-Keung Chan, Chi-Ying Tsui, Ming L. Liou. 167-172 [doi]
• Low power signal processing architectures for network microsensorsMichael J. Dong, K. Geoffrey Yung, William J. Kaiser. 173-177 [doi]
• K2: an estimator for peak sustainable power of VLSI circuitsMichael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel. 178-183 [doi]
• Switching activity estimation using limited depth reconvergent path analysisJosé C. Costa, José C. Monteiro, Srinivas Devadas. 184-189 [doi]
• Composite sequence compaction for finite-state machines using block entropy and high-order Markov modelsRadu Marculescu, Diana Marculescu, Massoud Pedram. 190-195 [doi]
• Reducing TLB power requirementsToni Juan, Tomás Lang, Juan J. Navarro. 196-201 [doi]
• Exploiting the locality of memory references to reduce the address bus energyEnric Musoll, Tomás Lang, Jordi Cortadella. 202-207 [doi]
• An extended addressing mode for low powerAtul Kalambur, Mary Jane Irwin. 208-213 [doi]
• Minimizing energy dissipation in high-speed multipliersRafael Fried. 214-219 [doi]
• A one division per clock pipelined division architecture based on LAPR (lookahead of partial-remainder) for low-power ECC applicationsHyung-Joon Kwon, Kwyro Lee. 220-224 [doi]
• Power reduction techniques for a spread spectrum based correlatorDavid Garrett, Mircea R. Stan. 225-230 [doi]
• A sequential procedure for average power analysis of sequential circuitsLi-Pen Yuan, Sung-Mo Kang. 231-234 [doi]
• Energy delay measures of barrel switch architectures for pre-alignment of floating point operands for additionR. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili. 235-238 [doi]
• Analysis of power consumption in memory hierarchiesPatrick Hicks, Matthew Walnock, Robert Michael Owens. 239-242 [doi]
• The impact of SOI MOSFETs on low power digital circuitsYing-Che Tseng, Steven C. Chin, Jason C. S. Woo. 243-246 [doi]
• On the power dissipation in dynamic threshold silicon-on-insulator CMOS inverterWei Jin, Philip C. H. Chan, Mansun Chan. 247-250 [doi]
• Analogue LSI RF switch and beamforming matrixes for communications satellitesMarkku Åberg, Anssi Leppänen, Arto Rantala, Jouko Marjonen. 251-254 [doi]
• Low power architecture for high speed infrared wireless communication systemHiroshi Uno, Keiji Kumatani, Hiroyuki Okuhata, Isao Shirakawa, Toru Chiba. 255-258 [doi]
• Low power data processing by elimination of redundant computationsMir Azam, Paul D. Franzon, Wentai Liu. 259-264 [doi]
• An object code compression approach to embedded processorsYukihiro Yoshida, Bao-Yu Song, Hiroyuki Okuhata, Takao Onoye, Isao Shirakawa. 265-268 [doi]
• Low power multiplexer decompositionUnni Narayanan, Hon Wai Leong, Ki-Seok Chung, Chien-Liang Liu. 269-274 [doi]
• Node normalization and decomposition in low power technology mappingWinfried Nöth, Reiner Kolla. 275-280 [doi]
• A gate resizing technique for high reduction in power consumptionPatrick Girard, Christian Landrault, Serge Pravossoudovitch, D. Severac. 281-286 [doi]
• Re-mapping for low power under tight timing constraintsPatrick Vuillod, Luca Benini, Giovanni De Micheli. 287-292 [doi]
• Low power design without compromise (panel)Jim Burr, Anantha Chandrakasan, Fari Assaderaghi, Francky Catthoor, Frank Fox, Dave Greenhill, Deo Singh, Jim Sproch. 293-294 [doi]
• SOI CMOS as a mainstream low power technology: a critical assessmentDimitri A. Antoniadis. 295-300 [doi]
• Fully depleted CMOS/SOI device design guidelines for low power applicationsSrinivasa R. Banna, Philip C. H. Chan, Mansun Chan, Samuel K. H. Fung, Ping K. Ko. 301-306 [doi]
• Hybrid dual-threshold design techniques for high-performance processors with low-power featuresUming Ko, Andrew Pua, Anthony M. Hill, Pranjal Srivastava. 307-311 [doi]
• Device and technology optimizations for low power design in deep sub-micron regimeKai Chen 0002, Chenming Hu. 312-316 [doi]
• Supply and threshold voltage optimization for low power designDavid J. Frank, Paul Solomon, Scott Reynolds, John Shin. 317-322 [doi]
• Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental resultsDragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current. 323-327 [doi]
• AC-1: a clock-powered microprocessorWilliam C. Athas, Nestoras Tzartzanis, Lars J. Svensson, Lena Peterson, Huimin Li, Xing Yu Jiang, Peiqing Wang, W. C. Liu. 328-333 [doi]