K. Wayne Current - researchr alias

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Viewing Publication 1 - 35 from 35

2008

Jitter Analysis of Nonautonomous MOS Current-Mode Logic CircuitsMarko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija. tcas, 55-I(10):3038-3049, 2008. [doi]

2007

A High-Voltage SOI CMOS Exciter Chip for a Programmable Fluidic Processor SystemK. Wayne Current, Kelvin Yuk, Charles McConaghy, Peter R. C. Gascoyne, Jon A. Schwartz, Jody V. Vykoukal, Craig Andrews. tbcas, 1(2):105-115, 2007. [doi]

2005

A New Model for Timing Jitter Caused by Device Noise in Current-Mode Logic Frequency DividersMarko Aleksic, Nikola Nedovic, K. Wayne Current, Vojin G. Oklobdzija. patmos 2005: 724-732 [doi]

2004

Low-Power Voltage Comparator Circuit for CMOS Quaternary LogicYongjian Brandon Guo, K. Wayne Current. mvl, 10(3):225-260, 2004. [doi]

2002

Voltage Comparator Circuits for Multiple-Valued CMOS LogicYongjian Brandon Guo, K. Wayne Current. ismvl 2002: 67 [doi]

2000

1998

CMOS implementation of low-power oscillators based on the modified Fabre-Normand current conveyorJelena Popovic, Borivoje Nikolic, K. Wayne Current, Aleksandra Pavasovic, Dragan Vasiljevic. icecsys 1998: 349-352 [doi]

1997

Clocked CMOS adiabatic logic with integrated single-phase power-clock supply: experimental resultsDragan Maksimovic, Vojin G. Oklobdzija, Borivoje Nikolic, K. Wayne Current. islped 1997: 323-327 [doi]

1996

Low-Energy Logic Circuit Techniques for Multiple-Valued LogicK. Wayne Current, Vojin G. Oklobdzija, Dragan Maksimovic. ismvl 1996: 86 [doi]

1995

Memory Circuits for Multiple-Valued Logic Voltage SignalsK. Wayne Current. ismvl 1995: 52-57 [doi]

A CMOS continuous-time NTSC-to-color-difference decoderJames F. Parker, K. Wayne Current, Stephen H. Lewis. jssc, 30(12):1524-1532, December 1995. [doi]

1994

Quaternary Multiplier CircuitWei-Shang Chu, K. Wayne Current. ismvl 1994: 15-18

Current-mode CMOS multiple-valued logic circuitsK. Wayne Current. jssc, 29(2):95-107, February 1994. [doi]

1993

Multiple Valued Logic: Current-Mode CMOS CircuitsK. Wayne Current. ismvl 1993: 176-181

Block-Diagram-Level Design Capture, Functional Simulation, and Layout Assembly of Analog CMOS ICsK. Wayne Current, Jim Parker, Wes Hardaker. iscas 1993: 2090-2093

1992

A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter CircuitK. Wayne Current. ismvl 1992: 229-234

High-speed computation of the Radon transform and backprojection using an expandable multiprocessor architectureEric Shieh, K. Wayne Current, Paul J. Hurst, Iskender Agi. tcsv, 2(4):347-360, 1992. [doi]

1991

A Bi-Directional Current-Mode CMOS Multiple-Valued Logic Memory CircuitK. Wayne Current, M. E. Hurlston. ismvl 1991: 196-202

A new VLSI architecture for real-time control of robot manipulatorsJ. Liu, Ziqiang Mao, G. Z. Lu, W. H. Han, Tien C. Hsia, K. Wayne Current, Wei-Shang Chu. icra 1990: 1828-1835 [doi]

1990

A CMOS Quaternary Threshold Logic Full Adder Circuit with Transparent LatchK. Wayne Current. ismvl 1990: 168-173

A VLSI architecture for two-dimensional Radon transform computationsPaul J. Hurst, K. Wayne Current, Iskender Agi, Eric Shieh. icassp 1990: 933-936 [doi]

1989

An architecture for region boundary extraction in raster scan images suitable for VLSI implementationJames M. Apffel, K. Wayne Current, Jorge L. C. Sanz, Anil K. Jain 0002. mva, 2(4):193-214, 1989. [doi]

A Radon transform computer for multidimensional signal processingStephen Azevedo, James M. Brase, Harry E. Martz, Anil K. Jain 0002, K. Wayne Current, Paul J. Hurst. icassp 1989: 1457-1459 [doi]

1986

Characteristics of Prototype CMOS Quaternary Logic Encoder-Decoder CircuitsJames L. Mangin, K. Wayne Current. TC, 35(2):157-161, 1986.

1980

Pipelined Binary Parallel Counters Employing Latched Quaternary Logic Full AddersK. Wayne Current. TC, 29(5):400-403, 1980.

A High Data-Rate Digital Output Correlator DesignK. Wayne Current. TC, 29(5):403-405, 1980.

High Density Integrated Computing Circuitry with Multiple Valued LogicK. Wayne Current. TC, 29(2):191-195, 1980.

1979

Implementing Parallel Counters with Four-Valued Threshold LogicK. Wayne Current, Douglas A. Mow. TC, 28(3):200-204, 1979.

A high data rate, low power all-digital correlation circuit designK. Wayne Current, Douglas A. Mow, S. Youssef-Digaleh. icassp 1979: 859-862 [doi]

1978

Parallel counter design using four-valued threshold logicK. Wayne Current, Douglas A. Mow. icassp 1978: 796-799 [doi]

Applications of multivalued threshold logic in large-scale-intergrated, digital signal processing circuitsK. Wayne Current, Douglas A. Mow. ismvl 1978: 187 [doi]

Four-valued threshold logic full adder circuit implementationsK. Wayne Current, Douglas A. Mow. ismvl 1978: 95-100 [doi]

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