Table of Contents

• Some Experiments in Test Pattern Generation for FPGA-Implemented Combinational CircuitsMichel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian. 3-8 [doi]
• Solving the I/O Bandwidth Problem in System on a Chip TestingWalid Maroufi, Mounir Benabdenbi, Meryem Marzouki. 9-14 [doi]
• Testability Properties of Vertex Precedent BDDsAndré Inácio Reis, A. Prado, Marcelo Lubaszewski. 15-20 [doi]
• ATG-Based Timing Analysis of Circuits Containing Complex GatesJosé Luís Güntzel, A. C. Medina Pinto, Eduardo D'Avila, Ricardo Reis 0001. 21-28 [doi]
• A Bit Scalable Architecture for Fuzzy Processors with Three Inputs and a Flexible Fuzzification UnitRoberto d'Amore. 29-34 [doi]
• Partitioned Branch Condition Resolution LogicAamir A. Farooqui, K. Wayne Current, Vojin G. Oklobdzija. 35-40 [doi]
• Synthesis of High Performance Extended Burst Mode Asynchronous State MachinesDuarte Lopes de Oliveira, Marius Strum, Wang Jiang Chau, Wagner Chiepa Cunha. 41-46 [doi]
• Improved IDEASergio C. Salomão, João M. S. Alcântara, Vladimir Castro Alves, Felipe M. G. França. 47-54 [doi]
• Revisiting Hamiltonian Decomposition of the HypercubeKunio Okuda, Siang W. Song. 55-60 [doi]
• An Input-Output Encoding Approach for Serial DecompositionVenkatesan Muthukumar, Robert J. Bignall, Henry Selvaraj. 61-68 [doi]
• Disjunctive Decomposition of Switching Functions Using Symmetry InformationMalgorzata Chrzanowska-Jeske, Wei Wang, Jing Xia, Marcin Jeske. 69-74 [doi]
• Methods Based on Petri Net for Resource Sharing EstimationPaulo Maciel 0001, Fred Cruz Filho, Edna Barros, Wolfgang Rosenstiel. 75-82 [doi]
• Robust Implementation and Statistical Modeling of a VI-ConverterAchim Graupner, René Schüffny. 83-88 [doi]
• Resizing Rules for the Reuse of MOS Analog DesignsCarlos Galup-Montoro, Márcio C. Schneider. 89-93 [doi]
• Analysis and Design of a Family of Low-Power Class AB Operational AmplifiersFernando Silveira, Denis Flandre. 94-98 [doi]
• A Generator of Trapezoidal Association of Transistors (TAT): Improving Analog Circuits in a Pre-Diffused Transistor ArrayAndré Luiz Aita, Sergio Bampi, Jung Hyun Choi. 99-106 [doi]
• Address Satisfaction for Storage Files with Fifos or Stacks during Scheduling of DSP AlgorithmsCarlos A. Alba Pinto, Koen Van Eijk, Bart Mesman, Jochen A. G. Jess. 107-112 [doi]
• Register Binding for Predicated Execution in DSP ApplicationsQin Zhao, C. A. J. van Eijk, Carlos A. Alba Pinto, Jochen A. G. Jess. 113-118 [doi]
• A Data Path Synthesis Method to Self-Testable Application Specific Integrated Circuit (ASIC)J. Perez R. Cost, José Vieira do Vale Neto. 119-124 [doi]
• From a Hyperdocument-Centric to an Object-Oriented Approach for the Cave ProjectLeandro Soares Indrusiak, Ricardo Augusto da Luz Reis. 125-132 [doi]
• WTROPIC: A WWW-Based Macro-Cell GeneratorJoão Leonardo Fragoso, Fernando Moraes 0001, Ricardo Reis 0001. 133-138 [doi]
• Modular Exponentiation on Fine-Grained FPGAAlexander Tiountchik, Elena Trichina. 139-143 [doi]
• Net by Net Routing with a New Path Search AlgorithmMarcelo O. Johann, Ricardo Reis 0001. 144-149 [doi]
• Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-TransistorPeter Glösekötter, Christian Pacha, Karl F. Goser, Gilson I. Wirth, Werner Prost, Uwe Auer, M. Agethen, P. Velling, Franz-Josef Tegude. 150-158 [doi]
• On the Choice of Models of Computation for Writing Executable Specifications of System Level DesignsIvan Jeukens, Marius Strum. 159-164 [doi]
• Functional Redundancy for Dynamic Exploitation of Performance-Energy Consumption Trade-OffsVictor M. Goulart Ferreira, Hiroto Yasuura. 165-170 [doi]
• Modeling an E1/TU12 Mapper for SDH SystemsReinaldo Silveira, Wilhelmus A. M. Van Noije. 171-176 [doi]
• JPEG Decoding in an Electronic Voting MachineRicardo Pezzuol Jacobi, F. Trindade, José Porfírio A. de Carvalho, R. Cantanhede. 177-184 [doi]
• An FPGA Implementation of the ATM LayerJosé Antônio Gomes de Lima, Elmar U. K. Melchier, Hamilton Soares da Silva. 185-190 [doi]
• Prototyping a Pager-Like Device Using FPGAs: Design of an Object FinderG. A. Cerezo Vasquez, Wilhelmus A. M. Van Noije, Silvio E. Barbin. 191-196 [doi]
• Jet Determination in Liquid Argon Calorimeters Using a Heavily Interconnected System of Field Programmable Gate ArraysB. Dulny, Jürgen Fent, Werner Haberer, Christian Kiesling, A. Osthoff. 197-201 [doi]
• Prototyping of a Biologically-Plausible Vision System for Robotic ApplicationsRené Zapata, Pascal Lépinay, L. Torres, Jacques Droulez, Vincent Creuze. 202-210 [doi]
• Hybrid latch Flip-Flop with Improved Power EfficiencyNikola Nedovic, Vojin G. Oklobdzija. 211-215 [doi]
• SisECO: Design of an Echo-Canceling IC for Base Band ModemsLuciano Agostini, Georg Stemmer, A. Prado, R. Pacheco, T. Campos, Sergio Bampi, Ricardo Reis 0001. 216-221 [doi]
• Modeling of Short Circuit Power Consumption Using Timing-Only Logic Cell MacromodelsEduardo A. C. da Costa, Fernando Paixão Cortes, Rodrigo Ferrugem Cardoso, Luigi Carro, Sergio Bampi. 222-227 [doi]
• The Use of Extended TSPC CMOS Structures to Build Circuits with Doubled Input/Output Data ThroughputJoao Navarro Soares, Wilhelmus A. M. Van Noije. 228-236 [doi]
• Evaluation of a Soft Error Tolerance Technique Based on Time and/or Space RedundancyLorena Anghel, Dan Alexandrescu, Michael Nicolaidis. 237-242 [doi]
• Optimized Generation of VHDL Mutants for Injection of Transition ErrorsRégis Leveugle, K. Hadjiat. 243-248 [doi]
• Recent Improvements on the Specification of Transient-Fault Tolerant VHDL Descriptions: A Case-Study for Area Overhead AnalysisFabian Vargas 0001, Alexandre M. Amory. 249-254 [doi]
• Designing a Radiation Hardened 8051-Like Micro-ControllerFernanda Gusmão de Lima, Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Ricardo Reis 0001, Raoul Velazco, Sana Rezgui. 255-262 [doi]
• JADE: An Embedded Systems Specification, Code Generation and Optimization ToolC. L. Pereira, Diogenes C. da Silva Júnior, R. G. Duarte, Antônio Otávio Fernandes, L. H. Canaan, Claudionor José Nunes Coelho Jr., L. L. Ambrosio. 263-268 [doi]
• An ACL2 Model of VHDL for Symbolic Simulation and Formal VerificationVanderlei Moraes Rodrigues, Dominique Borrione, Philippe Georgelin. 269-274 [doi]
• A New Approach to Solving the Hardware-Software Partitioning Problem in Embedded System DesignDaniel W. Engels, Srinivas Devadas. 275-280 [doi]
• Design of a Classification System for Rectangular Shapes Using a Co-Design EnvironmentRolf Fredi Molz, Paulo Martins Engel, Fernando Gehm Moraes, Lionel Torres, Michel Robert. 281-288 [doi]
• Fault Models and Compact Test Vectors for MOS OpAmp circuitsJosé Vicente Calvano, Vladimir Castro Alves, Marcelo Soares Lubaszewski, Antonio Carneiro de Mesquita Filho. 289-294 [doi]
• Toward Analog Circuit Synthesis: A Global Methodology Based upon Design of ExperimentsYann Deval, Jean-Baptiste Bégueret, Jean Tomas, Pascal Fouillat. 295-300 [doi]
• A JAVA-Based Mixed-Signal Design EnvironmentJochen Mades, Thomas Schneider 0006, Manfred Glesner, André Windisch, Wolfgang Ecker. 301-306 [doi]
• Testing Mixed-Signal Cores307-314 [doi]
• What is the Appropriate Model for Crosstalk Control?Lou Scheffer. 315-320 [doi]
• Efficient /spl nu/MOS Realization of Threshold Voters for Self-Purging RedundancyJosé M. Quintana, Maria J. Avedillo, Esther Rodríguez-Villegas, Adoración Rueda. 321-326 [doi]
• LASCA-Interconnect Parasitic Extraction Tool for Deep-Submicron IC DesignF. K. Ferreira, Fernando Moraes 0001, Ricardo Reis 0001. 327-332 [doi]
• An Integrated Circuit for the in Situ Characterization of CMOS Best-Process MicromachiningBrett Warneke, Kristofer S. J. Pister. 333-340 [doi]
• An Application-Tailored Dynamically Reconfigurable Hardware Architecture for Digital Baseband ProcessingJürgen Becker 0001, Thilo Pionteck, Manfred Glesner. 341-346 [doi]
• Exploiting FPGA-Based Architectures and Design Tools for Problems of Reconfigurable ComputationsIouliia Skliarova, António de Brito Ferrari. 347-352 [doi]
• Synthesis of Control Circuits with Dynamically Modifiable Behavior on the Basis of Statically Reconfigurable FPGAsValery Sklyarov. 353-358 [doi]
• Implementation of Cryptographic Applications on the Reconfigurable FPGA Coprocessor microEnableHolger Singpiel, Harald Simmler, Andreas Kugel, Reinhard Männer, Antônio C. C. Vieira, Federico Gálvez-Durand, João M. S. Alcântara, Vladimir Castro Alves. 359-364 [doi]
• Limits to Voltage Scaling from the Low Power PerspectiveA. Forestier, Mircea R. Stan. 365-370 [doi]
• Adaptive Partial Businvert Encoding for Power Efficient Data Transfer over Wide System BusesRobert Siegmund, Claudia Kretzschmar, Dietmar Müller 0001. 371-376 [doi]
• Energy-Efficient Register AccessJessica H. Tseng, Krste Asanovic. 377-384 [doi]
• Design and Simulation of Heterogeneous Embedded SystemsKlaus D. Müller-Glaser, Eric Sax, Wilhelm Stork, A. Wagner, J. Drescher, Markus Kühl. 385-390 [doi]
• A Comparison of OO and Reactive Based Specifications on the Design of Embedded SystemsSérgio Akira Ito, Júlio C. B. de Mattos, Luigi Carro, Simão S. Toscani. 391-396 [doi]
• A Comparison of Microcontrollers Targeted to FPGA-Based Embedded ApplicationsSérgio Akira Ito, Luigi Carro. 397 [doi]