Table of Contents

• A Superconducting Ternary Systolic Array ProcessorMititada Morisue, Fu-Qiang Li. 10-17
• Heterojunction Bipolar Technology for Emitter-Coupled Multiple-Valued Logic in Gigahertz Adders and MultipliersLutz J. Micheel. 18-26
• Unique Folding and Hysteresis Characteristics of RTD for Multi-Valued Logic and Counting ApplicationsSen Jung Wei, Hung Chang Lin. 27-33
• Easily Testable Multiple-Valued Cellular ArraysNaotake Kamiura, Yutaka Hata, Fujio Miyawaki, Kazuharu Yamato. 36-42
• Aliasing in Multiple-Valued Test Data CompactionGeetani Edirisooriya, John P. Robinson. 43-50
• Direct Cover MVL Minimization with Cost-TablesGerhard W. Dueck. 58-65
• Multiple-Valued Programmable Logic Array Minmization by Simulated AnnealingGerhard W. Dueck, Robert C. Earle, Parthasarathy P. Tirumalai, Jon T. Butler. 66-74
• Experiences of Parallel Processing with Direct Cover Algorithms for Multiple-Valued Logic MinimizationChyan Yang, Onur Oral. 75-82
• Design of a 4-Valued Digital Multiplier Using an Artificial Heterogeneous Two-Layered Neural NetworkChia-Lun J. Hu. 84-87
• A Deductive Neural-Logic SystemJoo-Hwee Lim, Ho-Chung Lui, Hoon heng Teh. 96-102
• Towards the Realization of 4-Valued CMOS CircuitsKonrad Lei, Zvonko G. Vranesic. 104-110
• Incremental Gate: A Method to Compute Minimal Cost CCD Realizations of MVL FunctionsMostafa H. Abd-El-Barr, H. Choy. 111-118
• The Theory of Clipping Voltage-Switches and Design of Quaternary nMOS CircuitsXunwei Wu. 119-125
• An Application of the p-Valued Input, q-Kind-Valued Output Logic to the Synthesis of the p-Valued Logical NetworksTakahiro Haga. 128-137
• On the Efficient Decoding of Reed-Solomon Codes Based on GMD CriterionKiyomichi Araki, Masayuki Takada, Masakatu Morii. 138-145
• Defaults as First-Class CitizensPatrick Doherty, Witold Lukaszewicz. 146-154
• On the Performance of Multivalued Integrated Circuits: Past, Present and FutureDaniel Etiemble. 156-164
• Concurrent Checking and Unidirectional Errors in Multiple-Valued CircuitsDavid Wessels, Jon C. Muzio. 166-173
• Application of Fail-Safe Multiple-Valued Logic to Control of Power PressMasayoshi Sakai, Masakazu Kato, Koichi Futsuhara, Masao Mukaidono. 174-180
• Fault Analysis on Two-Level (K+1)-Valued Logic CircuitsHui Min Wang, Chung-Len Lee, Jwu E. Chen. 181-188
• (n+1)-Valued Modal Implicative SemilatticesM. C. Canals Frau, Aldo V. Figallo. 190-196
• Fuzzifying Topological Groups Based on Completely Distributive Residuated Lattice-Valued Logic (I)Jizhong Shen. 198-205
• Dynamic Current-Mode Multi-Valued MOS Memory with Error CorrectionEdward K. F. Lee, P. Glenn Gulak. 208-215
• Bi-CMOS Current Mode Multiple Valued Logic Circuits with 1.5V Supply VoltageKazutaka Taniguchi, Mamoru Sasaki, Yutaka Ogata, Fumio Ueno, Takahiro Inoue. 216-220
• On the Synthesis of MVL Functions for Current-Mode CMOS Circuits ImplementationMostafa H. Abd-El-Barr, M. I. Mahroos. 221-228
• A Current-Mode CMOS Algorithmic Analog-to-Quaternary Converter CircuitK. Wayne Current. 229-234
• On Multiple-Valued Logic Functions Monotonic with Respect to AmbiguityKyoichi Nakashima, Noboru Takagi. 236-242
• Fundamental Properties of Extended Kleene-Stone Logic FunctionsNoboru Takagi, Kyoichi Nakashima, Masao Mukaidono. 243-249
• On Set-Valued Functions and Boolean CollectionsRatko Tosic, Ivan Stojmenovic, Dan A. Simovici, Corina Reischer. 250-254
• Rectangular AlgebrasReinhard Pöschel, M. Reichel. 255-260
• A Universal Logic MachineMarek A. Perkowski. 262-271
• Design of a Multiple-Valued Rule-Programmable Matching VLSI Chip for Real-Time Rule-Based SystemsTakahiro Hanyu, Kouichi Takeda, Tatsuo Higuchi. 274-281
• Set-Valued Logic Networks Based on Optical Wavelength MultiplexingShuichi Maeda, Takafumi Aoki, Tatsuo Higuchi. 282-290
• Area-Efficient Implication Circuits for Very Dense Lukasiewicz Logic ArraysJonathan Wayne Mills. 291-298
• Semigrid Sets of Central Relations Over a Finite DomainMasahiro Miyakawa, Akihiro Nozaki, Grant Pogosyan, Ivo G. Rosenberg. 300-307
• A Completeness Criterion for Semi-Affine AlgebrasAgnes Szendrei. 314-319
• Parallel Hardware Algorithms with Redundant Number Representations for Multiple-Valued Arithmetic VLSIShoji Kawahito, Y. Mitsui, Makoto Ishida, Tetsuro Nakamura. 337-345
• Binary Input/Ternary Output Switching Circuits Designed Via the Sign TransformationPhilipp W. Besslich, E. A. Trachtenberg. 348-354
• Autocorrelation Techniques for Multi-Bit Decoder PLAsR. Tomczuk, D. Michael Miller. 355-364
• Some Remarks on Fourier Transform and Differential Operators for Digital FunctionsRadomir S. Stankovic. 365-370
• Profiles of Topics and Authors of the International Symposium on Multiple-Valued Logic for 1971-1991Susan W. Butler, Jon T. Butler. 372-379
• Optimal Output Assignment and the Maximum Number of Implicants Needed to Cover the Multiple-Valued Logic FunctionsYutaka Hata, Fujio Miyawaki, Kazuharu Yamato. 389-395
• On the Use of Multiple-Valued Switch-Level Algebra to Analyze Binary MOS Bridge Circuits and Dynamic CircuitsMou Hu, Shensheng Xu, Kenneth C. Smith. 396-400
• Fast Logic Synthesis Based Upon Ternary Universal Logic Module ::::::f::::::Benchu Fei, Nan Zhuang. 401-407
• An Automatic Adjustment Method of Backpropagation Learning Parameters, Using Fuzzy InferenceFumio Ueno, Takahiro Inoue, Badur-ul-Haque Baloch, Takayoshi Yamamoto. 410-414
• A Meaningful Infinite-Valued Switching Function - Fuzzy Threshold Function and Its Application to Process ControlYoshinori Yamamoto. 415-422
• Inverted Pendulum Controlled Circuit Using Fuzzy State Memory with Voltage Mode Fuzzy State MemoryYuji Shirai, Fumio Ueno, Takahiro Inoue, Motohiro Inoue, Kouji Tasaki. 423-427
• A Proposal of Fault-Checking Fuzzy ControlHiroshi Ito, Takashi Matsubara, Takakazu Kurokawa, Yoshiaki Koga. 428-434
• Efficient Derivation of Reed-Muller Expansions in Multiple-Valued Logic SystemsBerthold Harking, Claudio Moraga. 436-441
• The Generalized Orthonormal Expansion of Functions with Multiple-Valued Inputs and Some of Its ApplicationsMarek A. Perkowski. 442-450
• Optimization of Multiple-Valued AND-EXOR Expressions Using Multiple-Place Decision DiagramsTsutomu Sasao. 451-458
• On a Logic Based on Fuzzy ModalitiesAkira Nakamura. 460-466
• Revision Principle for Approximate Reasoning-Based on Semantic Revising MethodZuliang Shen, Liya Ding, Ho-Chung Lui, Pei-Zhuang Wang, Masao Mukaidono. 467-473
• On Yager s Aggregation OperatorsHeinz J. Skala. 474-477
• Fuzzy Logic and the Calculus of Fuzzy If-Then RulesLotfi A. Zadeh. 480