Abstract is missing.
- Multiple-Valued Logic Design ToolsD. Michael Miller. 2-11
- Fast Synthesis for Ternary Reed-Muller ExpansionQinhua Hong, Benchu Fei, Haomin Wu, Marek A. Perkowski, Nan Zhuang. 14-16
- Multiple-Valued PLA Minimization by Concurrent Multiple and Mixed Simulated AnnealingCem Yildirim, Jon T. Butler, Chyan Yang. 17-23
- Entropic Minimization of Multiple-Valued FunctionsAntonio Lloris-Ruíz, Juan Francisco Gómez-Lopera, Ramón Román-Roldán. 24-28
- Gate Model Networks for Minimization of Multiple-Valued Logic FunctionsYutaka Hata, Takahiro Hozumi, Kazuharu Yamato. 29-34
- A Canonical Disjunctive Form of Extended Kleene-Stone Logic FunctionsNoboru Takagi, Kyoichi Nakashima, Masao Mukaidono. 36-41
- Three-Valued Nonmonotonic LogicZuoquan Lin. 42-47
- Signed Formulas and Annotated LogicsJames J. Lu, Neil V. Murray, Erik Rosenthal. 48-53
- Minimal Resolution Proof Systems for Finitely-Valued Lukasiewicz LogicsE. R. Harley, Zbigniew Stachniak. 54-59
- On the Definition of Modal Operators in Fuzzy LogicHelmut Thiele. 62-67
- Single-Chip Realization of a Fuzzy Logic Controller with Neural Network Structure (NNFLC)Zhenfeng Wang, Dongming Jin, Zhijian Li. 68-73
- Synthesis and Design Automation of Analog Fuzzy Logic VLSI CircuitsLaurent Lemaitre, Marek J. Patyra, Daniel Mlynek. 74-79
- Novel CMOS Scan Design for VLSI TestabilityHaomin Wu, Nan Zhuang, Marek A. Perkowski. 82-86
- A Method of Test Pattern Generation for Multiple-Valued PLA sYasunori Nagata, Chushin Afuso. 87-91
- A Repairable and Diagnosable Cellular Array on Multiple-Valued LogicNaotake Kamiura, Yutaka Hata, Kazuharu Yamato. 92-97
- On Functional EntropyDan A. Simovici, Corina Reischer. 100-104
- Semirigid Sets of Quasilinear ClonesAkihiro Nozaki, Grant Pogosyan, Masahiro Miyakawa, Ivo G. Rosenberg. 105-110
- Some Results on the Decision and Construction for Sheffer Functions in Partial K-Valued LogicRenren Liu. 111-116
- A Fast Algorithm for the Disjunctive Decomposition of ::::m::::-Valued Functions Part I: The Decomposition AlgorithmSami B. Abugharbieh, Samuel C. Lee. 118-125
- A Fast Algorithm for the Disjunctive Decomposition of ::::m::::-Valued Functions Part II: Time Complexity AnalysisSami B. Abugharbieh, Samuel C. Lee. 126-131
- EXORCISM-MV-2: Minimization of Exclusive Sum of Products Expressions for Multiple-Valued Input Incompletely Specified FunctionsNing Song, Marek A. Perkowski. 132-137
- Dreams for New-Device-Based Superchips: From Transistors to EnzymesTakafumi Aoki. 140-149
- Design and Examination of a Multiple-Valued Flip-Flop Circuit with Stair Shaped I-V Curved Device as a Coupling ElementShinji Karasawa, Kazuhiko Yamanouchi. 152-157
- Series Resonant Tunneling Diodes as a Two-Dimensional Memory CellMing-Huei Shieh, Hung Chang Lin. 158-163
- Multiple-Valued Logic Computation Circuits Using Micro- and Nanoelectronic DevicesLutz J. Micheel, Albert H. Taddiken, Alan C. Seabaugh. 164-169
- Multiple Valued Logic: Current-Mode CMOS CircuitsK. Wayne Current. 176-181
- A Representation of Approximate Reasoning with AnalogyKiyotaka Miyai, Yutaka Hata, Kazuharu Yamato. 184-189
- Algebraic Properties of a Learning Multiple-Valued Logic NetworkZheng Tang, Okihiko Ishizuka, Qi-xin Cao, Hiroki Matsumoto. 196-201
- Algorithm and Implementation of a Learning Multiple-Valued Logic NetworkQi-xin Cao, Okihiko Ishizuka, Zheng Tang, Hiroki Matsumoto. 202-207
- Systematic Construction of Natural Deduction Systems for Many-Valued LogicsMatthias Baaz, Christian G. Fermüller, Richard Zach. 208-213
- A Basis for the Comparison of Binary and m-Valued Current Mode Circuits: the Multioperand Addition with Redundant Number SystemsDaniel Etiemble, Keivan Navi. 216-221
- Multiple-Valued Logic Functions Represented by TSUM, TPRODUCT, NOT and VariablesYutaka Hata, Kazuharu Yamato. 222-227
- Decimal Addition and Subtraction Units Using the ::::p::::-Valued Decimal Signed-Digit Number RepresentationNoriaki Muranaka, Shigeru Imanishi, D. Michael Miller. 228-233
- Calculation of Ternary Mixed Polarity Function VectorBenchu Fei, Qinhua Hong, Nan Zhuang. 236-238
- Current-Mode CMOS Galois Field CircuitsZeljko Zilic, Zvonko G. Vranesic. 245-250
- Functional Completeness and Weak Completeness in Set LogicDan A. Simovici, Ivan Stojmenovic, Ratko Tosic. 251-256
- Lukasiewicz Insect: The Role of Continuous-Valued Logic in a Mobile Robot s Sensors, Control, and LocomotionJonathan Wayne Mills. 258-263
- Impact of Interconnection-Free Biomolecular ComputingTakafumi Aoki, Tatsuo Higuchi. 271-276
- Design of Set-Valued Logic Networks for Wave-Parallel ComputingYasushi Yuminaka, Takafumi Aoki, Tatsuo Higuchi. 277-282
- Design of Multiple-Valued Linear Digital Circuits for Highly Parallel Unary OperationsMasami Nakajima, Michitaka Kameyama. 283-288