Enric Musoll - researchr alias

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Viewing Publication 1 - 20 from 20

2011

Variable-size mosaics: A process-variation aware technique to increase the performance of tile-based, massive multi-core processorsEnric Musoll. cee, 37(6):1193-1211, 2011. [doi]

2010

A cost-effective load-balancing policy for tile-based, massive multi-core packet processorsEnric Musoll. tecs, 9(3), 2010. [doi]

Load balancing packets on a tile-based massive multi-core processor with S-NUCAEnric Musoll. ancs 2010: 32 [doi]

Hardware-Based Load Balancing for Massive Multicore Architectures Implementing Power GatingEnric Musoll. tcad, 29(3):493-497, 2010. [doi]

2009

Trading off higher execution latency for increased reliability in tile-based massive multi-core architecturesEnric Musoll. isqed 2009: 201-207 [doi]

Mesh-based many-core performance under process variations: a core yield perspectiveEnric Musoll. sigarch, 37(4):27-34, 2009. [doi]

A Process-Variation Aware Technique for Tile-Based, Massive Multicore ProcessorsEnric Musoll. cal, 8(2):52-55, 2009. [doi]

Leakage-saving opportunities in mesh-based massive multi-core architecturesEnric Musoll. sigarch, 37(5):1-7, 2009. [doi]

2008

Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gatingEnric Musoll. sasp 2008: 89-94 [doi]

A Thermal-Friendly Load-Balancing Technique for Multi-Core ProcessorsEnric Musoll. isqed 2008: 549-552 [doi]

Power Gating Clustered Many-Core ArchitecturesEnric Musoll. jolpe, 4(3):290-300, 2008. [doi]

2003

Speculating to reduce unnecessary power consumptionEnric Musoll. tecs, 2(4):509-536, 2003. [doi]

1999

Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power ProcessorsEnric Musoll. euromicro 1999: 238-247 [doi]

1998

Extension of the working-zone-encoding method to reduce the energy on the microprocessor data busTomás Lang, Enric Musoll, Jordi Cortadella. In ICCD. 1998: 414-419 [doi]

Register-Transfer Level Transformations for Low-Power Data-PathsEnric Musoll, Jordi Cortadella. icae, 5(4):315-332, 1998. [doi]

Working-zone encoding for reducing the energy in microprocessor address busesEnric Musoll, Tomás Lang, Jordi Cortadella. tvlsi, 6(4):568-572, 1998. [doi]

1997

Exploiting the locality of memory references to reduce the address bus energyEnric Musoll, Tomás Lang, Jordi Cortadella. islped 1997: 202-207 [doi]

1996

Optimizing CMOS Circuits for Low Power Using Transistor ReorderingEnric Musoll, Jordi Cortadella. date 1996: 219-223 [doi]

1995

High-level synthesis techniques for reducing the activity of functional unitsEnric Musoll, Jordi Cortadella. islped 1995: 99-104 [doi]

Scheduling and resource binding for low powerEnric Musoll, Jordi Cortadella. isss 1995: 104-109 [doi]

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