Abstract is missing.
- Control Independence in Trace ProcessorsEric Rotenberg, James E. Smith. 4-15 [doi]
- Fetch Directed Instruction PrefetchingGlenn Reinman, Brad Calder, Todd M. Austin. 16-27 [doi]
- Improving Branch Predictors by Correlating on Data ValuesTimothy H. Heil, Zak Smith, James E. Smith. 28-37 [doi]
- Instruction Fetch Mechanisms for Multipath Execution ProcessorsArtur Klauser, Dirk Grunwald. 38 [doi]
- A Superscalar 3D Graphics EngineAndrew Wolfe, Derek B. Noonburg. 50-61 [doi]
- Dynamic 3D Graphics Workload Characterization and the Architectural ImplicationsTulika Mitra, Tzi-cker Chiueh. 62-71 [doi]
- Exploiting a New Level of DLP in Multimedia ApplicationsJesús Corbal, Roger Espasa, Mateo Valero. 72 [doi]
- Compiler-Driven Cached Code Compression Schemes for Embedded ILP ProcessorsSergei Y. Larin, Thomas M. Conte. 82-92 [doi]
- Evaluation of a High Performance Code Compression MethodCharles Lefurgy, Eva Piccininni, Trevor N. Mudge. 93-102 [doi]
- Low-Cost Branch Folding for Embedded Applications with Small Tight LoopsLea Hwang Lee, Jeff Scott, Bill Moyer, John Arends. 103 [doi]
- Automatic and Efficient Evaluation of Memory Hierarchies for Embedded SystemsSantosh G. Abraham, Scott A. Mahlke. 114-125 [doi]
- Hardware Identification of Cache Conflict MissesJamison D. Collins, Dean M. Tullsen. 126-135 [doi]
- Access Region Locality for High-Bandwidth Processor Memory System DesignSangyeun Cho, Pen-Chung Yew, Gyungho Lee. 136-146 [doi]
- Code Transformations to Improve Memory ParallelismVijay S. Pai, Sarita V. Adve. 147 [doi]
- Compiler-Directed Dynamic Computation Reuse: Rationale and Initial ResultsDaniel A. Connors, Wen-mei W. Hwu. 158-169 [doi]
- Dynamic Memory Disambiguation in the Presence of Out-of-Order Store IssuingSoner Önder, Rajiv Gupta. 170-176 [doi]
- Delaying Physical Register Allocation through Virtual-Physical RegistersTeresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals. 186 [doi]
- Core Technologies in Hardware and SoftwareBruce Shriver. 194 [doi]
- DIVA: A Reliable Substrate for Deep Submicron Microarchitecture DesignTodd M. Austin. 196-207 [doi]
- Exploiting ILP in Page-based Intelligent MemoryMark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra. 208-218 [doi]
- The Use of Multithreading for Exception HandlingCraig B. Zilles, Joel S. Emer, Gurindar S. Sohi. 219-229 [doi]
- Value Prediction for Speculative Multithreaded ArchitecturesPedro Marcuello, Jordi Tubella, Antonio González. 230 [doi]
- Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power ProcessorsEnric Musoll. 238-247 [doi]
- Selective Cache Ways: On-Demand Cache Resource AllocationDavid H. Albonesi. 248 [doi]
- Wavefront Scheduling: Path based Data Representation and Scheduling of SubgraphsJay Bharadwaj, Kishore N. Menezes, Chris McKinsey. 262-271 [doi]
- Optimizations and Oracle Parallelism with Dynamic TranslationKemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind. 284 [doi]