Abstract is missing.
- Custom Processor Core Construction from C CodeJelena Trajkovic, Daniel D. Gajski. 1-6 [doi]
- Resource Sharing in Custom Instruction Set ExtensionsMarcela Zuluaga, Nigel P. Topham. 7-13 [doi]
- Custom Instruction Generation with High-Level SynthesisKenshu Seto, Masahiro Fujita. 14-19 [doi]
- Application Acceleration with the Explicitly Parallel Operations System - the EPOS ProcessorAlexandros Papakonstantinou, Deming Chen, Wen-mei W. Hwu. 20-25 [doi]
- Design and Architectural Exploration of Expression-Grained Reconfigurable ArraysGiovanni Ansaloni, Paolo Bonzini, Laura Pozzi. 26-33 [doi]
- Retargeting, Evaluating, and Generating Reconfigurable Array-Based ArchitecturesCarlos Morra, João M. P. Cardoso, João Bispo, Jürgen Becker. 34-41 [doi]
- An FPGA Design Space Exploration Tool for Matrix Inversion ArchitecturesAli Irturk, Bridget Benson, Shahnam Mirzaei, Ryan Kastner. 42-47 [doi]
- Proving Functional Correctness of Weakly Programmable IPs - A Case Study with Formal Property CheckingSacha Loitz, Markus Wedler, Christian Brehm, Timo Vogt, Norbert Wehn, Wolfgang Kunz. 48-54 [doi]
- Extensible On-Chip PeripheralsBharat Sukhwani, Alessandro Forin, Richard Neil Pittman. 55-62 [doi]
- Thermal-aware Design Considerations for Application-Specific Instruction Set ProcessorHai Lin, Guangyu Sun, Yunsi Fei, Yuan Xie, Anand Sivasubramaniam. 63-68 [doi]
- Application Specific Low Latency Instruction Cache for NAND Flash Memory Based Embedded SystemsKwangyoon Lee, Alex Orailoglu. 69-74 [doi]
- An Efficient Design Space Exploration Methodology for On-Chip Multiprocessors Subject to Application-Specific ConstraintsGianluca Palermo, Cristina Silvano, Vittorio Zaccaria. 75-82 [doi]
- AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded ApplicationsTohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato. 83-88 [doi]
- Energy and thermal tradeoffs in hardware-based load balancing for clustered multi-core architectures implementing power gatingEnric Musoll. 89-94 [doi]
- System-Level Performance Estimation for Application-Specific MPSoC Interconnect SynthesisPo-Kuan Huang, Matin Hashemi, Soheil Ghiasi. 95-100 [doi]
- Accelerating Compute-Intensive Applications with GPUs and FPGAsShuai Che, Jie Li, Jeremy W. Sheaffer, Kevin Skadron, John Lach. 101-107 [doi]
- TRaX: A Multi-Threaded Architecture for Real-Time Ray TracingJosef B. Spjut, Solomon Boulos, Daniel Kopta, Erik Brunvand, Spencer Kellis. 108-114 [doi]
- Multi-core Architectures with Dynamically Reconfigurable Array Processors for the WiMAX Physical LayerWei Han, Ying Yi, Mark Muir, Ioannis Nousias, Tughrul Arslan, Ahmet T. Edorgan. 115-120 [doi]
- An MDCT Hardware Accelerator for MP3 AudioXingdong Dai, Meghanad D. Wagh. 121-125 [doi]