Nigel P. Topham - researchr alias

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Viewing Publication 1 - 58 from 58

2023

Run-time integrity monitoring of untrustworthy analog front-endsHeba Salem, Nigel P. Topham. date 2023: 1-6 [doi]

2021

Detecting denial-of-service hardware Trojans in DRAM-based memory systemsHeba Salem, Nigel P. Topham. icecsys 2021: 1-6 [doi]

2020

Fast and Correct Load-Link/Store-Conditional Instruction Handling in DBT SystemsMartin Kristien, Tom Spink, Brian Campbell 0001, Susmit Sarkar, Ian Stark, Björn Franke, Igor Böhm, Nigel P. Topham. tcad, 39(11):3544-3554, 2020. [doi]

2019

Poise: Balancing Thread-Level Parallelism and Memory System Performance in GPUs Using Machine LearningSaumay Dublish, Vijay Nagarajan, Nigel P. Topham. hpca 2019: 492-505 [doi]

Mitigating JIT compilation latency in virtual execution environmentsMartin Kristien, Tom Spink, Harry Wagstaff, Björn Franke, Igor Böhm, Nigel P. Topham. vee 2019: 101-107 [doi]

2018

High Speed Cycle-Approximate Simulation of Embedded Cache-Incoherent and Coherent Chip-MultiprocessorsChristopher Thompson, Miles Gould, Nigel P. Topham. ijpp, 46(6):1247-1282, 2018. [doi]

2015

Efficient dual-ISA support in a retargetable, asynchronous Dynamic Binary TranslatorTom Spink, Harry Wagstaff, Björn Franke, Nigel P. Topham. samos 2015: 103-112 [doi]

2014

Efficient code generation in a region-based dynamic binary translatorTom Spink, Harry Wagstaff, Björn Franke, Nigel P. Topham. lctrts 2014: 3-12 [doi]

2013

A Parallel Dynamic Binary Translator for Efficient Multi-Core SimulationOscar Almer, Igor Böhm, Tobias J. K. Edler von Koch, Björn Franke, Stephen C. Kyle, Volker Seeker, Christopher Thompson, Nigel P. Topham. ijpp, 41(2):212-235, 2013. [doi]

The Smart Cache: An Energy-Efficient Cache Architecture Through Dynamic AdaptationKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. ijpp, 41(2):305-330, 2013. [doi]

RECAP: Region-Aware Cache PartitioningKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. iccd 2013: 294-301 [doi]

High speed cycle approximate simulation for cache-incoherent MPSoCsChristopher Thompson, Miles Gould, Nigel P. Topham. samos 2013: 88-95 [doi]

Early partial evaluation in a JIT-compiled, retargetable instruction set simulator generated from a high-level architecture descriptionHarry Wagstaff, Miles Gould, Björn Franke, Nigel P. Topham. dac 2013: 21 [doi]

2012

Design Space Exploration of Hybrid Ultra Low Power Branch PredictorsMatthew Bielby, Miles Gould, Nigel P. Topham. arcs 2012: 184-199 [doi]

Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translationStephen C. Kyle, Igor Böhm, Björn Franke, Hugh Leather, Nigel P. Topham. lctrts 2012: 21-30 [doi]

Energy-efficient cache partitioning for future CMPsKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. IEEEpact 2012: 465-466 [doi]

Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPsKarthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham, Björn Franke. hpca 2012: 311-322 [doi]

Predicting best design trade-offs: A case study in processor customizationMarcela Zuluaga, Edwin V. Bonilla, Nigel P. Topham. date 2012: 1030-1035 [doi]

2011

Selecting the optimal system: automated design of application-specific systems-on-chipOscar Almer, Miles Gould, Björn Franke, Nigel P. Topham. micro 2011: 43-50 [doi]

A Learning-Based Approach to the Automated Design of MPSoC NetworksOscar Almer, Nigel P. Topham, Björn Franke. arcs 2011: 243-258 [doi]

Scalable multi-core simulation using parallel dynamic binary translationOscar Almer, Igor Böhm, Tobias J. K. Edler von Koch, Björn Franke, Stephen C. Kyle, Volker Seeker, Christopher Thompson, Nigel P. Topham. samos 2011: 190-199 [doi]

Generalized just-in-time trace compilation using a parallel task farm in a dynamic binary translatorIgor Böhm, Tobias J. K. Edler von Koch, Stephen C. Kyle, Björn Franke, Nigel P. Topham. PLDI 2011: 74-85 [doi]

Virtual Manycore platforms: Moving towards 100+ processor coresRainer Leupers, Lieven Eeckhout, Grant Martin, Frank Schirrmeister, Nigel P. Topham, Xiaotao Chen. date 2011: 715-720 [doi]

A reconfigurable cache architecture for energy efficiencyKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. cf 2011: 9 [doi]

Smart cache: A self adaptive cache architecture for energy efficiencyKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. samos 2011: 41-50 [doi]

2010

Cycle-accurate performance modelling in an ultra-fast just-in-time dynamic binary translation instruction set simulatorIgor Böhm, Björn Franke, Nigel P. Topham. samos 2010: 1-10 [doi]

Exploring the unified design-space of custom-instruction selection and resource sharingMarcela Zuluaga, Nigel P. Topham. samos 2010: 282-291 [doi]

2009

2008

Resource Sharing in Custom Instruction Set ExtensionsMarcela Zuluaga, Nigel P. Topham. sasp 2008: 7-13 [doi]

2007

Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systemsRichard Vincent Bennett, Alastair Colin Murray, Björn Franke, Nigel P. Topham. lctrts 2007: 83-92 [doi]

Synthetic Trace-Driven Simulation of Cache MemoryRahman Hassan, Antony Harris, Nigel P. Topham, Aristides Efthymiou. aina 2007: 764-771 [doi]

2003

High performance IDCT realization using complex arithmeticKar-Lik Wong, Nigel P. Topham. icassp 2003: 313-316 [doi]

2002

OneDSP: A unifying DSP architecture for Systems-on-a-ChipKar-Lik Wong, Nigel P. Topham. icassp 2002: 3792-3795 [doi]

2000

Multiple-banked register file architecturesJosé-Lorenzo Cruz, Antonio González, Mateo Valero, Nigel P. Topham. isca 2000: 316-325 [doi]

1999

Distributed Modulo SchedulingMarcio Merino Fernandes, Josep Llosa, Nigel P. Topham. hpca 1999: 130-134 [doi]

Randomized Cache Placement for Eliminating ConflictsNigel P. Topham, Antonio González. TC, 48(2):185-192, 1999. [doi]

1998

Partitioned Schedules for Clustered VLIW ArchitecturesMarcio Merino Fernandes, Josep Llosa, Nigel P. Topham. ipps 1998: 386-391 [doi]

1997

1995

An Assessment of Assignment Schemes for Dependency GraphsSathiamoorthy Manoharan, Nigel P. Topham. pc, 21(1):85-107, 1995.

Compiling and Optimizing for Decoupled ArchitecturesNigel P. Topham, Alasdair Rawsthorne, Callum McLean, Muriel Mewissen, Peter L. Bird. sc 1995: 40 [doi]

Performance of the decoupled ACRI-1 architecture: the perfect clubNigel P. Topham, Kenneth McDougall. hpcn 1995: 472-480

1994

Trace-Driven Simulation of Decoupled ArchitecturesSathiamoorthy Manoharan, Nigel P. Topham, A. W. R. Crawford. hicss 1994: 271-279

1993

The Effectiveness of DecouplingPeter L. Bird, Alasdair Rawsthorne, Nigel P. Topham. ics 1993: 47-56 [doi]

Performance of Weak Consistency Schemes on the DEC AlphaT. Harris, Nigel P. Topham. parco 1994: 429-436

The Performance of Parallel Loops on SCI-Based Memory HierarchiesRoberto A. Hexsel, Nigel P. Topham. parco 1994: 703-706

1992

A Comparison of Two Memory Models for High Performance ComputersPeter L. Bird, Nigel P. Topham, Sathiamoorthy Manoharan. conpar 1992: 399-404

1990

A general bound on schedule length for independent tasksSathiamoorthy Manoharan, Nigel P. Topham. pc, 16(1):69-73, 1990.

1988

Context flow: An alternative to conventional pipelined architecturesNigel P. Topham, Amos Omondi, Roland N. Ibbett. tjs, 2(1):29-53, 1988. [doi]

On the design and performance of conventional pipelined architecturesNigel P. Topham, Amos Omondi, Roland N. Ibbett. tjs, 1(4):353-393, 1988. [doi]

1985

MU6V: A Parallel Vector Processing SystemRoland N. Ibbett, P. C. Capon, Nigel P. Topham. isca 1985: 136-144

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