Abstract is missing.
- Faster unicores are still neededAndré Seznec. [doi]
- What cloud computing can teach us about embedded many-core programming?Andras Vajda. [doi]
- Rethinking computer architecture for throughput computingWen-mei W. Hwu. [doi]
- General purpose computing on low-power embedded GPUs: Has it come of age?Arian Maghazeh, Unmesh D. Bordoloi, Petru Eles, Zebo Peng. 1-10 [doi]
- Parallelizing general histogram application for CUDA architecturesUgljesa Milic, Isaac Gelado, Nikola Puzovic, Alex Ramírez, Milo Tomasevic. 11-18 [doi]
- A scalable FFT processor architecture for OFDM based communication systemsDeepak Revanna, Omer Anjum, Manuele Cucchi, Roberto Airoldi, Jari Nurmi. 19-27 [doi]
- Low-power application-specific FFT processor for LTE applicationsTomasz Patyk, David Guevorkian, Teemu Pitkänen, Pekka Jääskeläinen, Jarmo Takala. 28-32 [doi]
- Abstraction of polychronous dataflow specifications into mode-automataJulien Ouy, Matthew Kracht, Sandeep K. Shukla. 33-40 [doi]
- PiMM: Parameterized and Interfaced dataflow Meta-Model for MPSoCs runtime reconfigurationKarol Desnos, Maxime Pelcat, Jean-François Nezan, Shuvra S. Bhattacharyya, Slaheddine Aridhi. 41-48 [doi]
- Modeling pipelined application with Synchronous Data Flow graphsMarco Lattuada, Fabrizio Ferrandi. 49-55 [doi]
- Parallel implementation of real-time semi-global matching on embedded multi-core architecturesOliver Jakob Arndt, Daniel Becker, Christian Banz, Holger Blume. 56-63 [doi]
- An effective model extraction method with state space compression for model checking SystemC TLM designsYanyan Gao, Xi Li. 64-71 [doi]
- A Process-based Reconfigurable SystemC Module for simulation speedupEfstathios Sotiriou-Xanthopoulos, Kostas Siozios, George Economakos, Dimitrios Soudris. 72-79 [doi]
- MGSim - A simulation environment for multi-core research and educationRaphael Poss, Mike Lankamp, Qiang Yang, Jian Fu, M. Irfan Uddin, Chris R. Jesshope. 80-87 [doi]
- High speed cycle approximate simulation for cache-incoherent MPSoCsChristopher Thompson, Miles Gould, Nigel P. Topham. 88-95 [doi]
- Lightweight resource estimation model to extend battery life in video playbackTero Rintaluoma, Olli Silvén. 96-103 [doi]
- Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAsSyed M. A. H. Jafri, Muhammad Adeel Tajammul, Ahmed Hemani, Kolin Paul, Juha Plosila, Hannu Tenhunen. 104-112 [doi]
- NoC links energy reduction through link voltage scalingAndrea Mineo, Maurizio Palesi, Giuseppe Ascia, Vincenzo Catania. 113-120 [doi]
- Mapping of PRP/HSR redundancy protocols onto a configurable FPGA/CPU based architectureHolger Flatt, Jürgen Jasperneite, Daniel Dennstedt, Tran Dinh Hung. 121-128 [doi]
- An embedded hardware-efficient architecture for real-time cascade Support Vector Machine classificationChristos Kyrkou, Theocharis Theocharides, Christos-Savvas Bouganis. 129-136 [doi]
- SWAN-iCare: A smart wearable and autonomous negative pressure device for wound monitoring and therapyIsabelle Texier, Pierre Marcoux, Pascale Pham, Marie Muller, Pierre-Yves Benhamou, Marc Correvon, Gabriela Dudnik, Guy Voirin, Natascha Bue, Jan Cristensen, Massimo Laurenza, Giuseppe Gazzara, Andreas Raptopoulos, Alexandros Bartzas, Dimitrios Soudris, Carl Saxby, Thierry Navarro, Fabio Di Francesco, Pietro Salvo, Marco Romanelli, Battistino Paggi, Leonidas Lymperopoulos. 137-144 [doi]
- Stochastic modeling and performance analysis of multimedia SoCsBalaji Raman, Ayoub Nouri, Deepak Gangadharan, Marius Bozga, Ananda Basu, Mayur Maheshwari, Axel Legay, Saddek Bensalem, Samarjit Chakraborty. 145-154 [doi]
- Concurrent multi-level arrays: Wait-free extensible hash mapsSteven D. Feldman, Pierre LaBorde, Damian Dechev. 155-163 [doi]
- Efficient runtime support for embedded MPSoCsDimitris Theodoropoulos, Polyvios Pratikakis, Dionisios N. Pnevmatikatos. 164-171 [doi]
- Fast transaction-level dynamic power consumption modelling in priority preemptive wormhole switching networks on chipJames Harbin, Leandro Soares Indrusiak. 172-179 [doi]
- Deploying OpenMP on an embedded multicore acceleratorSpiros N. Agathos, Vassilios V. Dimakopoulos, Aggelos Mourelis, Alexandros Papadogiannakis. 180-187 [doi]
- A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architecturesRicardo S. Ferreira, Vinicius Duarte, Waldir Meireles, Monica Magalhães Pereira, Luigi Carro, Stephan Wong. 188-195 [doi]
- Dynamic task mapping onto multi-core architectures through stream rewritingLars Middendorf, Christian Zebelein, Christian Haubelt. 196-204 [doi]
- An accurate energy model for streaming applications mapped on MPSoC platformsJelena Spasic, Todor Stefanov. 205-212 [doi]
- Pulse-length determination techniques in the rectangular single event transient fault modelAlireza Rohani, Hans G. Kerkhoff, Enrico Costenaro, Dan Alexandrescu. 213-218 [doi]
- Compiler-aided methodology for low overhead on-line testingGhazaleh Nazarian, Robert M. Seepers, Christos Strydis, Georgi Gaydadjiev. 219-226 [doi]
- TimeCube: A manycore embedded processor with interference-agnostic progress trackingAnshuman Gupta, Jack Sampson, Michael Bedford Taylor. 227-236 [doi]
- ECONO: Express coherence notifications for efficient cache coherency in many-core CMPsJosé L. Abellán, Alberto Ros, Juan Fernández Peinador, Manuel E. Acacio. 237-244 [doi]
- Special session on "Fault-tolerant techniques for computer systems, architectures and processors"Ioannis Sourdis. 245 [doi]
- on-Demand system reliability: The DeSyRe projectIoannis Sourdis. 246 [doi]
- Cobra: A comprehensive bundle-based reliable architectureAndrea Pellegrini, Valeria Bertacco. 247-254 [doi]
- On-demand thread-level fault detection in a concurrent programming environmentJian Fu, Qiang Yang 0006, Raphael Poss, Chris R. Jesshope, Chunyuan Zhang. 255-262 [doi]
- GPUburn: A system to test and mitigate GPU hardware failuresDavid Defour, Eric Petit. 263-270 [doi]
- Workload-dependent relative fault sensitivity and error contribution factor of GPU onchip memory structuresRonak Shah, Minsu Choi, Byunghyun Jang. 271-278 [doi]
- Special session on "Exposed data path architectures: Recent advances and applications"Jani Boutellier, Pekka Jääskeläinen. 279 [doi]
- Verilog-based simulation of hardware support for data-flow concurrency on multicore systemsGeorge Matheou, Paraskevas Evripidou. 280-287 [doi]
- Design of a unified transport triggered processor for LDPC/turbo decoderShahriar Shahabuddin, Janne Janhunen, Muhammet Fatih Bayramoglu, Markku J. Juntti, Amanullah Ghazi, Olli Silvén. 288-295 [doi]
- Exploiting tightly-coupled coresDaniel Bates, Alex Bradbury, Andreas Koltes, Robert Mullins. 296-305 [doi]
- FlexCore: Implementing an exposed datapath processorMagnus Själander, Per Larsson-Edefors. 306-313 [doi]
- Dataflow computing with Polymorphic RegistersCatalin Bogdan Ciobanu, Georgi Gaydadjiev, Christian Pilato, Donatella Sciuto. 314-321 [doi]
- OpenCL code generation for low energy wide SIMD architectures with explicit datapathDongrui She, Yifan He, Luc Waeijen, Henk Corporaal. 322-329 [doi]
- SIMD made explicitLuc Waeijen, Dongrui She, Henk Corporaal, Yifan He. 330-337 [doi]