Abstract is missing.
- Functional Fmax test-time reduction using novel DFTs for circuit initializationUjjwal Guin, Tapan J. Chakraborty, Mohammad Tehranipoor. 1-6 [doi]
- Phoenix NoC: A distributed fault tolerant architectureCésar A. M. Marcon, Alexandre M. Amory, Thais Webber, Thomas Volpato, Leticia B. Poehls. 7-12 [doi]
- Memory-centric accelerator design for Convolutional Neural NetworksMaurice Peemen, Arnaud A. A. Setio, Bart Mesman, Henk Corporaal. 13-19 [doi]
- Dynamic bandwidth adaptation using recognition accuracy prediction through pre-classification for embedded vision systemsYang Xiao, Chuanjun Zhang, Kevin Inck, Vijaykrishnan Narayanan. 20-25 [doi]
- Characterizing the costs and benefits of hardware parallelism in accelerator coresSteven J. Battle, Mark Hempstead. 26-32 [doi]
- High accuracy approximate multiplier with error correctionChia-Hao Lin, Ing-Chao Lin. 33-38 [doi]
- Exploiting correlation in stochastic circuit designArmin Alaghi, John P. Hayes. 39-46 [doi]
- Statistical analysis and modeling for error composition in approximate computation circuitsWei-Ting Jonas Chan, Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar 0002, John Sartori. 47-53 [doi]
- Dynamic thread mapping for high-performance, power-efficient heterogeneous many-core systemsGuangshuo Liu, Jinpyo Park, Diana Marculescu. 54-61 [doi]
- Energy-aware synthesis of application specific MPSoCsThannirmalai Somu Muthukaruppan, Haris Javaid, Tulika Mitra, Sri Parameswaran. 62-69 [doi]
- Long term sustainability of differentially reliable systems in the dark silicon eraJason M. Allred, Sanghamitra Roy, Koushik Chakraborty. 70-77 [doi]
- A global router on GPU architectureYiding Han, Koushik Chakraborty, Sanghamitra Roy. 78-84 [doi]
- A private level-1 cache architecture to exploit the latency and capacity tradeoffs in multicores operating at near-threshold voltagesFarrukh Hijaz, Qingchuan Shi, Omer Khan. 85-92 [doi]
- Power gating with block migration in chip-multiprocessor last-level cachesDavid Kadjo, HyungJun Kim, Paul Gratz, Jiang Hu, Raid Ayoub. 93-99 [doi]
- FlexiWay: A cache energy saving technique using fine-grained cache reconfigurationSparsh Mittal, Zhao Zhang, Jeffrey S. Vetter. 100-107 [doi]
- Register allocation and VDD-gating algorithms for out-of-order architecturesSteven J. Battle, Mark Hempstead. 108-114 [doi]
- LightTx: A lightweight transactional design in flash-based SSDs to support flexible transactionsYouyou Lu, Jiwu Shu, Jia Guo, Shuai Li, Onur Mutlu. 115-122 [doi]
- Program interference in MLC NAND flash memory: Characterization, modeling, and mitigationYu Cai, Onur Mutlu, Erich F. Haratsch, Ken Mai. 123-130 [doi]
- Low power multi-level-cell resistive memory design with incomplete data mappingDimin Niu, Qiaosha Zou, Cong Xu, Yuan Xie. 131-137 [doi]
- Lazy Precharge: An overhead-free method to reduce precharge overhead for memory parallelism improvement of DRAM systemTao Zhang, Cong Xu, Yuan Xie, Guangyu Sun. 138-144 [doi]
- Design tradeoffs for simplicity and efficient verification in the Execution Migration MachineKeun Sup Shim, Mieszko Lis, Myong Hyon Cho, Ilia A. Lebedev, Srinivas Devadas. 145-153 [doi]
- Rationale for a 3D heterogeneous multi-core processorEric Rotenberg, Brandon H. Dwiel, Elliott Forbes, Zhenqian Zhang, Randy Widialaksono, Rangeen Basu Roy Chowdhury, Nyunyi M. Tshibangu, Steve Lipa, W. Rhett Davis, Paul D. Franzon. 154-168 [doi]
- Accelerator-rich CMPs: From concept to real hardwareYu-Ting Chen, Jason Cong, Mohammad Ali Ghodrat, Muhuan Huang, Chunyue Liu, Bingjun Xiao, Yi Zou. 169-176 [doi]
- Scattered superpage: A case for bridging the gap between superpage and page coloringLicheng Chen, Yanan Wang, Zehan Cui, Yongbing Huang, Yungang Bao, Mingyu Chen. 177-184 [doi]
- Data compression for thermal mitigation in the Hybrid Memory CubeMushfique Junayed Khurshid, Mikko H. Lipasti. 185-192 [doi]
- Data placement in HPC architectures with heterogeneous off-chip memoryMilan Pavlovic, Nikola Puzovic, Alex Ramírez. 193-200 [doi]
- Managing test coverage uncertainty due to thermal noise in nano-CMOS: A case-study on an SRAM arrayVikram B. Suresh, Sandip Kundu. 201-206 [doi]
- Assessing the impact of hard faults in performance components of modern microprocessorsNikos Foutris, Dimitris Gizopoulos, John Kalamatianos, Vilas Sridharan. 207-214 [doi]
- Sneak path testing and fault modeling for multilevel memristor-based memoriesSachhidh Kannan, Ramesh Karri, Ozgur Sinanoglu. 215-220 [doi]
- Integrating thermocouple sensors into 3D ICsDawei Li, Ji-Hoon Kim, Seda Ogrenci Memik. 221-226 [doi]
- Gate delay modeling for pre- and post-silicon timing related tasks for ultra-low power CMOS circuitsPrasanjeet Das, Sandeep K. Gupta. 227-234 [doi]
- Noise-based algorithms for functional equivalence and tautology checkingPey-Chang Kent Lin, Sunil P. Khatri. 235-240 [doi]
- FastLanes: An FPGA accelerated GPU microarchitecture simulatorKuan Fang, Yufei Ni, Jiayuan He, Zonghui Li, Shuai Mu, Yangdong Deng. 241-248 [doi]
- Bayesian theory oriented Optimal Data-Provider Selection for CMPGuohong Li, Zhenyu Liu, Sanchuan Guo, Chongmin Li, Dongsheng Wang. 249-256 [doi]
- Selected inversion for vectorless power grid verification by exploiting localityJianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. 257-263 [doi]
- Energy-efficient Runtime Adaptive Scrubbing in fault-tolerant Network-on-Chips (NoCs) architecturesTravis Boraten, Avinash Kodi. 264-271 [doi]
- Efficient floating-point representation for balanced codes for FPGA devicesJulio Villalba, Javier Hormigo, Francisco Corbera, Mario A. González, Emilio L. Zapata. 272-277 [doi]
- Free ECC: An efficient error protection for compressed last-level cachesLong Chen, Yanan Cao, Zhao Zhang. 278-285 [doi]
- FreshCache: Statically and dynamically exploiting dataless waysArkaprava Basu, Derek Hower, Mark D. Hill, Michael M. Swift. 286-293 [doi]
- RECAP: Region-Aware Cache PartitioningKarthik T. Sundararajan, Timothy M. Jones, Nigel P. Topham. 294-301 [doi]
- Speculative tag access for reduced energy dissipation in set-associative L1 data cachesAlen Bardizbanyan, Magnus Själander, David B. Whalley, Per Larsson-Edefors. 302-308 [doi]
- Exploring the energy efficiency of Multispeculative AddersAlberto A. Del Barrio, Román Hermida, Seda Ogrenci Memik. 309-315 [doi]
- A temperature-aware synthesis approach for simultaneous delay and leakage optimizationNathaniel A. Conos, Miodrag Potkonjak. 316-321 [doi]
- A TCAM generator for packet classificationInfall Syafalni, Tsutomu Sasao. 322-328 [doi]
- Voltage scaling on C-elements: A speed, power and energy efficiency analysisMatheus Trevisan Moreira, Ney Laert Vilar Calazans. 329-334 [doi]
- Watts-inside: A hardware-software cooperative approach for Multicore Power DebuggingJie Chen 0020, Fan Yao, Guru Venkataramani. 335-342 [doi]
- Variation tolerance and error resilience in a low power wireless receiverJan Hoogerbrugge. 343-348 [doi]
- Power capping of CPU-GPU heterogeneous systems through coordinating DVFS and task mappingToshiya Komoda, Shingo Hayashi, Takashi Nakada, Shinobu Miwa, Hiroshi Nakamura. 349-356 [doi]
- Simulation and architecture improvements of atomic operations on GPU scratchpad memoryGert-Jan van den Braak, Juan Gómez-Luna, Henk Corporaal, José María González-Linares, Nicolas Guil. 357-362 [doi]
- Exploiting dynamic phase distance mapping for phase-based tuning of embedded systemsTosiron Adegbija, Ann Gordon-Ross. 363-368 [doi]
- Towards efficient dynamic data placement in NoC-based multicoresQingchuan Shi, Farrukh Hijaz, Omer Khan. 369-376 [doi]
- SLIDER: Smart Late Injection DEflection Router for mesh NoCsBhawna Nayak, John Jose, Madhu Mutyam. 377-383 [doi]
- Scalable trace signal selection using machine learningKamran Rahmani, Prabhat Mishra, Sandip Ray. 384-389 [doi]
- Selecting critical implications with set-covering formulation for SAT-based Bounded Model CheckingMahmoud Elbayoumi, Michael S. Hsiao, Mustafa Y. ElNainay. 390-395 [doi]
- Equivalence checking of partial designs using dependency quantified Boolean formulaeKarina Gitina, Sven Reimer, Matthias Sauer, Ralf Wimmer, Christoph Scholl, Bernd Becker. 396-403 [doi]
- Quipu: High-performance simulation of quantum circuits using stabilizer framesHéctor J. Garcia, Igor L. Markov. 404-410 [doi]
- Performance simulator based on hardware resources constraints for ion trap quantum computerMuhamamd Ahsan, Byung-Soo Choi, Jungsang Kim. 411-418 [doi]
- QuRE: The Quantum Resource Estimator toolboxMartin Suchara, John Kubiatowicz, Arvin I. Faruque, Frederic T. Chong, Ching-Yi Lai, Gerardo Paz. 419-426 [doi]
- Chisel-Q: Designing quantum circuits with a scala embedded languageXiao Liu, John Kubiatowicz. 427-434 [doi]
- Towards analyzing and improving robustness of software applications to intermittent and permanent faults in hardwareAnkur Sharma, Joseph Sloan, Lucas Francisco Wanner, Salma Elmalaki, Mani B. Srivastava, Puneet Gupta. 435-438 [doi]
- Compiler-based approach to reducing leakage energy of instruction scratch-pad memoriesYijie Huangfu, Wei Zhang. 439-442 [doi]
- Assessment of cloud-based health monitoring using Homomorphic EncryptionÖvünç Kocabas, Tolga Soyata, Jean-Philippe Couderc, Mehmet Aktas, Jean Xia, Michael C. Huang. 443-446 [doi]
- Semi-analytical current source modeling of near-threshold operating logic cells considering process variationsQing Xie, Tiansong Cui, Yanzhi Wang, Shahin Nazarian, Massoud Pedram. 447-450 [doi]
- Algorithm clustering for multi-algorithm processor designMadhushika M. E. Karunarathna, Yu-Chu Tian, Colin J. Fidge, Ross Hayward. 451-454 [doi]
- CG-Resync: Conversion-guided resynchronization for a SSD-based RAID arrayLetian Yi, Jiwu Shu, Jiaxin Ou, Weimin Zheng. 455-458 [doi]
- Analysis and minimization of short-circuit current in mesh clock networkSeongbo Shim, Minyoung Mo, Sangmin Kim, Youngsoo Shin. 459-462 [doi]
- LPScan: An algorithm for supply scaling and switching activity minimization during testSeetal Potluri, Satya Trinadh Adireddy, Chidhambaranathan Rajamanikkam, Shankar Balachandran. 463-466 [doi]
- JOP-alarm: Detecting jump-oriented programming-based anomalies in applicationsFan Yao, Jie Chen 0020, Guru Venkataramani. 467-470 [doi]
- On design vulnerability analysis and trust benchmarks developmentHassan Salmani, Mohammad Tehranipoor, Ramesh Karri. 471-474 [doi]
- Dynamic AC-scheduling for hardware cores with unknown and uncertain informationSilvia Lovergine, Fabrizio Ferrandi. 475-478 [doi]
- Resonant frequency divider design methodology for dynamic frequency scalingYing Teng, Baris Taskin. 479-482 [doi]
- Resource allocation algorithms for guaranteed service in application-specific NoCsGongming Yang, Hao He, Jiang Hu. 483-486 [doi]
- A low-jitter phase-locked resonant clock generation and distribution schemeAyan Mandal, Kalyana C. Bollapalli, Nikhil Jayakumar, Sunil P. Khatri, Rabi N. Mahapatra. 487-490 [doi]
- Equivalence checking for compiler transformations in behavioral synthesisZhenkun Yang, Kecheng Hao, Kai Cong, Sandip Ray, Fei Xie. 491-494 [doi]
- On dynamic polymorphing of a superscalar core for improving energy efficiencySudarshan Srinivasan, Rance Rodrigues, Arunachalam Annamalai, Israel Koren, Sandip Kundu. 495-498 [doi]
- Optimizing post-silicon conformance checkingLi Lei, Kai Cong, Fei Xie. 499-502 [doi]
- Increasing GPU throughput using kernel interleaved thread block schedulingMihir Awatramani, Joseph Zambreno, Diane T. Rover. 503-506 [doi]
- Stochastic functions using sequential logicNaman Saraf, Kia Bazargan, David J. Lilja, Marc D. Riedel. 507-510 [doi]
- Low-current probabilistic writes for power-efficient STT-RAM cachesNikolaos Strikos, Vasileios Kontorinis, Xiangyu Dong, Houman Homayoun, Dean M. Tullsen. 511-514 [doi]
- DR-SNUCA: An energy-scalable dynamically partitioned cacheAnshuman Gupta, Jack Sampson, Michael Bedford Taylor. 515-518 [doi]
- Performance-controllable shared cache architecture for multi-core soft real-time systemsMyoungjun Lee, Soontae Kim. 519-522 [doi]