Table of Contents

• MACAU: A Markov model for reliability evaluations of caches under Single-bit and Multi-bit UpsetsJinho Suh, Murali Annavaram, Michel Dubois. 3-14 [doi]
• Efficient scrub mechanisms for error-prone emerging memoriesManu Awasthi, Manjunath Shevgoor, Kshitij Sudan, Bipin Rajendran, Rajeev Balasubramonian, Viji Srinivasan. 15-26 [doi]
• Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chipsTimothy N. Miller, Xiang Pan, Renji Thomas, Naser Sedaghati, Radu Teodorescu. 27-38 [doi]
• Staged Reads: Mitigating the impact of DRAM writes on DRAM readsNiladrish Chatterjee, Naveen Muralimanohar, Rajeev Balasubramonian, Al Davis, Norman P. Jouppi. 41-52 [doi]
• Balancing DRAM locality and parallelism in shared memory CMP systemsMin Kyu Jeong, Doe Hyun Yoon, Dam Sunwoo, Mike Sullivan, Ikhwan Lee, Mattan Erez. 53-64 [doi]
• MORSE: Multi-objective reconfigurable self-optimizing memory schedulerJanani Mukundan, José F. Martínez. 65-76 [doi]
• The case for GPGPU spatial multitaskingJacob Adriaens, Katherine Compton, Nam Sung Kim, Michael J. Schulte. 79-90 [doi]
• TAP: A TLP-aware cache management policy for a CPU-GPU heterogeneous architectureJaekyu Lee, Hyesoon Kim. 91-102 [doi]
• CPU-assisted GPGPU on fused CPU-GPU architecturesYi Yang, Ping Xiang, Mike Mantor, Huiyang Zhou. 103-114 [doi]
• Design, integration and implementation of the DySER hardware accelerator into OpenSPARCJesse Benson, Ryan Cofell, Chris Frericks, Chen-Han Ho, Venkatraman Govindaraju, Tony Nowatzki, Karthikeyan Sankaralingam. 115-126 [doi]
• SCD: A scalable coherence directory with flexible sharer set encodingDaniel Sanchez, Christos Kozyrakis. 129-140 [doi]
• π-TM: Pessimistic invalidation for scalable lazy hardware transactional memoryAnurag Negi, J. Rubén Titos Gil, Manuel E. Acacio, José M. García, Per Stenström. 141-152 [doi]
• BulkSMT: Designing SMT processors for atomic-block executionXuehai Qian, Benjamin Sahelices, Josep Torrellas. 153-164 [doi]
• Supporting efficient collective communication in NoCsSheng Ma, Natalie D. Enright Jerger, Zhiying Wang. 165-176 [doi]
• Quasi-nonvolatile SSD: Trading flash memory nonvolatility to improve storage system performance for enterprise applicationsYangyang Pan, Guiqiang Dong, Qi Wu, Tong Zhang 0002. 179-188 [doi]
• System-level implications of disaggregated memoryKevin T. Lim, Yoshio Turner, Jose Renato Santos, Alvin AuYoung, Jichuan Chang, Parthasarathy Ranganathan, Thomas F. Wenisch. 189-200 [doi]
• Improving write operations in MLC phase change memoryLei Jiang, Bo Zhao, Youtao Zhang, Jun Yang 0002, Bruce R. Childers. 201-210 [doi]
• Adaptive Set-Granular Cooperative CachingDyer Rolán, Basilio B. Fraguela, Ramon Doallo. 213-224 [doi]
• Cache restoration for highly partitioned virtualized systemsDavid Daly, Harold W. Cain. 225-234 [doi]
• Decoupled dynamic cache segmentationSamira Manabi Khan, Zhe Wang, Daniel A. Jiménez. 235-246 [doi]
• Computational sprintingArun Raghavan, Yixin Luo, Anuj Chandawalla, Marios C. Papaefthymiou, Kevin P. Pipe, Thomas F. Wenisch, Milo M. K. Martin. 249-260 [doi]
• Power balanced pipelinesJohn Sartori, Ben Ahrens, Rakesh Kumar. 261-272 [doi]
• Flexible register management using reference countingSteven Battle, Andrew D. Hilton, Mark Hempstead, Amir Roth. 273-284 [doi]
• AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architectureGuihai Yan, Yingmin Li, Yinhe Han, Xiaowei Li 0001, Minyi Guo, Xiaoyao Liang. 287-298 [doi]
• JETC: Joint energy thermal and cooling management for memory and CPU subsystems in serversRaid Zuhair Ayoub, Rajib Nath, Tajana Rosing. 299-310 [doi]
• Cooperative partitioning: Energy-efficient cache partitioning for high-performance CMPsKarthik T. Sundararajan, Vasileios Porpodas, Timothy M. Jones, Nigel P. Topham, Björn Franke. 311-322 [doi]
• Dynamically heterogeneous cores through 3D resource poolingHouman Homayoun, Vasileios Kontorinis, Amirali Shayan, Ta-Wei Lin, Dean M. Tullsen. 323-334 [doi]
• Architectural support for synchronization-free deterministic parallel programmingCedomir Segulja, Tarek S. Abdelrahman. 337-348 [doi]
• Pacman: Tolerating asymmetric data races with unintrusive hardwareShanxiang Qi, Norimasa Otsuki, Lois Orosa Nogueira, Abdullah Muzahid, Josep Torrellas. 349-360 [doi]
• BulkCompactor: Optimized deterministic execution via Conflict-Aware commit of atomic blocksYuelu Duan, Xing Zhou, Wonsun Ahn, Josep Torrellas. 361-372 [doi]
• Parabix: Boosting the efficiency of text processing on commodity processorsDan Lin 0003, Nigel Medforth, Kenneth S. Herdy, Arrvindh Shriraman, Robert D. Cameron. 373-384 [doi]
• WEST: Cloning data cache behavior using Stochastic TracesGanesh Balakrishnan, Yan Solihin. 387-398 [doi]
• Statistical performance comparisons of computersTianshi Chen, Yunji Chen, Qi Guo, Olivier Temam, Yue Wu, Weiwu Hu. 399-410 [doi]
• Accelerating business analytics applicationsValentina Salapura, Tejas Karkhanis, Priya Nagpurkar, José E. Moreira. 413-422 [doi]
• Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processorAugusto Vega, Pradip Bose, Alper Buyuktosunoglu, Jeff H. Derby, Michele Franceschini, Charles Johnson, Robert K. Montoye. 423-432 [doi]
• QuickIA: Exploring heterogeneous architectures on real prototypesNagabhushan Chitlur, Ganapati Srinivasa, Scott Hahn, P. K. Gupta, Dheeraj Reddy, David A. Koufaty, Paul Brett, Abirami Prabhakaran, Li Zhao, Nelson Ijih, Suchit Subhaschandra, Sabina Grover, Xiaowei Jiang, Ravi Iyer. 433-440 [doi]
• Network congestion avoidance through Speculative ReservationNan Jiang, Daniel U. Becker, George Michelogiannakis, William J. Dally. 443-454 [doi]
• Network within a network approach to create a scalable high-radix router microarchitectureJung Ho Ahn, Sungwoo Choo, John Kim. 455-466 [doi]
• Whole packet forwarding: Efficient design of fully adaptive routing algorithms for networks-on-chipSheng Ma, Natalie D. Enright Jerger, Zhiying Wang. 467-478 [doi]