Table of Contents

• Towards Efficient Neural Network Model Parallelism on Multi-FPGA PlatformsDavid Rodriguez, Rafael Tornero, José Flich. 1-6 [doi]
• Security Evaluation of a Hybrid CMOS/MRAM Ascon Hardware ImplementationNathan Roussel, Olivier Potin, Jean-Max Dutertre, Jean-Baptiste Rigaud. 1-6 [doi]
• Accurate yet Efficient Stochastic Computing Neural Acceleration with High Precision Residual FusionYixuan Hu, Tengyu Zhang, Renjie Wei, Meng Li, Runsheng Wang, Yuan Wang 0001, Ru Huang. 1-6 [doi]
• Energy-efficient Wearable-to-Mobile Offload of ML Inference for PPG-based Heart-Rate EstimationAlessio Burrello, Matteo Risso, Noemi Tomasello, Yukai Chen, Luca Benini, Enrico Macii, Massimo Poncino, Daniele Jahier Pagliari. 1-6 [doi]
• A Safety-Guaranteed Framework for Neural-Network-Based Planners in Connected Vehicles under Communication DisturbanceKevin Kai-Chun Chang, Xiangguo Liu, Chung-Wei Lin, Chao Huang 0015, Qi Zhu 0002. 1-6 [doi]
• MANTIS: Machine Learning-Based Approximate ModeliNg of RedacTed Integrated CircuitSChaitali Sathe, Yiorgos Makris, Benjamin Carrion Schafer. 1-6 [doi]
• Efficient Parallelization of 5G-PUSCH on a Scalable RISC-V Many-Core ProcessorMarco Bertuletti, Yichao Zhang, Alessandro Vanelli-Coralli, Luca Benini. 1-6 [doi]
• MA-Opt: Reinforcement Learning-based Analog Circuit Optimization using Multi-ActorsYoungchang Choi, Minjeong Choi, Kyongsu Lee, Seokhyeong Kang. 1-5 [doi]
• TBERT: Dynamic BERT Inference with Top-k Based PredictorsZejian Liu, Kun Zhao, Jian Cheng 0001. 1-6 [doi]
• DEL: Dynamic Symbolic Execution-based Lifter for Enhanced Low-Level Intermediate RepresentationHany Abdelmaksoud, Zain Alabedin Haj Hammadeh, Görschwin Fey, Daniel Lüdtke. 1-2 [doi]
• Minimizing Communication Conflicts in Network-On-Chip Based Processing-In-Memory ArchitectureHanbo Sun, Tongxin Xie, Zhenhua Zhu, Guohao Dai, Huazhong Yang, Yu Wang 0002. 1-6 [doi]
• RankSearch: An Automatic Rank Search Towards Optimal Tensor Compression for Video LSTM Networks on EdgeChanghai Man, Cheng Chang, Chenchen Ding, Ao Shen, Hongwei Ren, Ziyi Guan, Yuan Cheng, Shaobo Luo, Rumin Zhang, Ngai Wong, Hao Yu 0001. 1-2 [doi]
• Fast and Accurate Wire Timing Estimation Based on Graph LearningYuyang Ye, Tinghuan Chen, Yifei Gao, Hao Yan, Bei Yu 0001, Longxing Shi. 1-6 [doi]
• The Next Era for Chiplet InnovationGabriel H. Loh, Raja Swaminathan. 1-6 [doi]
• Securing Heterogeneous 2.5D ICs Against IP Theft through Dynamic Interposer ObfuscationJonti Talukdar, Arjun Chaudhuri, Jinwoo Kim, Sung Kyu Lim, Krishnendu Chakrabarty. 1-2 [doi]
• STAR: An Efficient Softmax Engine for Attention Model with RRAM CrossbarYifeng Zhai, Bing Li, Bonan Yan, Jing Wang. 1-2 [doi]
• Exact Synthesis Based on Semi-Tensor Product Circuit SolverHongyang Pan, Zhufei Chu. 1-6 [doi]
• Efficient Hyperdimensional Learning with Trainable, Quantizable, and Holistic Data RepresentationJiseung Kim 0005, Hyunsei Lee, Mohsen Imani, Yeseong Kim. 1-6 [doi]
• Motivating Agent-Based Learning for Bounding Time in Mixed-Criticality SystemsBehnaz Ranjbar, Ali Hosseinghorban, Akash Kumar 0001. 1-2 [doi]
• Co-Design of Topology, Scheduling, and Path Planning in Automated WarehousesChristopher Leet, Chanwook Oh, Michele Lora, Sven Koenig, Pierluigi Nuzzo 0002. 1-6 [doi]
• End-to-End Optimization of High-Density e-Skin Design: From Spiking Taxel Readout to Texture ClassificationJiaqi Wang, Mark Daniel Alea, Jonah Van Assche, Georges G. E. Gielen. 1-6 [doi]
• Cross Layer Design for the Predictive Assessment of Technology-Enabled ArchitecturesMichael T. Niemier, X. S. Hu, L. Liu, Mohammad Mehdi Sharifi, Ian O'Connor, David Atienza, Giovanni Ansaloni, Can Li, Asif Khan, Daniel C. Ralph. 1-10 [doi]
• Memristor-Spikelearn: A Spiking Neural Network Simulator for Studying Synaptic Plasticity under Realistic Device and Circuit BehaviorsYuming Liu, Angel Yanguas-Gil, Sandeep Madireddy, Yanjing Li. 1-6 [doi]
• Table Re-Computation Based Low Entropy Inner Product Masking SchemeJingdian Ming, Yongbin Zhou, Wei Cheng 0003, Huizhong Li. 1-6 [doi]
• AI-Based Detection of Droplets and Bubbles in Digital Microfluidic BiochipsJianan Xu, Wenjie Fan, Jan Madsen, Georgi Plamenov Tanev, Luca Pezzarossa. 1-6 [doi]
• Adversarial Attack on Hyperdimensional Computing-based NLP ApplicationsSizhe Zhang, Zhao Wang, Xun Jiao. 1-6 [doi]
• Scalable Coherent Optical Crossbar Architecture using PCM for AI AccelerationDaniel Sturm 0003, Sajjad Moazeni. 1-6 [doi]
• PetaOps/W edge-AI $\mu$ Processors: Myth or reality?Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal. 1-6 [doi]
• Towards Smart Cattle Farms: Automated Inspection of Cattle Health with Real-Life DataYigit Tuncel, Toygun Basaklar, Mackenzie Smithyman, João Dórea, Vinícius Nunes De Gouvêa, Younghyun Kim 0001, Ümit Y. Ogras. 1-2 [doi]
• An Automated Verification Framework for HalideIR-Based Compiler TransformationsYanzhao Wang, Fei Xie, Zhenkun Yang, Jeremy Casas, Pasquale Cocchini, Jin Yang 0006. 1-6 [doi]
• Light Flash Write for Efficient Firmware Update on Energy-harvesting IoT DevicesSongran Liu, Mingsong Lv, Wei Zhang 0173, Xu Jiang, Chuancai Gu, Tao Yang, Wang Yi 0001, Nan Guan. 1-6 [doi]
• Class-based Quantization for Neural NetworksWenhao Sun, Grace Li Zhang, Huaxi Gu, Bing Li 0005, Ulf Schlichtmann. 1-6 [doi]
• Efficient Design Rule Checking with GPU AccelerationWei Zhong, Zhenhua Feng, Zhuolun He, Weimin Wang, Yuzhe Ma, Bei Yu 0001. 1-2 [doi]
• CLAP: Locality Aware and Parallel Triangle Counting with Content Addressable MemoryTianyu Fu 0004, Chiyue Wei, Zhenhua Zhu, Shang Yang, Zhongming Yu, Guohao Dai, Huazhong Yang, Yu Wang 0002. 1-6 [doi]
• Twin ECC: A Data Duplication Based ECC for Strong DRAM Error ResilienceHyeong Kon Bae, Myung Jae Chung, Young-Ho Gong, Sung Woo Chung. 1-6 [doi]
• Towards Deep Learning-based Occupancy Detection Via WiFi Sensing in Unconstrained EnvironmentsCristian Turetta, Geri Skenderi, Luigi Capogrosso, Florenc Demrozi, Philipp H. Kindt, Alejandro Masrur, Franco Fummi, Marco Cristani, Graziano Pravadelli. 1-6 [doi]
• Hardware Efficient Weight-Binarized Spiking Neural NetworksChengcheng Tang, Jie Han 0001. 1-6 [doi]
• Evaluation of heterogeneous AIoT Accelerators within VEDLIoTRené Griessl, Florian Porrmann, Nils Kucza, Kevin Mika, Jens Hagemeyer, Martin Kaiser, Mario Porrmann, Marco Tassemeier, Marcel Flottmann, Fareed Qararyah, Muhammad Waqar Azhar, Pedro Trancoso, Daniel Ödman, Karol Gugala, Grzegorz Latosinski. 1-6 [doi]
• High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS TechnologyAibin Yan, Zhen Zhou, Liang Ding, Jie Cui 0004, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001. 1-2 [doi]
• The ZuSE-KI-Mobil AI Accelerator SoC: Overview and a Functional Safety PerspectiveFabian Kempf, Julian Höfer, Tanja Harbaum, Jürgen Becker 0001, Nael Fasfous, Alexander Frickenstein, Hans-Jörg Vögel, Simon Friedrich, Robert Wittig, Emil Matús, Gerhard P. Fettweis, Matthias Lüders, Holger Blume, Jens Benndorf, Darius Grantz, Martin Zeller, Dietmar Engelke, Karl-Heinz Eickel. 1-6 [doi]
• Smart Knowledge Transfer-based Runtime Power ManagementLin Chen, Xiao Li, Fan Jiang, Chengeng Li, Jiang Xu 0001. 1-6 [doi]
• Multiphysics Design and Simulation Methodology for Dense WDM Silicon PhotonicsJinsung Youn, Luca Ramini, Zeqin Lu, Ahsan Alam, James Pond, Marco Fiorentino, Raymond G. Beausoleil. 1-2 [doi]
• Pruning and Early-Exit Co-Optimization for CNN Acceleration on FPGAsGuilherme Korol, Michael Guilherme Jordan, Mateus Beck Rutzig, Jerónimo Castrillón, Antonio Carlos Schneider Beck. 1-6 [doi]
• Split Additive Manufacturing for Printed Neuromorphic CircuitsHaibin Zhao, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. 1-6 [doi]
• Low-Throughput Event-Based Image Sensors and ProcessingLaurent Fesquet, Rosalie Tran, Xavier Lesage, Mohamed Akrarai, Stéphane Mancini, Gilles Sicard. 1-6 [doi]
• PIC-RAM: Process-Invariant Capacitive Multiplier Based Analog In Memory Computing in 6T SRAMKailash Prasad, Aditya Biswas, Arpita Kabra, Joycee Mekie. 1-6 [doi]
• Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down ApproachDewmini Sudara Marakkalage, Giovanni De Micheli. 1-6 [doi]
• SparseMEM: Energy-efficient Design for In-memory Sparse-based Graph ProcessingMahdi Zahedi, Geert Custers, Taha Shahroodi, Georgi Gaydadjiev, Stephan Wong, Said Hamdioui. 1-6 [doi]
• MARB: Bridge the Semantic Gap between Operating System and Application Memory Access BehaviorHaifeng Li, Ke Liu 0004, Ting Liang, Zuojun Li, Tianyue Lu, Yisong Chang, Hui Yuan, Yinben Xia, Yungang Bao, Mingyu Chen 0001, Yizhou Shan. 1-6 [doi]
• Phalanx: Failure-Resilient Truck Platooning SystemChangjin Koo, Jaegeun Park, Taewook Ahn, Hongsuk Kim, Jong Chan Kim, Yongsoon Eun. 1-6 [doi]
• ViX: Analysis-driven Compiler for Efficient Low-Precision Variational InferenceAshitabh Misra, Jacob Laurel, Sasa Misailovic. 1-6 [doi]
• Chameleon: Dual Memory Replay for Online Continual Learning on Edge DevicesShivam Aggarwal, Kuluhan Binici, Tulika Mitra. 1-6 [doi]
• Autonomy-driven Emerging Directions in Software-defined VehiclesUnmesh D. Bordoloi, Samarjit Chakraborty, Markus Jochim, Prachi Joshi, Arvind Raghuraman, S. Ramesh. 1-6 [doi]
• Temperature-Aware Sizing of Multi-Chip Module Accelerators for Multi-DNN WorkloadsPrachi Shukla, Derrick Aguren, Tom Burd, Ayse K. Coskun, John Kalamatianos. 1-6 [doi]
• OverlaPIM: Overlap Optimization for Processing In-Memory Neural Network AccelerationMinxuan Zhou, Xuan Wang, Tajana Rosing. 1-6 [doi]
• Brain-Inspired Spatiotemporal Processing Algorithms for Efficient Event-Based PerceptionBiswadeep Chakraborty, Uday Kamal, Xueyuan She, Saurabh Dash, Saibal Mukhopadhyay. 1-6 [doi]
• Resource Optimization with 5G Configured Grant Scheduling for Real-Time ApplicationsYungang Pan, Rouhollah Mahfouzi, Soheil Samii, Petru Eles, Zebo Peng. 1-2 [doi]
• An Ultra-Low-Power Serial Implementation for Sigmoid and Tanh Using CORDIC AlgorithmYaoxing Chang, Petar Jokic, Stéphane Emery, Luca Benini. 1-2 [doi]
• SteppingNet: A Stepping Neural Network with Incremental Accuracy EnhancementWenhao Sun, Grace Li Zhang, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Bing Li 0005, Ulf Schlichtmann. 1-6 [doi]
• HERMES: qualification of High pErformance pRogrammable Microprocessor and dEvelopment of Software ecosystemNadia Ibellaatti, Edouard Lepape, Alp Kiliç, Kaya Akyel, Kassem Chouayakh, Fabrizio Ferrandi, Claudio Barone, Serena Curzel, Michele Fiorito, Giovanni Gozzi, Miguel Masmano, Ana Risquez Navarro, Manuel Muñoz, Vicente Nicolau Gallego, Patricia López Cueva, Jean-noel Letrillard, Franck Wartel. 1-5 [doi]
• Butterfly Effect Attack: Tiny and Seemingly Unrelated Perturbations for Object DetectionNguyen Anh Vu Doan, Arda Yüksel, Chih-Hong Cheng. 1-6 [doi]
• ArrayFlex: A Systolic Array Architecture with Configurable Transparent PipeliningChristodoulos Peltekis, Dionysios Filippas, Giorgos Dimitrakopoulos, Chrysostomos Nicopoulos, Dionisios N. Pnevmatikatos. 1-6 [doi]
• An Effective and Efficient Heuristic for Rational-Weight Threshold Logic Gate IdentificationTing-Yu Yeh, Yueh Cho, Yung-Chih Chen. 1-6 [doi]
• Polyglot Modal Models through Lingua FrancaAlexander Schulz-Rosengarten, Reinhard von Hanxleden, Marten Lohstroh, Soroush Bateni, Edward A. Lee. 1-2 [doi]
• Formal Analysis of Timing Diversity for Autonomous SystemsAnika Christmann, Robin Hapka, Rolf Ernst. 1-6 [doi]
• SERICO: Scheduling Real-Time I/O Requests in Computational Storage DrivesYun Huang, Nan Guan, Shuhan Bai, Tei-Wei Kuo, Chun Jason Xue. 1-6 [doi]
• BAFFI: a bit-accurate fault injector for improved dependability assessment of FPGA prototypesIlya Tuzov, David de Andrés, Juan-Carlos Ruiz-Garcia, Carles Hernández. 1-6 [doi]
• Mobile Accelerator Exploiting Sparsity of Multi-Heads, Lines, and Blocks in Transformers in Computer VisionEunji Kwon, Haena Song, Jihye Park, Seokhyeong Kang. 1-6 [doi]
• Out-of-Step Pipeline for Gather/Scatter InstructionsYi Ge, Katsuhiro Yoda, Makiko Ito, Toshiyuki Ichiba, Takahide Yoshikawa, Ryota Shioya, Masahiro Goshima. 1-2 [doi]
• SIGFuzz: A Framework for Discovering Microarchitectural Timing Side ChannelsChathura Rajapaksha, Leila Delshadtehrani, Manuel Egele, Ajay Joshi. 1-6 [doi]
• Developing an Ultra-low Power RISC-V Processor for Anomaly DetectionJina Park, Eunjin Choi, Kyungwon Lee, Jae-Jin Lee, Kyuseung Han, Woojoo Lee. 1-2 [doi]
• A Coupled Battery State-of-Charge and Voltage Model for Optimal Control ApplicationsMasoomeh Karami, Sajad Shahsavari, Eero Immonen, M. Hashem Haghbayan, Juha Plosila. 1-2 [doi]
• AGDM: An Adaptive Granularity Data Migration Strategy for Hybrid Memory SystemsZhouxuan Peng, Dan Feng 0001, Jianxi Chen, Jing Hu, Chuang Huang. 1-6 [doi]
• Minimum Unit Capacitance Calculation for Binary-Weighted Capacitor ArraysNibedita Karmokar, Ramesh Harjani, Sachin S. Sapatnekar. 1-2 [doi]
• Electromigration-aware design technology co-optimization for SRAM in advanced technology nodesMahta Mayahinia, Hsiao-Hsuan Liu, Subrat Mishra, Zsolt Tokei, Francky Catthoor, Mehdi B. Tahoori. 1-6 [doi]
• PEDAL: A Power Efficient GCN Accelerator with Multiple DAtafLowsYuhan Chen, Alireza Khadem, Xin He, Nishil Talati, Tanvir Ahmed Khan, Trevor N. Mudge. 1-6 [doi]
• Device-Aware Test for Back-Hopping Defects in STT-MRAMsSicong Yuan, Mottaqiallah Taouil, Moritz Fieback, Hanzhi Xun, Erik Jan Marinissen, Gouri Sankar Kar, Sidharth Rao, Sebastien Couet, Said Hamdioui. 1-6 [doi]
• Hardware and Software Support for Mixed Precision Computing: a Roadmap for Embedded and HPC SystemsWilliam Fornaciari, Giovanni Agosta, Daniele Cattaneo 0002, Lev Denisov, Andrea Galimberti, Gabriele Magnani, Davide Zoni. 1-6 [doi]
• Process Variation Resilient Current-Domain Analog In Memory ComputingKailash Prasad, Sai Shubham, Aditya Biswas, Joycee Mekie. 1-2 [doi]
• Automated Energy-Efficient DNN Compression under Fine-Grain Accuracy ConstraintsOurania Spantidi, Iraklis Anagnostopoulos. 1-6 [doi]
• Warm-Boot Attack on Modern DRAMsYichen Jiang, Shuo Wang, Renato Figueiredo, Yier Jin. 1-2 [doi]
• Towards High-Level Synthesis of Quantum CircuitsChao Lu, Christian Pilato, Kanad Basu. 1-6 [doi]
• Reinforcement-Learning-Based Job-Shop Scheduling for Intelligent Intersection ManagementShao-Ching Huang, Kai-En Lin, Cheng-Yen Kuo, Li-Heng Lin, Muhammed O. Sayin, Chung-Wei Lin. 1-6 [doi]
• The Post-pandemic Effects on IoT for Safety: The Safe Place ProjectFederico Cunico, Luigi Capogrosso, Alberto Castellini, Francesco Setti, Patrik Pluchino, Filippo Zordan, Valeria Santus, Anna Spagnolli, Stefano Cordibella, Giambattista Gennari, Mauro Borgo, Alberto Sozza, Stefano Troiano, Roberto Flor, Andrea Zanella, Alessandro Farinelli, Luciano Gamberini, Marco Cristani. 1-4 [doi]
• CEST: Computation-Efficient N:M Sparse Training for Deep Neural NetworksChao Fang, Wei Sun, Aojun Zhou, Zhongfeng Wang 0001. 1-2 [doi]
• Ditty: Directory-based Cache Coherence for Multicore Safety-critical SystemsZhuanhao Wu, Marat Bekmyrza, Nachiket Kapre, Hiren Patel. 1-6 [doi]
• The First Concept and Real-world Deployment of a GPU-based Thermal Covert Channel: Attack and CountermeasuresJeferson González-Gómez, Kevin Cordero-Zuñiga, Lars Bauer, Jörg Henkel. 1-6 [doi]
• Design Enablement Flow for Circuits with Inherent Obfuscation based on Reconfigurable TransistorsJens Trommer, N. Bhattacharjee, Thomas Mikolajick, S. Huhn, Marcel Merten, M. E. Djeridane, Muhammad Hassan 0002, Rolf Drechsler, S. Rai, N. Kavand, A. Darjani, A. Kumar, V. Sessi, M. Drescher, S. Kolodinski, M. Wiatr. 1-6 [doi]
• The SERRANO platform: Stepping towards seamless application development & deployment in the heterogeneous edge-cloud continuumAggelos Ferikoglou, Argyris Kokkinis, Dimitrios Danopoulos, Ioannis Oroutzoglou, Anastassios Nanos, Stathis Karanastasis, Márton Sipos, Javad Fadaie Ghotbi, Juan Jose Vegas Olmos, Dimosthenis Masouros, Kostas Siozios. 1-4 [doi]
• TURBULENCE: Complexity-effective Out-of-order Execution on GPU with Distance-based ISAReoma Matsuo, Toru Koizumi 0001, Hidetsugu Irie, Shuichi Sakai, Ryota Shioya. 1-2 [doi]
• Automated and Agile Design of Layout Hotspot Detector via Neural Architecture SearchZihao Chen, Fan Yang 0001, Li Shang, Xuan Zeng 0001. 1-6 [doi]
• EuFRATE: European FPGA Radiation-hardened Architecture for TelecommunicationsLudovica Bozzoli, Antonino Catanese, Emilio Fazzoletto, Eugenio Scarpa, Diana Goehringer, Sergio A. Pertuz, Lester Kalms, Cornelia Wulf, Najdet Charaf, Luca Sterpone, Sarah Azimi, Daniele Rizzieri, Salvatore Gabriele La Greca, David Merodio Codinachs, Stephen King. 1-6 [doi]
• Neural Network on the Edge: Efficient and Low Cost FPGA Implementation of Digital Predistortion in MIMO SystemsYiyue Jiang, Andrius Vaicaitis, Miriam Leeser, John Dooley. 1-2 [doi]
• SAT-Based Quantum Circuit AdaptationSebastian Brandhofer, Jinwoong Kim, Siyuan Niu, Nicholas T. Bronn. 1-6 [doi]
• Lightspeed Binary Neural Networks using Optical Phase-Change MaterialsTaha Shahroodi, Raphael Cardoso, Mahdi Zahedi, Stephan Wong, Alberto Bosio, Ian O'Connor, Said Hamdioui. 1-2 [doi]
• Non-Profiled Side-Channel Assisted Fault Attack: A Case Study on DOMREPSayandeep Saha, Prasanna Ravi, Dirmanto Jap, Shivam Bhasin. 1-6 [doi]
• On the Degree of Parallelism in Real-Time Scheduling of DAG TasksQingqiang He, Nan Guan, Mingsong Lv, Zonghua Gu 0001. 1-6 [doi]
• Efficient Approximation of Performance Spaces for Analog Circuits via Multi-Objective OptimizationBenedikt Ohse, David Schreiber, Jürgen Kampe, Christopher Schneider. 1-6 [doi]
• Time Series-based Driving Event Recognition for Two WheelersSai Usha Nagasri Goparaju, L. Lakshmanan, Abhinav Navnit, Rahul B, Lovish B, Deepak Gangadharan, Aftab M. Hussain. 1-2 [doi]
• Out-of-channel data placement for balancing wear-out and I/O workloads in RAID-enabled SSDsFan Yang, Chengqi Xiao, Jun Li 0062, Zhibing Sha, Zhigang Cai, Jianwei Liao. 1-6 [doi]
• An Efficient Fault Injection Algorithm for Identifying Unimportant FFs in Approximate Computing CircuitsJiaxuan Lu, Yutaka Masuda, Tohru Ishihara. 1-2 [doi]
• Energy-efficient NTT Design with One-bank SRAM and 2-D PE ArrayJianan Mu, Huajie Tan, Jiawen Wu, Haotian Lu, Chip-Hong Chang, Shuai Chen, Shengwen Liang, Jing Ye 0001, Huawei Li 0001, Xiaowei Li 0001. 1-2 [doi]
• Structural Generation of Virtual Prototypes for Smart Sensor Development in SystemC-AMS from Simulink ModelsAlexandra Küster, Rainer Dorsch, Christian Haubelt. 1-2 [doi]
• Dynamic Refinement of Hardware Assertion CheckersHasini Witharana, Sahan Sanjaya, Prabhat Mishra 0001. 1-6 [doi]
• TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-NodesSeyed Ahmad Mirsalari, Giuseppe Tagliavini, Davide Rossi, Luca Benini. 1-2 [doi]
• Two-stage PCB Routing Using Polygon-based Dynamic Partitioning and MCTSYoubiao He, Hebi Li, Ge Luo 0002, Forrest Sheng Bao. 1-2 [doi]
• TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC OperationJinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao, Yue Zhang. 1-6 [doi]
• Highly-Bespoke Robust Printed Neuromorphic CircuitsHaibin Zhao, Brojogopal Sapui, Michael Hefenbrock, Zhidong Yang, Michael Beigl, Mehdi B. Tahoori. 1-6 [doi]
• Fully On-board Low-Power Localization with Multizone Time-of-Flight Sensors on Nano-UAVsHanna Müller, Nicky Zimmerman, Tommaso Polonelli, Michele Magno, Jens Behley, Cyrill Stachniss, Luca Benini. 1-6 [doi]
• Exploiting Short Application Lifetimes for Low Cost Hardware Encryption in Flexible ElectronicsNathaniel Bleier, Muhammad Husnain Mubarik, Suman Balaji, Francisco Rodriguez, Antony Sou, Scott White, Rakesh Kumar 0002. 1-6 [doi]
• FSL-HD: Accelerating Few-Shot Learning on ReRAM using Hyperdimensional ComputingWeihong Xu, Jaeyoung Kang 0001, Tajana Rosing. 1-6 [doi]
• SCFI: State Machine Control-Flow Hardening Against Fault AttacksPascal Nasahl, Martin Unterguggenberger, Rishub Nagpal, Robert Schilling, David Schrammel, Stefan Mangard. 1-6 [doi]
• 2lowSim: System-Level Simulator of eFlash-Based Compute-in-Memory Accelerators for Convolutional Neural NetworksJooho Wang, Sunwoo Kim 0002, Junsu Heo, Chester Sungchung Park. 1-6 [doi]
• Accelerating Gustavson-based SpMM on Embedded FPGAs with Element-wise Parallelism and Access Pattern-aware CachesShiqing Li, Weichen Liu. 1-6 [doi]
• Atomic but Lazy Updating with Memory-mapped Files for Persistent MemoryQisheng Jiang, Lei Jia, Chundong Wang 0001. 1-6 [doi]
• Extending the Design Space of Dynamic Quantum Circuits for Toffoli based NetworkAbhoy Kole, Arighna Deb, Kamalika Datta, Rolf Drechsler. 1-6 [doi]
• MIRROR: MaxImizing the Re-usability of RTL thrOugh RTL to C CompileRMd. Imtiaz Rashid, Benjamin Carrion Schafer. 1-6 [doi]
• VE-FIDES: Designing Trustworthy Supply Chains Using Innovative Fingerprinting ImplementationsBernhard Lippmann, Joel Hatsch, Stefan Seidl, Detlef Houdeau, Niranjana Papagudi Subrahmanyam, Daniel Schneider, Malek Safieh, Anne Passarelli, Aliza Maftun, Michaela Brunner, Tim Music, Michael Pehl, Tauseef Siddiqui, Ralf Brederlow, Ulf Schlichtmann, Bjoern Driemeyer, Maurits Ortmanns, Robert Hesselbarth, Matthias Hiller. 1-6 [doi]
• Optimizing Data Migration for Garbage Collection in ZNS SSDsZhenhua Tan, Linbo Long, Renping Liu, Congming Gao, Yi Jiang, Yan Liu. 1-2 [doi]
• The CNN vs. SNN Event-camera Dichotomy and Perspectives For Event-Graph Neural NetworksThomas Dalgaty, Thomas Mesquida, Damien Joubert, Amos Sironi, Cyrille Soubeyrat, Pascal Vivet, Christoph Posch. 1-6 [doi]
• Equivalence Checking of System-Level and SPICE-Level Models of Static Nonlinear CircuitsKemal Çaglar Coskun, Muhammad Hassan 0002, Rolf Drechsler. 1-6 [doi]
• A Rapid Reset 8-Transistor Physically Unclonable Function Utilising Power GatingYujin Zheng, Alex Bystrov, Alex Yakovlev. 1-2 [doi]
• Genetic Algorithm-based Framework for Layer-Fused Scheduling of Multiple DNNs on Multi-core SystemsSebastian Karl, Arne Symons, Nael Fasfous, Marian Verhelst. 1-6 [doi]
• Energy-Efficient Bayesian Inference Using Near-Memory Computation with MemristorsClement Türck, Kamel-Eddine Harabi, Tifenn Hirtzlin, Elisa Vianello, Raphaël Laurent, Jacques Droulez, Pierre Bessière, Marc Bocquet, Jean Michel Portal, Damien Querlioz. 1-2 [doi]
• PR-ESP: An Open-Source Platform for Design and Programming of Partially Reconfigurable SoCsBiruk B. Seyoum, Davide Giri, Kuan-Lin Chiu, Bryce Natter, Luca P. Carloni. 1-6 [doi]
• MAVFI: An End-to-End Fault Analysis Framework with Anomaly Detection and Recovery for Micro Aerial VehiclesYu-Shun Hsiao, Zishen Wan, Tianyu Jia, Radhika Ghosal, Abdulrahman Mahmoud, Arijit Raychowdhury, David Brooks 0001, Gu-Yeon Wei, Vijay Janapa Reddi. 1-6 [doi]
• Analysis and Optimization of Worst-Case Time Disparity in Cause-Effect ChainsXu Jiang 0004, Xiantong Luo, Nan Guan, Zheng Dong 0002, Shaoshan Liu, Wang Yi 0001. 1-6 [doi]
• RoaD-RuNNer: Collaborative DNN partitioning and offloading on heterogeneous edge systemsAndreas Kosmas Kakolyris, Manolis Katsaragakis, Dimosthenis Masouros, Dimitrios Soudris. 1-6 [doi]
• Security-Aware Approximate Spiking Neural NetworksSyed Tihaam Ahmad, Ayesha Siddique, Khaza Anuarul Hoque. 1-6 [doi]
• Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature SelectionZahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch, Hans-Joachim Wunderlich. 1-2 [doi]
• TPP: Accelerate Application Launch via Two-Phase Prefetching on SmartphoneYing Yuan, Zhipeng Tan, Shitong Wei, Lihua Yang, Wenjie Qi, Xuanzhi Wang, Cong Liu. 1-6 [doi]
• Attacking ReRAM-based Architectures using Repeated WritesBiresh Kumar Joardar, Krishnendu Chakrabarty. 1-6 [doi]
• Token Adaptive Vision Transformer with Efficient Deployment for Fine-Grained Image RecognitionChonghan Lee, Rita Brugarolas Brufau, Ke Ding, Vijaykrishnan Narayanan. 1-6 [doi]
• SheLL: Shrinking eFPGA Fabrics for Logic LockingHadi Mardani Kamali, Kimia Zamiri Azar, Farimah Farahmandi, Mark M. Tehranipoor. 1-6 [doi]
• WCET Analysis of Shared Caches in Multi -Core Architectures using Event-Arrival CurvesThilo L. Fischer, Heiko Falk. 1-2 [doi]
• NimbleAI: Towards Neuromorphic Sensing-Processing 3D-integrated ChipsXabier Iturbe, Nassim Abderrahmane, Jaume Abella 0001, Sergi Alcaide, Eric Beyne, Henri-Pierre Charles, Christelle Charpin-Nicolle, Lars Chittka, Angélica Dávila, Arne Erdmann, Carles Estrada, Ander Fernández, Anna Fontanelli, José Flich, Gianluca Furano, Alejandro Hernán Gloriani, Erik Isusquiza, Radu Grosu, Carles Hernández, Daniele Ielmini, David Jackson, Maha Kooli, Nicola Lepri, Bernabé Linares-Barranco, Jean-Loup Lachese, Eric Laurent, Menno Lindwer, Frank Linsenmaier, Mikel Luján, Karel Masarík, Nele Mentens, Orlando Moreira, Chinmay Nawghane, Luca Peres, Jean-Philippe Noel, Arash Pourtaherian, Christoph Posch, Peter Priller, Zdenek Prikryl, Felix Resch, Oliver Rhodes, Todor P. Stefanov, Moritz Storring, Michele Taliercio, Rafael Tornero, Marcel D. van de Burgwal, Geert Van der Plas, Elisa Vianello, Pavel Zaykov. 1-6 [doi]
• Efficient Software-Implemented HW Fault Tolerance for TinyML Inference in Safety-critical ApplicationsUzair Sharif, Daniel Mueller-Gritschneder, Rafael Stahl, Ulf Schlichtmann. 1-6 [doi]
• Region-based Flash Caching with Joint Latency and Lifetime Optimization in Hybrid SMR Storage SystemsZhengang Chen, Guohui Wang, Zhi-Ping Shi 0002, Yong Guan, Tianyu Wang. 1-6 [doi]
• Quantization-Aware Neural Architecture Search with Hyperparameter Optimization for Industrial Predictive Maintenance ApplicationsNick van de Waterlaat, Sebastian Vogel, Hiram Rayo Torres Rodriguez, Willem P. Sanberg, Gerardo Daalderop. 1-2 [doi]
• FastRW: A Dataflow-Efficient and Memory-Aware Accelerator for Graph Random Walk on FPGAsYingxue Gao, Teng Wang, Lei Gong, Chao Wang 0003, Xi Li, Xuehai Zhou. 1-6 [doi]
• Accelerating Inference of 3D-CNN on ARMMany-core CPU via Hierarchical Model PartitionJiazhi Jiang, Zijiang Huang, Dan Huang, Jiangsu Du, Yutong Lu. 1-2 [doi]
• Maximizing the Potential of Custom RISC-V Vector Extensions for Speeding up SHA-3 Hash FunctionsHuimin Li 0004, Nele Mentens, Stjepan Picek. 1-6 [doi]
• Perspector: Benchmarking Benchmark SuitesSandeep Kumar, Abhisek Panda, Smruti R. Sarangi. 1-6 [doi]
• Bio-inspired Autonomous Exploration Policies with CNN-based Object Detection on Nano-dronesLorenzo Lamberti, Luca Bompani, Victor Javier Kartsch, Manuele Rusci, Daniele Palossi, Luca Benini. 1-6 [doi]
• Maximizing Computing Accuracy on Resource-Constrained ArchitecturesVan-Phu Ha, Olivier Sentieys. 1-6 [doi]
• Smart Hammering: A practical method of pinhole detection in MRAM memoriesSina Bakhtavari Mamaghani, Christopher Münch, Jongsin Yun, Martin Keim, Mehdi Baradaran Tahoori. 1-6 [doi]
• FPGA Acceleration of GCN in Light of the Symmetry of Graph Adjacency MatrixGopikrishnan Raveendran Nair, Han-Sok Suh, Mahantesh Halappanavar, Frank Liu, Jae-sun Seo, Yu Cao 0001. 1-6 [doi]
• ISOP: Machine Learning-Assisted Inverse Stack-Up Optimization for Advanced Package DesignHyunsu Chae, Bhyrav Mutnury, Keren Zhu 0001, Douglas Wallace, Douglas Winterberg, Daniel De Araujo, Jay Reddy, Adam R. Klivans, David Z. Pan. 1-6 [doi]
• ZuSE Ki-Avf: Application-Specific AI Processor for Intelligent Sensor Signal Processing in Autonomous DrivingGia Bao Thieu, Sven Gesper, Guillermo Payá Vayá, Christoph Riggers, Oliver Renke, Till Fiedler, Jakob Marten, Tobias Stuckenberg, Holger Blume, Christian Weis, Lukas Steiner, Chirag Sudarshan, Norbert Wehn, Lennart M. Reimann, Rainer Leupers, Michael Beyer, Daniel Köhler, Alisa Jauch, Jan Micha Borrmann, Setareh Jaberansari, Tim Berthold, Meinolf Blawat, Markus Kock, Gregor Schewior, Jens Benndorf, Frederik Kautz, Hans-Martin Blüthgen, Christian Sauer 0001. 1-6 [doi]
• Achieving Datacenter-scale Performance through Chiplet-based Manycore ArchitecturesHarsh Sharma, Sumit K. Mandal, Janardhan Rao Doppa, Ümit Y. Ogras, Partha Pratim Pande. 1-6 [doi]
• Run-time integrity monitoring of untrustworthy analog front-endsHeba Salem, Nigel P. Topham. 1-6 [doi]
• Analog Coverage-driven Selection of Simulation Corners for AMS Integrated CircuitsSayandeep Sanyal, Aritra Hazra, Pallab Dasgupta, Scott Morrison, Sudhakar Surendran, Lakshmanan Balasubramanian, Mohammad Moshiur Rahman. 1-6 [doi]
• Computing Effective Resistances on Large Graphs Based on Approximate Inverse of Cholesky FactorZhiqiang Liu, Wenjian Yu. 1-6 [doi]
• Timing Predictability for SOME/IP-based Service-Oriented Automotive In-Vehicle NetworksEnrico Fraccaroli, Prachi Joshi, Shengjie Xu, Khaja Shazzad, Markus Jochim, Samarjit Chakraborty. 1-6 [doi]
• Using High-Level Synthesis to model System Verilog procedural timing controlsLuca Ezio Pozzoni, Fabrizio Ferrandi, Loris Mendola, Alfio Antonino Palazzo, Francesco Pappalardo 0002. 1-6 [doi]
• A machine-learning-guided framework for fault-tolerant DNNsMarcello Traiola, Angeliki Kritikakou, Olivier Sentieys. 1-2 [doi]
• Synthesis and Utilization of Standard Cells Amenable to Gear Ratio of Gate-Metal Pitches for Improving Pin AccessibilityJooyeon Jeong, Sehyeon Chung, Kyeongrok Jo, Taewhan Kim. 1-6 [doi]
• DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA toolKyungjoon Chang, Jaehoon Ahn, Heechun Park, Kyu-Myung Choi, Taewhan Kim. 1-6 [doi]
• A Speed- and Energy-Driven Holistic Training Framework for Sparse CNN AcceleratorsYuanchen Qu, Yu Ma, Pingqiang Zhou. 1-6 [doi]
• Debugging Low Power Analog Neural Networks for Edge ComputingSascha Schmalhofer, Marwin Möller, Nikoletta Katsaouni, Marcel H. Schulz, Lars Hedrich. 1-2 [doi]
• Digital Emulation of Oscillator Ising MachinesShreesha Sreedhara, Jaijeet Roychowdhury, Joachim Wabnig, Pavan Srinath. 1-2 [doi]
• SAT-MapIt: A SAT-based Modulo Scheduling Mapper for Coarse Grain Reconfigurable ArchitecturesCristian Tirelli, Lorenzo Ferretti, Laura Pozzi. 1-6 [doi]
• APUF Production Line Faults: Uniqueness and TestingYeqi Wei, Wenjing Rao, Natasha Devroye. 1-6 [doi]
• SoCFuzzer: SoC Vulnerability Detection using Cost Function enabled Fuzz TestingMuhammad Monir Hossain, Arash Vafaei, Kimia Zamiri Azar, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor. 1-6 [doi]
• Liveness-Aware Checkpointing of Arrays for Efficient Intermittent ComputingYoungbin Kim, Yoojin Lim, Chaedeok Lim. 1-6 [doi]
• Divide and Verify: Using a Divide-and-Conquer Strategy for Polynomial Formal Verification of Complex CircuitsRolf Drechsler, Alireza Mahzoon. 1-2 [doi]
• RTLock: IP Protection using Scan-Aware Logic Locking at RTLMd Rafid Muttaki, Shyvagata Saha, Hadi Mardani Kamali, Fahim Rahman, Mark M. Tehranipoor, Farimah Farahmandi. 1-6 [doi]
• Efficient Software Masking of AES through Instruction Set ExtensionsSongqiao Cui, Josep Balasch. 1-6 [doi]
• SIMSnn: A Weight-Agnostic ReRAM-based Search-In-Memory Engine for SNN AccelerationFangxin Liu, Wenbo Zhao, Zongwu Wang, Xiaokang Yang, Li Jiang 0002. 1-2 [doi]
• R-LDPC: Refining Behavior Descriptions in HLS to Implement High-throughput LDPC DecoderYifan Zhang, Qiang Cao 0001, Jie Yao, Hong Jiang 0001. 1-6 [doi]
• Fast Performance Evaluation Methodology for High-speed Memory InterfacesTaehoon Kim, Yoona Lee, Woo-seok Choi. 1-6 [doi]
• Assessing Convolutional Neural Networks Reliability through Statistical Fault InjectionsAnnachiara Ruospo, Gabriele Gavarini, Corrado De Sio, J. Guerrero, Luca Sterpone, Matteo Sonza Reorda, Ernesto Sánchez 0001, Riccardo Mariani, J. Aribido, Jyotika Athavale. 1-6 [doi]
• The TeamPlay Project: Analysing and Optimising Time, Energy, and Security for Cyber-Physical SystemsBenjamin Rouxel, Christopher Brown 0002, Emad Ebeid, Kerstin Eder, Heiko Falk, Clemens Grelck, Jesper Holst, Shashank Jadhav, Yoann Marquer, Marcos Martinez de Alejandro, Kris Nikov, Ali Sahafi, Ulrik Pagh Schultz Lundquist, Adam Seewald, Vangelis Vassalos, Simon Wegener, Olivier Zendra. 1-6 [doi]
• Thermal Management for S-NUCA Many-Cores via Synchronous Thread RotationsYixian Shen, Sobhan Niknam, Anuj Pathania, Andy D. Pimentel. 1-6 [doi]
• Scalable Scan-Chain-Based Extraction of Neural Network ModelsShui Jiang, Seetal Potluri, Tsung-Yi Ho. 1-6 [doi]
• EMNAPE: Efficient Multi-Dimensional Neural Architecture Pruning for EdgeAIHao Kong, Xiangzhong Luo, Shuo Huai, Di Liu 0002, Ravi Subramaniam, Christian Makaya, Qian Lin, Weichen Liu. 1-2 [doi]
• HUnTer: Hardware Underneath Trigger for Exploiting SoC-level VulnerabilitiesSree Ranjani Rajendran, Shams Tarek, Benjamin M. Hicks, Hadi Mardani Kamali, Farimah Farahmandi, Mark M. Tehranipoor. 1-6 [doi]
• Learning-Oriented Reliability Improvement of Computing Systems From Transistor to Application LevelBehnaz Ranjbar, Florian Klemme, Paul R. Genssler, Hussam Amrouch, Jinhyo Jung, Shail Dave, Hwisoo So, Kyongwoo Lee, Aviral Shrivastava, Ji-Yung Lin, Pieter Weckx, Subrat Mishra, Francky Catthoor, Dwaipayan Biswas, Akash Kumar 0001. 1-10 [doi]
• Spatio-Temporal Modeling for Flash Memory Channels Using Conditional Generative NetsSimeng Zheng, Chih-Hui Ho, Wenyu Peng, Paul H. Siegel. 1-6 [doi]
• TIPLock: Key-Compressed Logic Locking using Through-Input-Programmable Lookup-TablesKaveh Shamsi, Rajesh Kumar Datta. 1-2 [doi]
• Self-awareness in Cyber-Physical Systems: Recent Developments and Open ChallengesLukas Esterle, Nikil D. Dutt, Christian Gruhl, Peter R. Lewis 0001, Lucio Marcenaro, Carlo S. Regazzoni, Axel Jantsch. 1-6 [doi]
• Exploiting assertions mining and fault analysis to guide RTL-level approximationAlberto Bosio, Samuele Germiniani, Graziano Pravadelli, Marcello Traiola. 1-2 [doi]
• Multidimensional Features Helping Predict Failures in Production SSD-Based Consumer Storage SystemsXinyan Zhang, Zhipeng Tan, Dan Feng, Qiang He, Wan Ju, Jiang Hao, Ji Zhang, Lihua Yang, Wenjie Qi. 1-6 [doi]
• Lattice QuantizationClément Metz, Thibault Allenet, Johannes C. Thiele, Antoine Dupret, Olivier Bichler. 1-2 [doi]
• CFU Playground: Want a faster ML processor? Do it yourself!Shvetank Prakash, Tim Callahan, Joseph Bushagour, Colby R. Banbury, Alan V. Green, Pete Warden, Tim Ansell, Vijay Janapa Reddi. 1-2 [doi]
• A Hardware-Software Cooperative Interval-Replaying for FPGA-based Architecture EvaluationHongwei Cui, Shuhao Liang, Yujie Cui, Weiqi Zhang, Honglan Zhan, Chun Yang, Xianhua Liu 0001, Xu Cheng 0001. 1-2 [doi]
• Synthesis with Explicit DependenciesPriyanka Golia, Subhajit Roy 0001, Kuldeep S. Meel. 1-6 [doi]
• ESRU: Extremely Low-Bit and Hardware-Efficient Stochastic Rounding Unit Design for Low-Bit DNN TrainingSung-En Chang, Geng Yuan, Alec Lu, Mengshu Sun, Yanyu Li, Xiaolong Ma, Zhengang Li, Yanyue Xie, Minghai Qin, Xue Lin, Zhenman Fang, Yanzhi Wang. 1-6 [doi]
• Pipe-BD: Pipelined Parallel Blockwise DistillationHongsun Jang, Jaewon Jung, Jaeyong Song, Joonsang Yu, Youngsok Kim, Jinho Lee. 1-6 [doi]
• STSearch: State Tracing-based Search Heuristics for RTL ValidationZiyue Zheng, Yangdi Lyu. 1-6 [doi]
• RL-Legalizer: Reinforcement Learning-based Cell Priority Optimization in Mixed-Height Standard Cell LegalizationSung Yun Lee, SeongHyeon Park, Daeyeon Kim, Minjae Kim, Tuyen P. Le, Seokhyeong Kang. 1-6 [doi]
• Lossless Sparse Temporal Coding for SNN-based Classification of Time-Continuous SignalsJohnson Loh, Tobias Gemmeke. 1-6 [doi]
• A Decentralized Frontier Queue for Improving Scalability of Breadth-First-Search on GPUsChou-Ying Hsieh, Po-Hsiu Cheng, Chia-Ming Chang, Sy-Yen Kuo. 1-6 [doi]
• Hardware Trojans in eNVM Neuromorphic DevicesLingxi Wu, Rahul Sreekumar, Rasool Sharifi, Kevin Skadron, Mircea R. Stan, Ashish Venkat. 1-6 [doi]
• SAFEXPLAIN: Safe and Explainable Critical Embedded Systems Based on AIJaume Abella 0001, Jon Pérez 0001, Cristofer Englund, Bahram Zonooz, Gabriele Giordana, Carlo Donzella, Francisco J. Cazorla, Enrico Mezzetti, Isabel Serra, Axel Brando, Irune Agirre, Fernando Eizaguirre, Thanh Hai Bui, Elahe Arani, Fahad Sarfraz, Ajay Balasubramaniam, Ahmed Badar, Ilaria Bloise, Lorenzo Feruglio, Ilaria Cinelli, Davide Brighenti, Davide Cunial. 1-6 [doi]
• High-accuracy Low-power Reconfigurable Architectures for Decomposition-based Approximate Lookup TableXingyue Qian, Chang Meng, Xiaolong Shen, Junfeng Zhao 0003, Leibin Ni, Weikang Qian. 1-6 [doi]
• MECALS: A Maximum Error Checking Technique for Approximate Logic SynthesisChang Meng, Jiajun Sun, Yuqi Mai, Weikang Qian. 1-6 [doi]
• Routability Prediction using Deep Hierarchical Classification and RegressionDaeyeon Kim, Jakang Lee, Seokhyeong Kang. 1-2 [doi]
• Real-Time Acoustic Perception for Automotive ApplicationsJun Yin, Stefano Damiano, Marian Verhelst, Toon van Waterschoot, Andre Guntoro. 1-6 [doi]
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• AIrchitect: Automating Hardware Architecture and Mapping OptimizationAnanda Samajdar, Jan Moritz Joseph, Tushar Krishna. 1-6 [doi]
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• Federated Learning with Heterogeneous Models for On-device Malware Detection in IoT NetworksSanket Shukla, Setareh Rafatirad, Houman Homayoun, Sai Manoj Pudukotai Dinakarrao. 1-6 [doi]
• ENASA: Towards Edge Neural Architecture Search based on CIM accelerationShixin Zhao, Songyun Qu, Ying Wang 0001, Yinhe Han. 1-2 [doi]
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• MOELA: A Multi-Objective Evolutionary/Learning Design Space Exploration Framework for 3D Heterogeneous Manycore PlatformsSirui Qi, Yingheng Li, Sudeep Pasricha, Ryan Gary Kim. 1-6 [doi]
• Design of Large-Scale Stochastic Computing Adders and their Anomalous BehaviorTimothy J. Baker, John P. Hayes. 1-6 [doi]
• Towards a Robust Multiply-Accumulate Cell in Photonics using Phase-Change MaterialsRaphael Cardoso, Clément Zrounba, Mohab Abdalla, Paul Jiménez, Mauricio Gomes de Queiroz, Benoît Charbonnier, Fabio Pavanello, Ian O'Connor, Sébastien Le Beux. 1-2 [doi]
• Scalable Spintronics-based Bayesian Neural Network for Uncertainty EstimationSoyed Tuhin Ahmed, Kamal Danouchi, Michael Hefenbrock, Guillaume Prenat, Lorena Anghel, Mehdi B. Tahoori. 1-6 [doi]
• Bitstream- Level Interconnect Fault Characterization for SRAM-based FPGAsChristian Fibich, Martin Horauer, Roman Obermaisser. 1-2 [doi]
• PumpChannel: An Efficient and Secure Communication Channel for Trusted Execution Environment on ARM-FPGA Embedded SoCJingquan Ge, Yuekang Li, Yang Liu 0003, Yaowen Zheng, Yi Liu, Lida Zhao. 1-6 [doi]
• A Novel Fault-Tolerant Architecture for Tiled Matrix MultiplicationSandeep Bal, Chandra Sekhar Mummidi, Victor da Cruz Ferreira, Sudarshan Srinivasan, Sandip Kundu. 1-6 [doi]
• PRIVE: Efficient RRAM Programming with Chip Verification for RRAM-based In-Memory Computing AccelerationWangxin He, Jian Meng, Sujan Kumar Gonugondla, Shimeng Yu, Naresh R. Shanbhag, Jae-sun Seo. 1-6 [doi]
• Spoiler-Alert: Detecting Spoiler Attacks Using a Cuckoo FilterJinhua Cui, Yiyun Yin, Congcong Chen, Jiliang Zhang 0002. 1-6 [doi]
• HADAS: Hardware-Aware Dynamic Neural Architecture Search for Edge Performance ScalingHalima Bouzidi, Mohanad Odema, Hamza Ouarnoughi, Mohammad Abdullah Al Faruque, Smaïl Niar. 1-6 [doi]
• Comprehensive Analysis of Hyperdimensional Computing Against Gradient Based AttacksHamza Errahmouni Barkam, SungHeon Eavn Jeon, Calvin Yeung, Zhuowen Zou, Xun Jiao, Mohsen Imani. 1-2 [doi]
• AuxcellGen: A Framework for Autonomous Generation of Analog and Memory Unit CellsSumanth Kamineni, Arvind K. Sharma, Ramesh Harjani, Sachin S. Sapatnekar, Benton H. Calhoun. 1-6 [doi]
• Hardware-Aware Automated Neural Minimization for Printed Multilayer PerceptronsArgyris Kokkinis, Georgios Zervakis 0001, Kostas Siozios, Mehdi B. Tahoori, Jörg Henkel. 1-2 [doi]
• Dynamic Task Remapping for Reliable CNN Training on ReRAM CrossbarsChung-Hsuan Tung, Biresh Kumar Joardar, Partha Pratim Pande, Janardhan Rao Doppa, Hai Helen Li, Krishnendu Chakrabarty. 1-6 [doi]
• HD-I-IoT: Hyperdimensional Computing for Resilient Industrial Internet of Things AnalyticsOnat Güngör, Tajana Rosing, Baris Aksanli. 1-6 [doi]
• CoFHEE: A Co-processor for Fully Homomorphic Encryption ExecutionMohammed Nabeel 0001, Deepraj Soni, Mohammed Ashraf, Mizan Abraha Gebremichael, Homer Gamil, Eduardo Chielle, Ramesh Karri, Mihai Sanduleanu, Michail Maniatakos. 1-2 [doi]
• TOFU: A Two-Step Floorplan Refinement Framework for Whitespace ReductionShixiong Kai, Chak-Wa Pui, Fangzhou Wang, Shougao Jiang, Bin Wang 0034, Yu Huang, Jianye Hao. 1-5 [doi]
• Temperature Impact on Remote Power Side-Channel Attacks on Shared FPGAsOgnjen Glamocanin, Hajira Bazaz, Mathias Payer, Mirjana Stojilovic. 1-6 [doi]
• DeepTH: Chip Placement with Deep Reinforcement Learning Using a Three-Head Policy NetworkDengwei Zhao, Shuai Yuan, Yanan Sun 0003, Shikui Tu, Lei Xu 0001. 1-2 [doi]
• Long Range Detection of Emanation from HDMI Cables Using CNN and Transfer LearningMd Faizul Bari, Meghna Roy Chowdhury, Shreyas Sen. 1-6 [doi]
• High-Level Synthesis versus Hardware ConstructionAlexander Kamkin, Mikhail M. Chupilko, Mikhail Lebedev, Sergey A. Smolov, Georgi Gaydadjiev. 1-6 [doi]
• FELOPi: A Framework for Simulation and Evaluation of Post-Layout File Against Optical ProbingSajjad Parvin, Mehran Goli, Frank Sill Torres, Rolf Drechsler. 1-2 [doi]
• Jumping Shift: A Logarithmic Quantization Method for Low-Power CNN AccelerationLongxing Jiang, David Aledo, René van Leuken 0001. 1-6 [doi]
• Improving Reliability of Spiking Neural Networks through Fault Aware Threshold Voltage OptimizationAyesha Siddique, Khaza Anuarul Hoque. 1-6 [doi]
• Improving Design Understanding of Processors leveraging Datapath ClusteringKatharina Ruep, Daniel Große. 1-2 [doi]
• Post-Silicon Optimization of a Highly Programmable 64-MHz PLL Achieving 2.7-5.7 μWMarco Gonzalez, David Bol. 1-6 [doi]
• EasiMask-Towards Efficient, Automated, and Secure Implementation of Masking in HardwareFabian Buschkowski, Pascal Sasdrich, Tim Güneysu. 1-6 [doi]
• BOMP- NAS: Bayesian Optimization Mixed Precision NASDavid van Son, Floran de Putter, Sebastian Vogel, Henk Corporaal. 1-2 [doi]
• Reduce: A Framework for Reducing the Overheads of Fault-Aware RetrainingMuhammad Abdullah Hanif, Muhammad Shafique 0001. 1-2 [doi]
• ADEE-LID: Automated Design of Energy-Efficient Hardware Accelerators for Levodopa-Induced Dyskinesia ClassifiersMartin Hurta, Vojtech Mrazek, Michaela Drahosova, Lukás Sekanina. 1-2 [doi]
• Autonomous Hyperloop Control Architecture Design using MAPE-KJulian Demicoli, Laurin Prenzel, Sebastian Steinhorst. 1-6 [doi]
• Establishing Dynamic Secure Sessions for ECQV Implicit Certificates in Embedded SystemsFikret Basic, Christian Steger, Robert Kofler. 1-6 [doi]
• ODLPIM: A Write-Optimized and Long-Lifetime ReRAM-Based Accelerator for Online Deep LearningHeng Zhou, Bing Wu 0001, Huan Cheng, Wei Zhao 0034, Xueliang Wei, Jinpeng Liu, Dan Feng 0001, Wei Tong 0001. 1-6 [doi]
• Exploration of Decision Sub-Network Architectures for FPGA-based Dynamic DNNsAnstasios Dimitriou, Mingyu Hu, Jonathon S. Hare, Geoff V. Merrett. 1-2 [doi]
• ChiselFV: A Formal Verification Framework for ChiselMufan Xiang, Yongjian Li, Yongxin Zhao. 1-6 [doi]
• Cache Side-channel Attacks and Defenses of the Sliding Window Algorithm in TEEsZili Kou, Sharad Sinha, Wenjian He, Wei Zhang 0012. 1-6 [doi]
• Information Processing Factory 2.0 - Self-awareness for Autonomous Collaborative SystemsNora Sperling, Alex Bendrick, Dominik Stöhrmann, Rolf Ernst, Bryan Donyanavard, Florian Maurer 0003, Oliver Lenke, Anmol Surhonne, Andreas Herkersdorf, Walaa Amer, Caio Batista de Melo, Ping-Xiang Chen, Quang Anh Hoang, Rachid Karami, Biswadip Maity, Paul Nikolian, Mariam Rakka, Dongjoo Seo, Saehanseul Yi, Minjun Seo, Nikil D. Dutt, Fadi J. Kurdahi. 1-6 [doi]
• Ultra-Dense 3D Physical Design Unlocks New Architectural Design Points with Large BenefitsTathagata Srimani, Robert M. Radway, Jinwoo Kim, Kartik Prabhu, Dennis Rich, Carlo Gilardi, Priyanka Raina, Max M. Shulaker, Sung Kyu Lim, Subhasish Mitra. 1-6 [doi]
• Processor Verification using Symbolic Execution: A RISC-V Case-StudyNiklas Bruns, Vladimir Herdt, Rolf Drechsler. 1-6 [doi]
• Quo Vadis Signal? Automated Directionality Extraction for Post-Programming Verification of a Transistor-Level Programmable FabricApurva Jain, Thomas Broadfoot, Yiorgos Makris, Carl Sechen. 1-2 [doi]
• AXI-Pack: Near-Memory Bus Packing for Bandwidth-Efficient Irregular WorkloadsChi Zhang, Paul Scheffler, Thomas Benz, Matteo Perotti, Luca Benini. 1-6 [doi]
• ImpactTracer: Root Cause Localization in Microservices Based on Fault Propagation ModelingRu Xie, Jing Yang, Jingying Li, Liming Wang. 1-6 [doi]
• READ: Reliability-Enhanced Accelerator Dataflow Optimization using Critical Input Pattern ReductionZuodong Zhang, Meng Li 0004, Yibo Lin, Runsheng Wang, Ru Huang. 1-2 [doi]
• Narrowing the Synthesis Gap: Academic FPGA Synthesis is Catching Up With the IndustryBenjamin Lukas Cajus Barzen, Arya Reais-Parsi, Eddie Hung, Minwoo Kang, Alan Mishchenko, Jonathan W. Greene, John Wawrzynek. 1-6 [doi]
• Machine Learning Accelerators in 2.5D Chiplet Platforms with Silicon PhotonicsFebin Sunny, Ebadollah Taheri, Mahdi Nikdast, Sudeep Pasricha. 1-6 [doi]
• A Novel Delay Calibration Method Considering Interaction between Cells and WiresLeilei Jin, Jiajie Xu, Wenjie Fu, Hao Yan, Xiao Shi, Ming Ling, Longxing Shi. 1-6 [doi]
• PIMPR: PIM-based Personalized Recommendation with Heterogeneous Memory HierarchyTao Yang, Hui Ma, Yilong Zhao, Fangxin Liu, Zhezhi He, Xiaoli Sun, Li Jiang 0002. 1-6 [doi]
• Metric Temporal Logic with Resettable Skewed ClocksAlberto Bombardelli, Stefano Tonetta. 1-6 [doi]
• Multispectral Feature Fusion for Deep Object Detection on Embedded NVIDIA PlatformsThomas Kotrba, Martin Lechner, Omair Sarwar, Axel Jantsch. 1-2 [doi]
• Highlighting Two EM Fault Models While Analyzing a Digital Sensor LimitationsRoukoz Nabhan, Jean-Max Dutertre, Jean-Baptiste Rigaud, Jean-Luc Danger, Laurent Sauvage. 1-2 [doi]
• Center-of-delay: a new metric to drive timing margin against spatial variation in complex SOCsChristian Lütkemeyer, Anton Belov. 1-6 [doi]
• Countering Uncertainties in In-Memory-Computing Platforms with Statistical Training, Accuracy Compensation and Recursive TestAmro Eldebiky, Grace Li Zhang, Bing Li. 1-6 [doi]
• A Practical Remote Power Attack on Machine Learning Accelerators in Cloud FPGAsShanquan Tian, Shayan Moini, Daniel E. Holcomb, Russell Tessier, Jakub Szefer. 1-6 [doi]
• The Cyber-Physical Metaverse - Where Digital Twins and Humans Come TogetherDirk Elias, Dirk Ziegenbein, Philipp Mundhenk, Arne Hamann, Anthony Rowe. 1-2 [doi]
• Data Freshness Optimization on Networked Intermittent SystemsHao-Jan Huang, Wen Sheng Lim, Chia-Heng Tu, Chun-Feng Wu, Yuan-Hao Chang 0001. 1-6 [doi]
• Low-Cost First-Order Secure Boolean Masking in Glitchy HardwareDilip S. V. Kumar, Josep Balasch, Benedikt Gierlichs, Ingrid Verbauwhede. 1-2 [doi]
• GraphIte: Accelerating Iterative Graph Algorithms on ReRAM Architectures via Approximate ComputingDwaipayan Choudhury, Ananth Kalyanaraman, Partha Pande 0001. 1-6 [doi]
• Fault Model Analysis of DRAM under Electromagnetic Fault Injection AttackQiang Liu 0011, Longtao Guo, Honghui Tang. 1-6 [doi]
• Exploiting Kernel Compression on BNNsFranyell Silfa, José María Arnau, Antonio González 0001. 1-6 [doi]
• Fast STA Graph Partitioning Framework for Multi-GPU AccelerationGuannan Guo, Tsung-Wei Huang, Martin D. F. Wong. 1-6 [doi]
• Binary ReRAM-based BNN first-layer implementationMona Ezzadeen, Atreya Majumdar, Sigrid Thomas, Jean-Philippe Noël, Bastien Giraud, Marc Bocquet, François Andrieu, Damien Querlioz, Jean Michel Portal. 1-6 [doi]
• Compact Test Pattern Generation For Multiple Faults In Deep Neural NetworksDina A. Moussa, Michael Hefenbrock, Mehdi B. Tahoori. 1-2 [doi]
• P-PIM: A Parallel Processing-in-DRAM Framework Enabling Row Hammer ProtectionRanyang Zhou, Sepehr Tabrizchi, Mehrdad Morsali, Arman Roohi, Shaahin Angizi. 1-6 [doi]
• Energy-efficient Hardware Acceleration of Shallow Machine Learning ApplicationsZiqing Zeng, Sachin S. Sapatnekar. 1-6 [doi]
• Extended Abstract: Monitoring-based Thermal Management for Mixed-Criticality SystemsMarcel Mettler, Martin Rapp, Heba Khdr, Daniel Mueller-Gritschneder, Jörg Renkel, Ulf Schlichtmann. 1-2 [doi]
• SAGERoute: Synergistic Analog Routing Considering Geometric and Electrical Constraints with Manual Design CompatibilityHaoyi Zhang, Xiaohan Gao, Haoyang Luo, Jiahao Song, Xiyuan Tang, Junhua Liu, Yibo Lin, Runsheng Wang, Ru Huang. 1-6 [doi]
• HDGIM: Hyperdimensional Genome Sequence Matching on Unreliable highly scaled FeFETHamza Errahmouni Barkam, Sanggeon Yun, Paul R. Genssler, Zhuowen Zou, Che-Kai Liu, Hussam Amrouch, Mohsen Imani. 1-6 [doi]
• †You Li, Guannan Zhao, Yunqi He, Hai Zhou. 1-6 [doi]
• Upheaving Self-Heating Effects from Transistor to Circuit Level using Conventional EDA Tool FlowsFlorian Klemme, Sami Salamin, Hussam Amrouch. 1-6 [doi]
• CorrectNet: Robustness Enhancement of Analog In-Memory Computing for Neural Networks by Error Suppression and CompensationAmro Eldebiky, Grace Li Zhang, Georg Böcherer, Bing Li 0005, Ulf Schlichtmann. 1-6 [doi]
• Securing a RISC-V architecture: A dynamic approachSébastien Pillement, Maria Mendez Real, J. Pottier, T. Nieddu, B. Le Gal, Sébastien Faucou, Jean-Luc Béchennec, Mikaël Briday, Sylvain Girbal, Jimmy Le Rhun, Olivier Gilles, Daniel Gracia Pérez, A. Sintzoff, J. R. Coulon. 1-5 [doi]
• A Step Toward Safe Unattended Train Operations: A Pioneer Vital Control ModuleGiovanni Mezzina, Arturo Amendola, Mario Barbareschi, Salvatore De Simone, Grazia Mascellaro, Alberto Moriconi, Cataldo Luciano Saragaglia, Diana Serra, Daniela De Venuto. 1-4 [doi]
• XRing: A Crosstalk-Aware Synthesis Method for Wavelength-Routed Optical Ring RoutersZhidan Zheng, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann. 1-6 [doi]
• REDRAW: Fast and Efficient Hardware Accelerator with Reduced Reads And Writes for 3D UNetTom Glint, Manu Awasthi, Joycee Mekie. 1-6 [doi]
• Privacy-by-Sensing with Time-domain Differentially-Private Compressed SensingJianbo Liu, Boyang Cheng, Pengyu Zeng, Steven Davis, Muya Chang, Ningyuan Cao. 1-6 [doi]
• Proteus : HLS-based NoC Generator and SimulatorAbhimanyu Rajeshkumar Bambhaniya, Yangyu Chen, Anshuman, Rohan Banerjee, Tushar Krishna. 1-6 [doi]
• FAGC: Free Space Fragmentation Aware GC Scheme based on Observations of Energy ConsumptionLihua Yang, Zhipeng Tan, Fang Wang, Yang Xiao, Wei Zhang, Biao He. 1-2 [doi]
• The FORA European Training Network on Fog Computing for Robotics and Industrial AutomationMohammadreza Barzegaran, Paul Pop. 1-6 [doi]
• Benchmarking Large Language Models for Automated Verilog RTL Code GenerationShailja Thakur, Baleegh Ahmad, Zhenxing Fan, Hammond Pearce, Benjamin Tan 0001, Ramesh Karri, Brendan Dolan-Gavitt, Siddharth Garg. 1-6 [doi]
• PECAN: A Product-Quantized Content Addressable Memory NetworkJie Ran, Rui Lin, Jason Chun Lok Li, Jiajun Zhou, Ngai Wong. 1-6 [doi]
• Mitigating Heterogeneities in Federated Edge Learning with Resource- independence AggregationZhao Yang, Qingshuang Sun. 1-2 [doi]
• Autonomous System Design Session - Benefits, Challenges and Risks in Various Application DomainsRasmus Adler. 1-2 [doi]
• Rethinking NPN Classification from Face and Point Characteristics of Boolean FunctionsJiaxi Zhang 0001, Shenggen Zheng, Liwei Ni, Huawei Li, Guojie Luo. 1-6 [doi]
• BOMIG: A Majority Logic Synthesis Framework for AQFP LogicRongliang Fu, Junying Huang, Mengmeng Wang, Nobuyuki Yoshikawa, Bei Yu 0001, Tsung-Yi Ho, Olivia Chen. 1-2 [doi]
• Content- and Lighting-Aware Adaptive Brightness Scaling for Improved Mobile User ExperienceSamuel Isuwa, David Amos, Amit Kumar Singh 0002, Bashir M. Al-Hashimi, Geoff V. Merrett. 1-2 [doi]
• SPHERE-DNA: Privacy-Preserving Federated Learning for eHealthJari Nurmi, Yinda Xu, Jani Boutellier, Bo Tan 0003. 1-6 [doi]
• Quantum Measurement Discrimination using Cumulative Distribution FunctionsZachery Utt, Daniel Volya, Prabhat Mishra 0001. 1-6 [doi]
• Polynomial Formal Verification of Floating Point AddersJan Kleinekathöfer, Alireza Mahzoon, Rolf Drechsler. 1-2 [doi]
• Expanding In-Cone Obfuscated Tree for Anti SAT AttackRuijie Wang, Li-Nung Hsu, Yung-Chih Chen, TingTing Hwang. 1-6 [doi]
• Analysis of Quantization Across DNN Accelerator Architecture ParadigmsTom Glint, Chandan Kumar Jha 0001, Manu Awasthi, Joycee Mekie. 1-2 [doi]
• DeepCAM: A Fully CAM-based Inference Accelerator with Variable Hash Lengths for Energy-efficient Deep Neural NetworksDuy Thanh Nguyen, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda. 1-6 [doi]
• UVMMU: Hardware-Offloaded Page Migration for Heterogeneous ComputingJihun Park, Donghun Jeong, Jungrae Kim. 1-6 [doi]
• Aiding to Multimedia Accelerators: A Hardware Design for Efficient Rounding of Binary Floating Point NumbersMahendra Rathor, Vishesh Mishra, Urbi Chatterjee. 1-6 [doi]
• GEM-RL: Generalized Energy Management of Wearable Devices using Reinforcement LearningToygun Basaklar, Yigit Tuncel, Suat Gumussoy, Ümit Y. Ogras. 1-6 [doi]
• UHS: An Ultra-fast Hybrid Storage Consolidating NVM and SSD in ParallelQingsong Zhu, Qiang Cao 0001, Jie Yao. 1-6 [doi]
• COMPACT: Co-processor for Multi-mode Precision-adjustable Non-linear Activation FunctionsWenhui Ou, Zhuoyu Wu, Zheng Wang 0027, Chao Chen, Yongkui Yang. 1-6 [doi]
• Built-in Self-Test and Built-in Self-Repair Strategies Without Golden Signature for Computing in MemoryYu-Chih Tsai, Wen-Chien Ting, Chia-Chun Wang, Chia-Cheng Chang, Ren-Shuo Liu. 1-6 [doi]
• FPGA-Based Accelerator for Rank-Enhanced and Highly-Pruned Block-Circulant Neural NetworksHaena Song, Jongho Yoon, Dohun Kim, Eunji Kwon, Tae Hyun Oh, Seokhyeong Kang. 1-6 [doi]
• Optimizing Industrial Applications for Heterogeneous HPC Systems: The OPTIMA Project Intermediate stageDimitris Theodoropoulos, Olivier Michel, Pavlos Malakonakis, Konstantinos Georgopoulos, Giovanni Isotton, Dionisios N. Pnevmatikatos, Ioannis Papaefstathiou, Gino Perna, Marisa Zanotti, Panagiotis Miliadis, Panagiotis Mpakos, Chloe Alverti, Aggelos Ioannou, Max Engelen, Albert Njoroge Kahira, Iakovos Mavroidis. 1-4 [doi]
• Block Group Scheduling: A General Precision-scalable NPU Scheduling Technique with Capacity-aware Memory AllocationSeokho Lee, Younghyun Lee, Hyejun Kim, Taehoon Kim, Yongjun Park. 1-6 [doi]
• Stateful Energy Management for Multi-Source Energy Harvesting Transient Computing SystemsSergey Mileiko, Oktay Cetinkaya, Rishad A. Shafik, Domenico Balsamo. 1-6 [doi]
• EvoLUTe: Evaluation of Look-Up-Table-based Fine-Grained IP RedactionRui Guo, M. Sazadur Rahman, Hadi Mardani Kamali, Fahim Rahman, Farimah Farahmandi, Mark M. Tehranipoor. 1-6 [doi]
• HULK-V: a Heterogeneous Ultra-low-power Linux capable RISC-V SoCLuca Valente, Yvan Tortorella, Mattia Sinigaglia, Giuseppe Tagliavini, Alessandro Capotondi, Luca Benini, Davide Rossi. 1-6 [doi]
• End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing ArchitectureNazareno Bruschi, Giuseppe Tagliavini, Angelo Garofalo, Francesco Conti 0001, Irem Boybat, Luca Benini, Davide Rossi. 1-6 [doi]
• A Lightweight and Adaptive Cache Allocation Scheme for Content Delivery NetworksKe Liu, Hua Wang, Ke Zhou, Cong Li. 1-6 [doi]
• RAWAtten: Reconfigurable Accelerator for Window Attention in Hierarchical Vision TransformersWantong Li, Yandong Luo, Shimeng Yu. 1-6 [doi]
• Hierarchical Non-Structured Pruning for Computing-In-Memory Accelerators with Reduced ADC Resolution RequirementWenlu Xue, Jinyu Bai, Sifan Sun, Wang Kang. 1-6 [doi]
• Layer-Puzzle: Allocating and Scheduling Multi-task on Multi-core NPUs by Using Layer HeterogeneityChengsi Gao, Ying Wang 0001, Cheng Liu 0008, Mengdi Wang, Weiwei Chen, Yinhe Han 0001, Lei Zhang. 1-6 [doi]
• Quantised Neural Network Accelerators for Low-Power IDS in Automotive NetworksShashwat Khandelwal, Anneliese Walsh, Shanker Shreejith. 1-2 [doi]
• High-Speed and Energy-Efficient Single-Port Content Addressable Memory to Achieve Dual-Port OperationHonglan Zhan, Chenxi Wang, Hongwei Cui, Xianhua Liu 0001, Feng Liu, Xu Cheng 0001. 1-6 [doi]
• Two-Stream Neural Network for Post-Layout Waveform PredictionSanghwi Kim, Hyejin Shin, Hyunkyu Kim. 1-2 [doi]
• par-gem5: Parallelizing gem5's Atomic ModeNiko Zurstraßen, José Cubero-Cascante, Jan Moritz Joseph, Li Yichao, Xinghua Xie, Rainer Leupers. 1-6 [doi]
• M5: Multi-modal Multi-task Model Mapping on Multi-FPGA with Accelerator Configuration SearchAkshay Karkal Kamath, Stefan Abi-Karam, Ashwin Bhat, Cong Hao. 1-6 [doi]
• MemPool Meets Systolic: Flexible Systolic Computation in a Large Shared-Memory Processor ClusterSamuel Riedel, Gua Hao Khov, Sergio Mazzola, Matheus A. Cavalcante, Renzo Andri, Luca Benini. 1-2 [doi]