Patrick Girard 0001 - researchr alias

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Viewing Publication 1 - 83 from 83

2024

2023

Intra-cell Resistive-Open Defect Analysis on a Foundry 8T SRAM-based IMC ArchitectureL. Ammoura, Marie-Lise Flottes, Patrick Girard 0001, J.-P. Noel, Arnaud Virazel. ets 2023: 1-4 [doi]

On Using Cell-Aware Methodology for SRAM Bit Cell TestingX. Xhafa, Aymen Ladhar, Eric Faehn, Lorena Anghel, G. di Pendina, Patrick Girard 0001, Arnaud Virazel. ets 2023: 1-4 [doi]

Learning-Based Characterization Models for Quality Assurance of Emerging Memory TechnologiesXhesila Xhafa, Patrick Girard 0001, Arnaud Virazel. ets 2023: 1-2 [doi]

Two Double-Node-Upset-Hardened Flip-Flop Designs for High-Performance ApplicationsAibin Yan, Aoran Cao, Zhengfeng Huang, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen, Jiliang Zhang. tetc, 11(4):1070-1081, October - December 2023. [doi]

Designs of BCD Adder Based on Excess-3 Code in Quantum-Dot Cellular AutomataAibin Yan, Runqi Liu, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen, Jiliang Zhang 0002. tcasII, 70(6):2256-2260, June 2023. [doi]

Designs of Two Quadruple-Node-Upset Self-Recoverable Latches for Highly Robust Computing in Harsh Radiation EnvironmentsAibin Yan, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. taes, 59(3):2885-2897, June 2023. [doi]

A Highly Robust and Low-Power Flip-Flop Cell With Complete Double-Node-Upset Tolerance for Aerospace ApplicationsAibin Yan, Yuting He, Xiaoxiao Niu, Jie Cui 0004, Tianming Ni, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. dt, 40(4):34-41, August 2023. [doi]

LDAVPM: A Latch Design and Algorithm-Based Verification Protected Against Multiple-Node-Upsets in Harsh Radiation EnvironmentsAibin Yan, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. tcad, 42(6):2069-2073, June 2023. [doi]

Two sextuple cross-coupled SRAM cells with double-node-upset protection and cost optimization for aerospace applicationsAibin Yan, Jing Xiang, Yang Chang, Zhengfeng Huang, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. mj, 139:105908, September 2023. [doi]

Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical ApplicationsAibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. itc-asia 2023: 1-6 [doi]

High Performance and DNU-Recovery Spintronic Retention Latch for Hybrid MTJ/CMOS TechnologyAibin Yan, Zhen Zhou, Liang Ding, Jie Cui 0004, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001. date 2023: 1-2 [doi]

A Low Overhead and Double-Node-Upset Self-Recoverable LatchAibin Yan, Fan Xia, Tianming Ni, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. itc-asia 2023: 1-5 [doi]

A Low Area and Low Delay Latch Design with Complete Double-Node-Upset-Recovery for Aerospace ApplicationsAibin Yan, Shaojie Wei, Jinjun Zhang, Jie Cui 0004, Jie Song, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. glvlsi 2023: 167-171 [doi]

Design of a Novel Latch with Quadruple-Node-Upset Recovery for Harsh Radiation HardnessAibin Yan, Chao Zhou, Shaojie Wei, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. itc-asia 2023: 1-6 [doi]

Design of Low-Cost Approximate CMOS Full AddersAibin Yan, Shaojie Wei, Zhixing Li, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. iscas 2023: 1-5 [doi]

2022

A Generic Fast and Low Cost BIST Solution for CMOS Image SensorsJ. Lefevre, P. Debaud, Patrick Girard 0001, Arnaud Virazel. ets 2022: 1-2 [doi]

Test and Reliability of Approximate HardwareMarcello Traiola, Bastien Deveautour, Alberto Bosio, Patrick Girard 0001, Arnaud Virazel. In Weiqiang Liu 0001, Fabrizio Lombardi, editors, Approximate Computing. pages 233-266, Springer International Publishing, 2022. [doi]

All-spin PUF: An Area-efficient and Reliable PUF Design with Signature Improvement for Spin-transfer Torque Magnetic Cell-based All-spin CircuitsKangwei Xu, Dongrong Zhang, Qiang Ren, Yuanqing Cheng, Patrick Girard 0001. jetc, 18(4), 2022. [doi]

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation EnvironmentsAibin Yan, Zhelong Xu, Xiangfeng Feng, Jie Cui 0004, Zhili Chen, Tianming Ni, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. tetc, 10(1):404-413, 2022. [doi]

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical ApplicationsAibin Yan, Zhengzheng Fan, Liang Ding, Jie Cui 0004, Zhengfeng Huang, Qijun Wang, Hao Zheng, Patrick Girard 0001, Xiaoqing Wen. taes, 58(1):517-529, 2022. [doi]

A Highly Robust, Low Delay and DNU-Recovery Latch Design for Nanoscale CMOS TechnologyAibin Yan, Zhen Zhou, Shaojie Wei, Jie Cui 0004, Yong Zhou, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. glvlsi 2022: 255-260 [doi]

SCLCRL: Shuttling C-elements based Low-Cost and Robust Latch Design Protected against Triple Node Upsets in Harsh Radiation EnvironmentsAibin Yan, Zhixing Li, Shiwei Huang, Zijie Zhai, Xiangyu Cheng, Jie Cui 0004, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. date 2022: 1257-1262 [doi]

Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOSAibin Yan, Shukai Song, Jixiang Zhang 0007, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. itc-asia 2022: 73-78 [doi]

A Radiation-Hardened Non-Volatile Magnetic Latch with High Reliability and Persistent StorageAibin Yan, Liang Ding, Zhen Zhou, Zhengfeng Huang, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. ats 2022: 1-6 [doi]

A Highly Reliable and Low Power RHBD Flip-Flop Cell for Aerospace ApplicationsAibin Yan, Kuikui Qian, Jie Cui 0004, Ningning Cui, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001. vts 2021: 1-6 [doi]

Sextuple Cross-Coupled-DICE Based Double-Node-Upset Recoverable and Low-Delay Flip-Flop for Aerospace ApplicationsAibin Yan, Yu Chen, Shukai Song, Zijie Zhai, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. glvlsi 2022: 333-338 [doi]

2021

A Survey of Test and Reliability Solutions for Magnetic Random Access MemoriesPatrick Girard 0001, Yuanqing Cheng, Arnaud Virazel, Wei Zhao 0010, Rajendra Bishnoi, Mehdi B. Tahoori. pieee, 109(2):149-169, 2021. [doi]

*Alberto Bosio, Ian O'Connor, Marcello Traiola, Jorge Echavarria, Jürgen Teich, Muhammad Abdullah Hanif, Muhammad Shafique 0001, Said Hamdioui, Bastien Deveautour, Patrick Girard 0001, Arnaud Virazel, Koen Bertels. ets 2021: 1-10 [doi]

Self-Test Libraries Analysis for Pipelined Processors Transition Fault Coverage ImprovementRiccardo Cantoro, Patrick Girard 0001, Riccardo Masante, Sandro Sartoni, Matteo Sonza Reorda, Arnaud Virazel. iolts 2021: 1-4 [doi]

DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown EffectJinbo Chen, Chengcheng Lu, JiaCheng Ni, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng. tvlsi, 29(7):1325-1334, 2021. [doi]

A Learning-Based Methodology for Accelerating Cell-Aware Model GenerationP. d'Hondt, Aymen Ladhar, Patrick Girard 0001, Arnaud Virazel. date 2021: 1580-1585 [doi]

Reducing Overprovision of Triple Modular Reduncancy Owing to Approximate ComputingBastien Deveautour, Marcello Traiola, Arnaud Virazel, Patrick Girard 0001. iolts 2021: 1-7 [doi]

Voltage Bootstrapped Schmitt Trigger based Radiation Hardened Latch Design for Reliable CircuitsNeha Gupta, Nikhil Agrawal, Narendra Singh Dhakad, Ambika Prasad Shah, Santosh Kumar Vishvakarma, Patrick Girard 0001. glvlsi 2021: 307-312 [doi]

Design of Fault-Tolerant and Thermally Stable XOR Gate in Quantum dot Cellular AutomataSyed Farah Naz, Ambika Prasad Shah, Suhaib Ahmed, Patrick Girard 0001, Michael Waltl. ets 2021: 1-2 [doi]

Improving TID Radiation Robustness of a CMOS OxRAM-Based Neuron Circuit by Using Enclosed Layout TransistorsPablo Ilha Vaz, Patrick Girard 0001, Arnaud Virazel, Hassen Aziza. tvlsi, 29(6):1122-1131, 2021. [doi]

Dual-modular-redundancy and dual-level error-interception based triple-node-upset tolerant latch designs for safety-critical applicationsAibin Yan, Zhihui He, Jun Zhou 0016, Jie Cui 0004, Tianming Ni, Zhengfeng Huang, Xiaoqing Wen, Patrick Girard 0001. mj, 111:105034, 2021. [doi]

Design of Radiation Hardened Latch and Flip-Flop with Cost-Effectiveness for Low-Orbit Aerospace ApplicationsAibin Yan, Aoran Cao, Zhelong Xu, Jie Cui 0004, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. et, 37(4):489-502, 2021. [doi]

A 4NU-Recoverable and HIS-Insensitive Latch Design for Highly Robust Computing in Harsh Radiation EnvironmentsAibin Yan, Aoran Cao, Zhengzheng Fan, Zhelong Xu, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. glvlsi 2021: 301-306 [doi]

2020

Development and Application of Embedded Test Instruments to Digital, Analog/RFs and Secure ICsFlorence Azaïs, S. Bernard, Mariane Comte, Bastien Deveautour, Sophie Dupuis, Hassan El Badawi, Marie-Lise Flottes, Patrick Girard 0001, Vincent Kerzèrho, L. Latorre, François Lefèvre, Bruno Rouzeyre, Emanuele Valea, T. Vayssadel, Arnaud Virazel. iolts 2020: 1-4 [doi]

DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 CacheJinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng. isqed 2020: 408-414 [doi]

On Using Approximate Computing to Build an Error Detection Scheme for Arithmetic CircuitsBastien Deveautour, Arnaud Virazel, Patrick Girard 0001, Valentin Gherman. et, 36(1):33-46, 2020. [doi]

Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft ErrorsZhengda Dou, Albin Yan, Jun Zhou 0016, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. itc-asia 2020: 35-40 [doi]

An ECC-Based Repair Approach with an Offset-Repair CAM for Mitigating the MBUs Affecting Repair CAMPanagiota Papavramidou, Michael Nicolaidis, Patrick Girard 0001. iolts 2020: 1-6 [doi]

Impact of Aging on Soft Error Susceptibility in CMOS CircuitsAmbika Prasad Shah, Patrick Girard 0001. iolts 2020: 1-4 [doi]

Maximizing Yield for Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. date 2020: 810-815 [doi]

A Survey of Testing Techniques for Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. pieee, 108(12):2178-2194, 2020. [doi]

A CMOS OxRAM-Based Neuron Circuit Hardened with Enclosed Layout Transistors for Aerospace ApplicationsPablo Ilha Vaz, Patrick Girard 0001, Arnaud Virazel, Hassen Aziza. iolts 2020: 1-6 [doi]

Information Assurance Through Redundant Design: A Novel TNU Error-Resilient Latch for Harsh Radiation EnvironmentAibin Yan, Yuanjie Hu, Jie Cui 0004, Zhili Chen, Zhengfeng Huang, Tianming Ni, Patrick Girard 0001, Xiaoqing Wen. TC, 69(6):789-799, 2020. [doi]

A Novel Low-Cost TMR-Without-Voter Based HIS-Insensitive and MNU-Tolerant Latch Design for Aerospace ApplicationsAibin Yan, Zhelong Xu, Kang Yang, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. taes, 56(4):2666-2676, 2020. [doi]

Quadruple Cross-Coupled Dual-Interlocked-Storage-Cells-Based Multiple-Node-Upset-Tolerant Latch DesignsAibin Yan, Yafei Ling, Jie Cui 0004, Zhili Chen, Zhengfeng Huang, Jie Song, Patrick Girard 0001, Xiaoqing Wen. tcas, 67-I(3):879-890, 2020. [doi]

HITTSFL: Design of a Cost-Effective HIS-Insensitive TNU-Tolerant and SET-Filterable Latch for Safety-Critical ApplicationsAibin Yan, Xiangfeng Feng, Xiaohu Zhao, Hang Zhou, Jie Cui 0004, Zuobin Ying, Patrick Girard 0001, Xiaoqing Wen. dac 2020: 1-6 [doi]

Dual-Interlocked-Storage-Cell-Based Double-Node-Upset Self-Recoverable Flip-Flop Design for Safety-Critical ApplicationsAibin Yan, Zhelong Xu, Jie Cui 0004, Zuobin Ying, Zhengfeng Huang, Huaguo Liang, Patrick Girard 0001, Xiaoqing Wen. iscas 2020: 1-5 [doi]

A Sextuple Cross-Coupled SRAM Cell Protected against Double-Node UpsetsAibin Yan, Yan Chen, Jun Zhou 0016, Jie Cui 0004, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. ats 2020: 1-5 [doi]

Design of Double-Upset Recoverable and Transient-Pulse Filterable Latches for Low-Power and Low-Orbit Aerospace ApplicationsAibin Yan, Yan Chen, Zhelong Xu, Zhili Chen, Jie Cui 0004, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen. taes, 56(5):3931-3940, 2020. [doi]

Novel Speed-and-Power-Optimized SRAM Cell Designs With Enhanced Self-Recoverability From Single- and Double-Node UpsetsAibin Yan, Yan Chen, Yuanjie Hu, Jun Zhou 0016, Tianming Ni, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen. tcas, 67-I(12):4684-4695, 2020. [doi]

2019

2018

A Special Section On Machine Learning and Artificial Intelligence In Low Power ElectronicsPatrick Girard 0001. jolpe, 14(4):459, 2018. [doi]

Scan-Chain Intra-Cell Aware TestingAymen Touati, Alberto Bosio, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda, Etienne Auvray. tetc, 6(2):278-287, 2018. [doi]

On the Comparison of Different ATPG Approaches for Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. ddecs 2018: 85-90 [doi]

Testing approximate digital circuits: Challenges and opportunitiesMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. latw 2018: 1-6 [doi]

Investigation of Mean-Error Metrics for Testing Approximate Integrated CircuitsMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. dft 2018: 1-6 [doi]

2017

A Special Section on New and Future Trends in Low Power ElectronicsPatrick Girard 0001. jolpe, 13(3):279, 2017. [doi]

Approximate computing: Design & test for integrated circuitsAlberto Bosio, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi. latw 2017: 1 [doi]

A Cross-Level Power Estimation Technique to Enhance High-Level Power Models QualityAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier. jolpe, 13(1):10-28, 2017. [doi]

HPET: An Efficient Hybrid Power Estimation Technique to Improve High-Level Power CharacterizationAlejandro Nocua, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Cyril Chevalier. jcsc, 26(8):1-19, 2017. [doi]

Microprocessor Testing: Functional Meets Structural TestA. Touati, Alberto Bosio, Patrick Girard 0001, Arnaud Virazel, Paolo Bernardi, Matteo Sonza Reorda. jcsc, 26(8):1-18, 2017. [doi]

Towards digital circuit approximation by exploiting fault simulationMarcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. ewdts 2017: 1-7 [doi]

A Low-Cost Reliability vs. Cost Trade-Off Methodology to Selectively Harden Logic CircuitsImran Wali, Bastien Deveautour, Arnaud Virazel, Alberto Bosio, Patrick Girard 0001, Matteo Sonza Reorda. et, 33(1):25-36, 2017. [doi]

Towards approximation during test of Integrated CircuitsImran Wali, Marcello Traiola, Arnaud Virazel, Patrick Girard 0001, Mario Barbareschi, Alberto Bosio. ddecs 2017: 28-33 [doi]

2016

2011

Neutron detection in atmospheric environment through static and dynamic SRAM-based test benchLuigi Dilillo, Paolo Rech, Jean Marc Gallière, Patrick Girard 0001, Frederic Wrobel, Frédéric Saigné. latw 2011: 1-6 [doi]

2007

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell BehaviorMagali Bastian, Vincent Gouin, Patrick Girard 0001, Christian Landrault, Alexandre Ney, Serge Pravossoudovitch, Arnaud Virazel. ats 2007: 507-510 [doi]

Fast Bridging Fault Diagnosis using Logic InformationAlexandre Rousset, Alberto Bosio, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel. ats 2007: 33-38 [doi]

2006

Power-Aware Test Data Compression for Embedded IP CoresNabil Badereddine, Zhanglei Wang, Patrick Girard 0001, Krishnendu Chakrabarty, Serge Pravossoudovitch, Christian Landrault. ats 2006: 5-10 [doi]

2003

Defect-oriented dynamic fault models for embedded-SRAMsSimone Borri, Magali Hage-Hassan, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel. ets 2003: 23-28 [doi]

1999

On calculating efficient LFSR seeds for built-in self testChristophe Fagot, Olivier Gascuel, Patrick Girard 0001, Christian Landrault. ets 1999: 7-14 [doi]

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