Abstract is missing.
- Fault Resilience Techniques for Flash Memory of DNN AcceleratorsShyue-Kung Lu, Yu-Sheng Wu, Jin-Hua Hong, Kohei Miyase. 1-6 [doi]
- Fault Modeling and Testing of RRAM-based Computing-In MemoriesYu-Cheng Yang, Jin-Fu Li. 7-12 [doi]
- Diagnosing Transition Delay Faults under Scan-Based Logic ArrayDuo-Yao Kang, Shiou-Ning Lin, Kuen-Jong Lee. 13-18 [doi]
- A Decision Tree-Based Screening Method for Improving Test Quality of Memory ChipsYa-Chi Cheng, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao. 19-24 [doi]
- Weak Die Screening by Feature Prioritized Random Forest for Improving Semiconductor Quality and ReliabilityShian-Yu Lin, Pai-Yu Tan, Cheng-Wen Wu, Ming-Der Shieh, Chien-Hui Chuang, Gordon Liao. 25-30 [doi]
- Wafer Map Pattern Analytics Driven By Natural Language QueriesYueling Jenny Zeng, Min-Jian Yang, Li-C. Wang. 31-36 [doi]
- Timing-Critical Path Analysis in Circuit Designs Considering Aging with Signal ProbabilityJiun-Cheng Tsai, Aaron C.-W. Liang, Charles H.-P. Wen. 37-42 [doi]
- Effective Switching Probability Calculation to Locate Hotspots in Logic CircuitsTaiki Utsunomiya, Ryu Hoshino, Kohei Miyase, Shyue-Kung Lu, Xiaoqing Wen, Seiji Kajihara. 43-48 [doi]
- Test Response Compaction for Software-Based Self-TestJia-Ruei Liang, Ya-Ni Hsieh, Jiun-Lang Huang. 49-54 [doi]
- Testing and Reliability of Computing-In Memories: Solutions and ChallengesJin-Fu Li. 55-60 [doi]
- Structured Test Development Approach for Computation-in-Memory ArchitecturesMoritz Fieback, Mottaqiallah Taouil, Said Hamdioui. 61-66 [doi]
- A failure analysis framework of ReRAM In-Memory Logic operationsL. Brackmann, A. Jafari, C. Bengel, M. Mayahinia, R. Waser, D. Wouters, S. Menzel, M. Tahoori. 67-72 [doi]
- Cost-Optimized and Robust Latch Hardened against Quadruple Node Upsets for Nanoscale CMOSAibin Yan, Shukai Song, Jixiang Zhang 0007, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen, Patrick Girard 0001. 73-78 [doi]
- A Novel Dual Logic Locking Method to Prevent Counterfeit IP/ICAobo Cui, Dongrong Zhang, Qiang Ren, Donglin Su. 79-84 [doi]
- A Physically Unclonable Function Embedded in a SAR ADCYi-Ying Chen, Soon-Jyh Chang. 85-89 [doi]
- An Improvement of the No-Reference Test Scheme Based on False Edge Detection for Image Processing ApplicationHideyuki Ichihara, Naruki Itoh, Tomoo Inoue. 90-95 [doi]
- Evaluating the impact of Permanent Faults in a GPU running a Deep Neural NetworkJuan-David Guerrero-Balaguera, Luigi Galasso, Robert Limas Sierra, Ernesto Sánchez 0001, Matteo Sonza Reorda. 96-101 [doi]