Abstract is missing.
- Quantum Computer Architecture: Towards Full-Stack Quantum AcceleratorsKoen Bertels, Aritra Sarkar, Thomas Hubregtsen, M. Serrao, A. A. Mouedenne, A. Yadav, A. M. Krol, I. Ashraf. 1-6 [doi]
- Backtracking Search for Optimal Parameters of a PLL-based True Random Number GeneratorBrice Colombier, Nathalie Bochard, Florent Bernard, Lilian Bossuet. 1-6 [doi]
- Long-term Continuous Assessment of SRAM PUF and Source of Random NumbersRui Wang, Georgios N. Selimis, Roel Maes, Sven Goossens. 7-12 [doi]
- Rescuing Logic Encryption in Post-SAT Era by Locking & ObfuscationAmin Rezaei, Yuanqi Shen, Hai Zhou. 13-18 [doi]
- Selective Concolic Testing for Hardware Trojan Detection in Behavioral SystemC DesignsBin Lin, Jinchao Chen, Fei Xie. 19-24 [doi]
- Test Pattern Superposition to Detect Hardware TrojansChris Nigh, Alex Orailoglu. 25-30 [doi]
- Ternary Compute-Enabled Memory using Ferroelectric Transistors for Accelerating Deep Neural NetworksSandeep Krishna Thirumala, Shubham Jain, Sumeet Kumar Gupta, Anand Raghunathan. 31-36 [doi]
- Macro-3D: A Physical Design Methodology for Face-to-Face-Stacked Heterogeneous 3D ICsLennart Bamberg, Alberto García Ortiz, Lingjun Zhu, Sai Pentapati, Da Eun Shim, Sung Kyu Lim. 37-42 [doi]
- Quantifying the Benefits of Monolithic 3D Computing Systems Enabled by TFT and RRAMAbdallah M. Felfel, Kamalika Datta, Arko Dutt, Hasita Veluri, Ahmed Zaky, Aaron Voon-Yew Thean, Mohamed M. Sabry Aly. 43-48 [doi]
- Organic-Flow: An Open-Source Organic Standard Cell Library and Process Development KitTing-Jung Chang, Zhuozhi Yao, Barry P. Rand, David Wentzlaff. 49-54 [doi]
- GANA: Graph Convolutional Network Based Automated Netlist Annotation for Analog CircuitsKishor Kunal, Tonmoy Dhar, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Jiang Hu, Ramesh Harjani, Sachin S. Sapatnekar. 55-60 [doi]
- Securing Programmable Analog ICs Against PiracyMohamed Elshamy, Alhassan Sayed, Marie-Minerve Louërat, Amine Rhouni, Hassan Aboushady, Haralampos-G. D. Stratigopoulos. 61-66 [doi]
- An Efficient Bayesian Optimization Approach for Analog Circuit Synthesis via Sparse Gaussian Process ModelingBiao He, Shuhan Zhang, Fan Yang 0001, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 67-72 [doi]
- Deeper Weight Pruning without Accuracy Loss in Deep Neural NetworksByungmin Ahn, Taewhan Kim. 73-78 [doi]
- Flexible Group-Level Pruning of Deep Neural Networks for On-Device Machine LearningKwangbae Lee, Hoseung Kim, Hayun Lee, Dongkun Shin. 79-84 [doi]
- Sparsity-Aware Caches to Accelerate Deep Neural NetworksVinod Ganesan, Sanchari Sen, Pratyush Kumar, Neel Gala, Kamakoti Veezhinathan, Anand Raghunathan. 85-90 [doi]
- On Improving Fault Tolerance of Memristor Crossbar Based Neural Network Designs by Target SparsifyingSong Jin, Songwei Pei, Yu Wang. 91-96 [doi]
- An Efficient SRAM yield Analysis Using Scaled-Sigma Adaptive Importance SamplingLiang Pang, Mengyun Yao, Yifan Chai. 97-102 [doi]
- Fast and Accurate High-Sigma Failure Rate Estimation through Extended Bayesian Optimized Importance SamplingMichael Hefenbrock, Dennis D. Weller, Michael Beigl, Mehdi Baradaran Tahoori. 103-108 [doi]
- Valid Window: A New Metric to Measure the Reliability of NAND Flash MemoryMin Ye, Qiao Li 0001, Jianqiang Nie, Tei-Wei Kuo, Chun Jason Xue. 109-114 [doi]
- GenieHD: Efficient DNA Pattern Matching Accelerator Using Hyperdimensional ComputingYeseong Kim, Mohsen Imani, Niema Moshiri, Tajana Rosing. 115-120 [doi]
- REPUTE: An OpenCL based Read Mapping Tool for Embedded GenomicsSidharth Maheshwari, Rishad A. Shafik, Ian Wilson, Alex Yakovlev, Amit Acharyya. 121-126 [doi]
- A Fast and Energy Efficient Computing-in-Memory Architecture for Few-Shot Learning ApplicationsDayane Reis, Ann Franchesca Laguna, Michael T. Niemier, Xiaobo Sharon Hu. 127-132 [doi]
- Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper)Eleonora Testa, Samantha Lubaba Noor, Odysseas Zografos, Mathias Soeken, Francky Catthoor, Azad Naeemi, Giovanni De Micheli. 133-138 [doi]
- A RRAM-based FPGA for Energy-efficient Edge ComputingXifan Tang, Edouard Giacomin, Patsy Cadareanu, Ganesh Gore, Pierre-Emmanuel Gaillardon. 144 [doi]
- Efficient and Robust High-Level Synthesis Design Space Exploration through offline Micro-kernels Pre-characterizationZi Wang, Jianqi Chen, Benjamin Carrión Schäfer. 145-150 [doi]
- Prospector: Synthesizing Efficient Accelerators via Statistical LearningAtefeh Mehrabi, Aninda Manocha, Benjamin C. Lee, Daniel J. Sorin. 151-156 [doi]
- Tango: An Optimizing Compiler for Just-In-Time RTL SimulationBlaise-Pascal Tine, Sudhakar Yalamanchili, Hyesoon Kim. 157-162 [doi]
- ESA Athena WFI Onboard Electronics - Distributed Control and Data ProcessingMarkus Planner, Sabine Ott, Sebastian Albrecht 0003, Jintin Tran, Christopher Mandla, Jan-Christoph Tenzer, Thomas Schanz, Samuel Pliego, Denis Tcherniak, Manfred Steller, Harald Jeszensky, Roland Ottensamer, Konrad Skup, Chris Thomas, Julian Thornhill. 163-168 [doi]
- LEGaTO: Low-Energy, Secure, and Resilient Toolset for Heterogeneous ComputingBehzad Salami 0001, K. Parasyris, Adrián Cristal, Osman S. Unsal, Xavier Martorell, Paul Carpenter, Raúl de la Cruz, L. Bautista, Daniel A. Jiménez, C. Alvarez, S. Nabavi, Sergi Madonar, Miquel Pericàs, Pedro Trancoso, M. Abduljabbar, Jing Chen, Pirah Noor Soomro, Madhavan Manivannan, M. Berge, Stefan Krupop, Frank Klawonn, Al-Mekhlafi, Sigrun May, Tobias Becker, Georgi Gaydadjiev, Hans Salomonsson, Devdatt P. Dubhashi, Oron Port, Yoav Etsion, Do Le Quoc, Christof Fetzer, Martin Kaiser, Nils Kucza, Jens Hagemeyer, René Griessl, Lennart Tigges, K. Mika, A. Hüffmeier, Marcelo Pasin, Valerio Schiavoni, Isabelly Rocha, Christian Göttel, Pascal Felber. 169-174 [doi]
- Efficient Compilation and Execution of JVM-Based Data Processing Frameworks on Heterogeneous Co-ProcessorsChristos Kotselidis, Sotiris Diamantopoulos, Orestis Akrivopoulos, Viktor Rosenfeld, Katerina Doka, Hazeef Mohammed, Georgios Mylonas, Vassilis Spitadakis, Will Morgan. 175-179 [doi]
- PSB-RNN: A Processing-in-Memory Systolic Array Architecture using Block Circulant Matrices for Recurrent Neural NetworksNagadastagiri Challapalle, Sahithi Rampalli, Makesh Chandran, Gurpreet S. Kalsi, Sreenivas Subramoney, John Sampson, Vijaykrishnan Narayanan. 180-185 [doi]
- XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA ExtensionsAngelo Garofalo, Giuseppe Tagliavini, Francesco Conti 0001, Davide Rossi, Luca Benini. 186-191 [doi]
- SNA: A Siamese Network Accelerator to Exploit the Model-Level Parallelism of Hybrid Network StructureXingbin Wang, Boyan Zhao, Rui Hou, Dan Meng. 192-197 [doi]
- HcveAcc: A High-Performance and Energy-Efficient Accelerator for Tracking Task in VSLAM SystemRenwei Li, Junning Wu, Meng Liu, Zuding Chen, Shengang Zhou, Shanggong Feng. 198-203 [doi]
- *Jinghao Sun, Yaoyao Chi, Tianfei Xu, Lei Cao, Nan Guan, Zhishan Guo, Wang Yi 0001. 204-209 [doi]
- WCET-aware Code Generation and Communication Optimization for Parallelizing CompilersSimon Reder, Jürgen Becker 0001. 210-215 [doi]
- Template schedule construction for global real-time scheduling on unrelated multiprocessor platformsAntoine Bertout, Joël Goossens, Emmanuel Grolleau, Xavier Poczekajlo. 216-221 [doi]
- Application-Aware Scheduling of Networked Applications over the Low-Power Wireless BusKacper Wardega, Wenchao Li. 222-227 [doi]
- GRAMARCH: A GPU-ReRAM based Heterogeneous Architecture for Neural Image SegmentationBiresh Kumar Joardar, Nitthilan Kannappan Jayakodi, Janardhan Rao Doppa, Hai Li, Partha Pratim Pande, Krishnendu Chakrabarty. 228-233 [doi]
- An Approximate Multiplane Network-on-ChipLing Wang, Yadong Wang, Xiaohang Wang. 234-239 [doi]
- Shenjing: A low power reconfigurable neuromorphic accelerator with partial-sum and spike networks-on-chipBo Wang, Jun Zhou, Weng-Fai Wong, Li-Shiuan Peh. 240-245 [doi]
- Compressing Subject-specific Brain-Computer Interface Models into One Model by Superposition in Hyperdimensional SpaceMichael Hersche, Philipp Rupp, Luca Benini, Abbas Rahimi. 246-251 [doi]
- A novel FPGA-based system for Tumor Growth PredictionKonstantinos Malavazos, Maria Papadogiorgaki, Pavlos Malakonakis, Ioannis Papaefstathiou. 252-257 [doi]
- An Event-Based System for Low-Power ECG QRS Complex DetectionSilvio Zanoli, Tomás Teijeiro, Fabio Montagna, David Atienza. 258-263 [doi]
- Semi-Autonomous Personal Care Robots Interface driven by EEG Signals DigitizationGiovanni Mezzina, Daniela De Venuto. 264-269 [doi]
- DynUnlock: Unlocking Scan Chains Obfuscated using Dynamic KeysNimisha Limaye, Ozgur Sinanoglu. 270-273 [doi]
- CMOS Implementation of Switching LatticesIsmail Cevik, Levent Aksoy, Mustafa Altun. 274-277 [doi]
- A Timing Uncertainty-Aware Clock Tree Topology Generation Algorithm for Single Flux Quantum CircuitsSoheil Nazar Shahsavani, Bo Zhang, Massoud Pedram. 278-281 [doi]
- Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IPAntonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar, Haralampos-G. D. Stratigopoulos. 282-285 [doi]
- Range-Controlled Floating-Gate Transistors: A Unified Solution for Unlocking and Calibrating Analog ICsSai Govinda Rao Nimmalapudi, Georgios Volanis, Yichuan Lu, Angelos Antonopoulos 0002, Andrew Marshall, Yiorgos Makris. 286-289 [doi]
- Testing Through Silicon Vias in Power Distribution Network of 3D-IC with Manufacturing Variability CancellationKoutaro Hachiya, Atsushi Kurokawa. 290-293 [doi]
- TFApprox: Towards a Fast Emulation of DNN Approximate Hardware Accelerators on GPUFilip Vaverka, Vojtech Mrazek, Zdenek Vasícek, Lukás Sekanina. 294-297 [doi]
- Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error ProbabilitiesValentin Gherman, Samuel Evain, Bastien Giraud. 298-301 [doi]
- BeLDPC: Bit Errors Aware Adaptive Rate LDPC Codes for 3D TLC NAND Flash MemoryMeng Zhang, Fei Wu, Qin Yu, Weihua Liu, Lanlan Cui, Yahui Zhao, Changsheng Xie. 302-305 [doi]
- Poisoning the (Data) Well in ML-Based CAD: A Case Study of Hiding Lithographic HotspotsKang Liu 0017, Benjamin Tan, Ramesh Karri, Siddharth Garg. 306-309 [doi]
- SOLOMON: An Automated Framework for Detecting Fault Attack Vulnerabilities in HardwareMilind Srivastava, Patanjali SLPSK, Indrani Roy, Chester Rebeiro, Aritra Hazra, Swarup Bhunia. 310-313 [doi]
- Formal Synthesis of Monitoring and Detection Systems for Secure CPS ImplementationsIpsita Koley, Saurav Kumar Ghosh, Soumyajit Dey, Debdeep Mukhopadhyay, Amogh Kashyap K. N., Sachin Kumar Singh, Lavanya Lokesh, Jithin Nalu Purakkal, Nishant Sinha. 314-317 [doi]
- ASCELLA: Accelerating Sparse Computation by Enabling Stream Accesses to MemoryBahar Asgari, Ramyad Hadidi, Hyesoon Kim. 318-321 [doi]
- Acceleration of probabilistic reasoning through custom processor architectureNimish Shah, Laura Isabel Galindez Olascoaga, Wannes Meert, Marian Verhelst. 322-325 [doi]
- A Performance Analysis Framework for Real-Time Systems Sharing Multiple ResourcesShayan Tabatabaei Nikkhah, Marc Geilen, Dip Goswami, Kees Goossens. 326-329 [doi]
- Scaling Up the Memory Interference Analysis for Hard Real-Time Many-Core SystemsMaximilien Dupont de Dinechin, Matheus Schuh, Matthieu Moy, Claire Maiza. 330-333 [doi]
- Lightweight Anonymous Routing in NoC based SoCsSubodha Charles, Megan Logan, Prabhat Mishra 0001. 334-337 [doi]
- A Non-invasive Wearable Bioimpedance System to Wirelessly Monitor Bladder FillingMarkus Reichmuth, Simone Schürle, Michele Magno. 338-341 [doi]
- InfiniWolf: Energy Efficient Smart Bracelet for Edge Computing with Dual Source Energy HarvestingMichele Magno, Xiaying Wang, Manuel Eggimann, Lukas Cavigelli, Luca Benini. 342-345 [doi]
- A Flexible and Scalable NTT Hardware : Applications from Homomorphically Encrypted Deep Learning to Post-Quantum CryptographyAhmet Can Mert, Emre Karabulut, Erdinç Öztürk, Erkay Savas, Michela Becchi, Aydin Aysu. 346-351 [doi]
- Reliable and Lightweight PUF-based Key Generation using Various Index Voting ArchitectureJeong-Hyeon Kim, Ho-Jun Jo, Kyung-Kuk Jo, Sung Hee Cho, Jaeyong Chung, Joon-Sung Yang. 352-357 [doi]
- Estimating the Circuit De-obfuscation Runtime based on Graph Deep LearningZhiqian Chen, Gaurav Kolhe, Setareh Rafatirad, Chang-Tien Lu, Sai Manoj P. D, Houman Homayoun, Liang Zhao. 358-363 [doi]
- Fast and Accurate DRAM Simulation: Can we Further Accelerate it?Johannes Feldmann, Kira Kraft, Lukas Steiner, Norbert Wehn, Matthias Jung 0001. 364-369 [doi]
- Accurate and Efficient Continuous Time and Discrete Events Simulation in SystemCBreytner Fernández-Mesa, Liliana Andrade, Frédéric Pétrot. 370-375 [doi]
- Modeling and Verifying Uncertainty-Aware Timing Behaviors using Parametric Logical Time ConstraintFei Gao, Frédéric Mallet, Min Zhang 0002, Mingsong Chen. 376-381 [doi]
- Nano-Crossbar based Computing: Lessons Learned and Future DirectionsMustafa Altun, Ismail Cevik, Ahmet Erten, Osman Eksik, Mircea Stan, Csaba Andras Moritz. 382-387 [doi]
- RESCUE: Interdependent Challenges of Reliability, Security and Quality in Nanoelectronic SystemsMaksim Jenihhin, Said Hamdioui, Matteo Sonza Reorda, Milos Krstic, Peter Langendörfer, C. Sauer, Anton Klotz, M. Huebner, Jörg Nolte, Heinrich Theodor Vierhaus, Georgios N. Selimis, Dan Alexandrescu, Mottaqiallah Taouil, Geert Jan Schrijen, Jaan Raik, Luca Sterpone, Giovanni Squillero, Zoya Dyka. 388-393 [doi]
- A Universal Spintronic Technology based on Multifunctional Standardized StackMehdi Baradaran Tahoori, Sarath Mohanachandran Nair, Rajendra Bishnoi, L. Torres, Sophiane Senni, Guillaume Patrigeon, P. Benoit, Gregory di Pendina, Guillaume Prenat. 394-399 [doi]
- A Learning-Based Thermal Simulation Framework for Emerging Two-Phase Cooling TechnologiesZihao Yuan, Geoffrey Vaartstra, Prachi Shukla, Zhengmao Lu, Evelyn Wang, Sherief Reda, Ayse K. Coskun. 400-405 [doi]
- Lightweight Thermal Monitoring in Optical Networks-on-Chip via Router ReuseMengquan Li, Jun Zhou, Weichen Liu. 406-411 [doi]
- A Spectral Approach to Scalable Vectorless Thermal Integrity VerificationZhiqiang Zhao, Zhuo Feng. 412-417 [doi]
- Dynamic Thermal Management with Proactive Fan Speed Control Through Reinforcement LearningArman Iranfar, Federico Terraneo, Gabor Csordas, Marina Zapater, William Fornaciari, David Atienza. 418-423 [doi]
- Reliable and Energy-Aware Fixed-Priority (m, k)-Deadlines Enforcement with Standby-SparingLinwei Niu, Dakai Zhu 0001. 424-429 [doi]
- Period Adaptation for Continuous Security Monitoring in Multicore Real-Time SystemsMonowar Hasan, Sibin Mohan, Rodolfo Pellizzoni, Rakesh B. Bobba. 430-435 [doi]
- Efficient Latency Bound Analysis for Data Chains of Real-Time Tasks in Multiprocessor SystemsJiankang Ren, Xin He, Junlong Zhou, Hongwei Ge, Guowei Wu, Guozhen Tan. 436-441 [doi]
- Cache Persistence-Aware Memory Bus Contention Analysis for Multicore SystemsSyed Aftab Rashid, Geoffrey Nelissen, Eduardo Tovar. 442-447 [doi]
- A Particle Swarm Optimization Guided Approximate Key Search Attack on Logic Locking in The Absence of Scan AccessRajit Karmakar, Santanu Chattopadhyay. 448-453 [doi]
- Effect of Aging on PUF Modeling Attacks based on Power Side-Channel ObservationsTrevor Kroeger, Wei Cheng, Sylvain Guilley, Jean-Luc Danger, Naghmeh Karimi. 454-459 [doi]
- Offline Model Guard: Secure and Private ML on Mobile DevicesSebastian P. Bayerl, Tommaso Frassetto, Patrick Jauernig, Korbinian Riedhammer, Ahmad-Reza Sadeghi, Thomas Schneider 0003, Emmanuel Stapf, Christian Weinert. 460-465 [doi]
- Security Enhancement for RRAM Computing System through Obfuscating Crossbar Row ConnectionsMinhui Zou, Zhenhua Zhu, Yi Cai, Junlong Zhou, Chengliang Wang, Yu Wang 0002. 466-471 [doi]
- Modeling a Floating-Gate Memristive Device for Computer Aided Design of Neuromorphic ComputingLoai Danial, V. Gupta, Evgeny Pikhay, Yakov Roizin, Shahar Kvatinsky. 472-477 [doi]
- Ground Plane Partitioning for Current Recycling of Superconducting CircuitsNaveen Kumar Katam, Bo Zhang, Massoud Pedram. 478-483 [doi]
- Silicon Photonic Microring Resonators: Design Optimization Under Fabrication Non-UniformityAsif Mirza, Febin Sunny, Sudeep Pasricha, Mahdi Nikdast. 484-489 [doi]
- AutoCkt: Deep Reinforcement Learning of Analog Circuit DesignsKeertana Settaluri, Ameer Haj Ali, Qijing Huang 0001, Kourosh Hakhamaneshi, Borivoje Nikolic. 490-495 [doi]
- Towards Decrypting the Art of Analog Layout: Placement Quality Prediction via Transfer LearningMingjie Liu, Keren Zhu, Jiaqi Gu, Linxiao Shen, Xiyuan Tang, Nan Sun, David Z. Pan. 496-501 [doi]
- Design of Multi-Output Switched-Capacitor Voltage Regulator via Machine LearningZhiyuan Zhou, Syrine Belakaria, Aryan Deshwal, Wookpyo Hong, Janardhan Rao Doppa, Partha Pratim Pande, Deukhyoun Heo. 502-507 [doi]
- Towards Secure Composition of Integrated Circuits and Electronic Systems: On the Role of EDAJohann Knechtel, Elif Bilge Kavun, Francesco Regazzoni 0001, Annelie Heuser, Anupam Chattopadhyay, Debdeep Mukhopadhyay, Soumyajit Dey, Yunsi Fei, Yaacov Belenky, Itamar Levi, Tim Güneysu, Patrick Schaumont, Ilia Polian. 508-513 [doi]
- Pitfalls in Machine Learning-based Adversary Modeling for Hardware SystemsFatemeh Ganji, Sarah Amir, Shahin Tajik, Domenic Forte, Jean-Pierre Seifert. 514-519 [doi]
- Using Universal Composition to Design and Analyze Secure Complex Hardware SystemsRan Canetti, Marten van Dijk, Hoda Maleki, Ulrich Rührmair, Patrick Schaumont. 520-525 [doi]
- 2QED and Property GenerationKeerthikumara Devarajegowda, Mohammad Rahmani Fadiheh, Eshan Singh, Clark W. Barrett, Subhasish Mitra, Wolfgang Ecker, Dominik Stoffel, Wolfgang Kunz. 526-531 [doi]
- SPEAR: Hardware-based Implicit Rewriting for Square-root Circuit VerificationAtif Yasin, Tiankai Su, Sébastien Pillement, Maciej J. Ciesielski. 532-537 [doi]
- A Reinforcement Learning Approach to Directed Test Generation for Shared Memory VerificationNícolas Pfeifer, Bruno V. Zimpel, Gabriel A. G. Andrade, Luiz C. V. dos Santos. 538-543 [doi]
- Towards Formal Verification of Optimized and Industrial MultipliersAlireza Mahzoon, Daniel Große, Christoph Scholl, Rolf Drechsler. 544-549 [doi]
- Is Register Transfer Level Locking Secure?Chandan Karfa, Ramanuj Chouksey, Christian Pilato, Siddharth Garg, Ramesh Karri. 550-555 [doi]
- Design Space Exploration for Model-based Communication SystemsValentina Richthammer, Marcel Rieß, Julian Bestler, Frank Slomka, Michael Glaß. 556-561 [doi]
- Statistical Time-based Intrusion Detection in Embedded SystemsNadir Amin Carreon, Allison Gilbreath, Roman Lysecky. 562-567 [doi]
- A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic NetworksEleonora Testa, Mathias Soeken, Heinz Riener, Luca G. Amarù, Giovanni De Micheli. 568-573 [doi]
- Saving Power by Converting Flip-Flop to 3-Phase Latch-Based DesignsHuimei Cheng, Xi Li, Yichen Gu, Peter A. Beerel. 574-579 [doi]
- Computing the full quotient in bi-decomposition by approximationAnna Bernasconi 0001, Valentina Ciriani, Jordi Cortadella, Tiziano Villa. 580-585 [doi]
- MiniDelay: Multi-Strategy Timing-Aware Layer Assignment for Advanced Technology NodesXinghai Zhang, Zhen Zhuang, Genggeng Liu, Xing Huang, Wen-Hao Liu, Wenzhong Guo, Ting-Chi Wang. 586-591 [doi]
- The Hypergeometric Distribution as a More Accurate Model for Stochastic ComputingTimothy J. Baker, John P. Hayes. 592-597 [doi]
- Accuracy Analysis for Stochastic Circuits with D Flip-Flop InsertionKuncai Zhong, Weikang Qian. 598-603 [doi]
- Dynamic Stochastic Computing for Digital Signal Processing ApplicationsSiting Liu, Jie Han 0001. 604-609 [doi]
- Sampling from Discrete Distributions in Combinational Hardware with Application to Post-Quantum CryptographyMichael X. Lyons, Kris Gaj. 610-613 [doi]
- On the Performance of Non-Profiled Differential Deep Learning Attacks against an AES Encryption Algorithm Protected using a Correlated Noise Generation based Hiding CountermeasureAmir Alipour, Athanasios Papadimitriou, Vincent Beroulle, Ehsan Aerabi, David Hély. 614-617 [doi]
- *Vladimir Herdt, Daniel Große, Rolf Drechsler. 618-621 [doi]
- Automated Generation of LTL Specifications For Smart Home IoT Using Natural LanguageShiyu Zhang, Juan Zhai, Lei Bu, Mingsong Chen, Linzhang Wang, Xuandong Li. 622-625 [doi]
- A Heat-Recirculation-Aware VM Placement Strategy for Data CentersHao Feng, Yuhui Deng, Yi Zhou. 626-629 [doi]
- Energy Optimization in NCFET-based ProcessorsSami Salamin, Martin Rapp, Hussam Amrouch, Andreas Gerstlauer, Jörg Henkel. 630-633 [doi]
- Towards a Model-based Multi-Objective Optimization Approach For Safety-Critical Real-Time SystemsSoulimane Kamni, Yassine Ouhammou, Antoine Bertout, Emmanuel Grolleau. 634-637 [doi]
- Current-Mode Carry-Free Multiplier Design using a Memristor-Transistor Crossbar ArchitectureShengqi Yu, Ahmed Soltan, Rishad A. Shafik, Thanasin Bunnam, Fei Xia, Domenico Balsamo, Alex Yakovlev. 638-641 [doi]
- n-bit Data Parallel Spin Wave Logic GateAbdulqader Mahmoud, Frederic Vanderveken, Florin Ciubotaru, Christoph Adelmann, Sorin Cotofana, Said Hamdioui. 642-645 [doi]
- High-speed analog simulation of CMOS vision chips using explicit integration techniques on many-core processorsGinés Doménech-Asensi, Tom J. Kazmierski. 646-649 [doi]
- A 100KHz-1GHz Termination-dependent Human Body Communication Channel Measurement using Miniaturized Wearable DevicesShitij Avlani, Mayukh Nath, Shovan Maity, Shreyas Sen. 650-653 [doi]
- From DRUP to PAC and BackDaniela Kaufmann, Armin Biere, Manuel Kauers. 654-657 [doi]
- Verifiable Security Templates for HardwareWilliam L. Harrison, Gerard Allwein. 658-661 [doi]
- IFFSET: In-Field Fuzzing of Industrial Control Systems using System EmulationDimitrios Tychalas, Michail Maniatakos. 662-665 [doi]
- FANNet: Formal Analysis of Noise Tolerance, Training Bias and Input Sensitivity in Neural NetworksMahum Naseer, Mishal Fatima Minhas, Faiq Khalid, Muhammad Abdullah Hanif, Osman Hasan, Muhammad Shafique 0001. 666-669 [doi]
- A Scalable Mixed Synthesis Framework for Heterogeneous NetworksMax Austin, Scott Temple, Walter Lau Neto, Luca G. Amarù, Xifan Tang, Pierre-Emmanuel Gaillardon. 670-673 [doi]
- DiSCERN: Distilling Standard-Cells for Emerging Reconfigurable NanotechnologiesShubham Rai, Michael Raitza, Siva Satyendra Sahoo, Akash Kumar 0001. 674-677 [doi]
- A 16×128 Stochastic-Binary Processing Element Array for Accelerating Stochastic Dot-Product Computation Using 1-16 Bit-Stream LengthQian Chen, Yuqi Su, Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim. 678-681 [doi]
- Towards Exploring the Potential of Alternative Quantum Computing ArchitecturesArighna Deb, Gerhard W. Dueck, Robert Wille. 682-685 [doi]
- Accelerating Quantum Approximate Optimization Algorithm using Machine LearningMahabubul Alam, Abdullah Ash-Saki, Swaroop Ghosh. 686-689 [doi]
- In-Memory Resistive RAM Implementation of Binarized Neural Networks for Medical ApplicationsBogdan Penkovsky, Marc Bocquet, Tifenn Hirtzlin, Jacques-Olivier Klein, Etienne Nowak, Elisa Vianello, Jean Michel Portal, Damien Querlioz. 690-695 [doi]
- Mixed-Signal Vector-by-Matrix Multiplier Circuits Based on 3D-NAND Memories for NeurocomputingMohammad Bavandpour, Shubham Sahay, Mohammad Reza Mahmoodi, Dmitri B. Strukov. 696-701 [doi]
- An Efficient Persistency and Recovery Mechanism for SGX-style Integrity Tree in Secure NVMMengya Lei, Fang Wang, Dan Feng, Fan Li, Jie Xu. 702-707 [doi]
- Revisiting Persistent Hash Table Design for Commercial Non-Volatile MemoryKaixin Huang, Yan Yan, Linpeng Huang. 708-713 [doi]
- Optimizing Performance of Persistent Memory File Systems using Virtual SuperpagesChaoshu Yang, Duo Liu, Runyu Zhang, Xianzhang Chen, Shun Nie, Qingfeng Zhuge, Edwin H.-M. Sha. 714-719 [doi]
- Frequent Access Pattern-based Prefetching Inside of Solid-State DrivesXiaofei Xu, Zhigang Cai, Jianwei Liao, Yutaka Ishikawa. 720-725 [doi]
- Engineering Change Order for Combinational and Sequential Design RectificationJie-Hong R. Jiang, Victor N. Kravets, Nian-Ze Lee. 726-731 [doi]
- Exact DAG-Aware RewritingHeinz Riener, Alan Mishchenko, Mathias Soeken. 732-737 [doi]
- Learning to Automate the Design Updates From Observed Engineering Changes in the Chip Development CycleVictor N. Kravets, Jie-Hong R. Jiang, Heinz Riener. 738-743 [doi]
- Synthesis and Optimization of Multiple Portions of Circuits for ECO based on Set-Covering and QBF FormulationsMasahiro Fujita, Yusuke Kimura, Xingming Le, Yukio Miyasaka, Amir Masoud Gharehbaghi. 744-749 [doi]
- Efficient Hardware-Assisted Crash Consistency in Encrypted Persistent MemoryZhan Zhang, Jianhui Yue, Xiaofei Liao, Hai Jin 0001. 750-755 [doi]
- 2DCC: Cache Compression in Two DimensionsAmin Ghasemazar, Mohammad Ewais, Prashant Nair, Mieszko Lis. 756-761 [doi]
- GraphVine: Exploiting Multicast for Scalable Graph AnalyticsLeul Belayneh, Valeria Bertacco. 762-767 [doi]
- ACOUSTIC: Accelerating Convolutional Neural Networks through Or-Unipolar Skipped Stochastic ComputingWojciech Romaszkan, Tianmu Li, Tristan Melton, Sudhakar Pamarti, Puneet Gupta. 768-773 [doi]
- Accuracy Tolerant Neural Networks Under Aggressive Power OptimizationXiang-Xiu Wu, Yi-Wen Hung, Yung-Chih Chen, Shih-Chieh Chang. 774-779 [doi]
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- PhoneBit: Efficient GPU-Accelerated Binary Neural Network Inference Engine for Mobile PhonesGang Chen, Shengyu He, Haitao Meng, Kai Huang. 786-791 [doi]
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- Priority-Preserving Optimization of Status Quo ID-Assignments in Controller Area NetworkSebastian Schwitalla, Lea Schönberger, Jian-Jia Chen. 834-839 [doi]
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- Realizing Quantum Algorithms on Real Quantum Computing DevicesCarmen G. Almudéver, Lingling Lao, Robert Wille, Gian G. Guerreschi. 864-872 [doi]
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- GPU-accelerated Time Simulation of Systems with Adaptive Voltage and Frequency ScalingEric Schneider, Hans-Joachim Wunderlich. 879-884 [doi]
- Lazy Event Prediction using Defining Trees and Schedule Bypass for Out-of-Order PDESDaniel Mendoza, Zhongqi Cheng, Emad Arasteh, Rainer Dömer. 885-890 [doi]
- Embedding Hierarchical Signal to Siamese Network for Fast Name RectificationYi-An Chen, Gung-Yu Pan, Che-Hua Shih, Yen-Chin Liao, Chia-Chih Yen, Hsie-Chia Chang. 891-896 [doi]
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- Energy-efficient Runtime Resource Management for Adaptable Multi-application MappingRobert Khasanov, Jerónimo Castrillón. 909-914 [doi]
- Sweeping for Leakage in Masked Circuit LayoutsDanilo Sijacic, Josep Balasch, Ingrid Verbauwhede. 915-920 [doi]
- Increased reproducibility and comparability of data leak evaluations using ExOTPhilipp Miedl, Bruno Klopott, Lothar Thiele. 921-926 [doi]
- GhostBusters: Mitigating Spectre Attacks on a DBT-Based ProcessorSimon Rokicki. 927-932 [doi]
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- Oracle-based Logic Locking Attacks: Protect the Oracle Not Only the NetlistEmmanouil Kalligeros, Nikolaos Karousos, Irene G. Karybali. 939-944 [doi]
- AnytimeNet: Controlling Time-Quality Tradeoffs in Deep Neural Network ArchitecturesJung-Eun Kim, Richard M. Bradford, Zhong Shao. 945-950 [doi]
- AntiDote: Attention-based Dynamic Optimization for Neural Network Runtime EfficiencyFuxun Yu, Chenchen Liu, Di Wang, Yanzhi Wang, Xiang Chen 0010. 951-956 [doi]
- Using Learning Classifier Systems for the DSE of Adaptive Embedded SystemsFedor Smirnov, Behnaz Pourmohseni, Jürgen Teich. 957-962 [doi]
- CNT-Cache: an Energy-Efficient Carbon Nanotube Cache with Adaptive EncodingDawen Xu 0002, Kexin Chu, Cheng Liu, Ying Wang, Lei Zhang, Huawei Li. 963-966 [doi]
- Enhancing Multithreaded Performance of Asymmetric Multicores with SIMD OffloadingJeckson Dellagostin Souza, Madhavan Manivannan, Miquel Pericàs, Antonio Carlos Schneider Beck. 967-970 [doi]
- Hardware Acceleration of CNN with One-Hot Quantization of Weights and ActivationsGang Li 0015, Peisong Wang, Zejian Liu, Cong Leng, Jian Cheng. 971-974 [doi]
- BNNsplit: Binarized Neural Networks for embedded distributed FPGA-based computing systemsGiorgia Fiscaletti, Marco Speziali, Luca Stornaiuolo, Marco D. Santambrogio, Donatella Sciuto. 975-978 [doi]
- L2L: A Highly Accurate Log_2_Lead Quantization of Pre-trained Neural NetworksSalim Ullah, Siddharth Gupta, Kapil Ahuja, Aruna Tiwari, Akash Kumar 0001. 979-982 [doi]
- Fault Diagnosis of Via-Switch Crossbar in Non-volatile FPGARyutaro Doi, Xu Bai, Toshitsugu Sakamoto, Masanori Hashimoto. 983-986 [doi]
- Applying Reservation-based Scheduling to a μC-based Hypervisor: An industrial case studyDakshina Dasari, Michael Pressler, Arne Hamann, Dirk Ziegenbein, Paul Austin. 987-990 [doi]
- Real-Time Energy Monitoring in IoT-enabled Mobile DevicesNitin Shivaraman, Seima Saki, Zhiwei Liu, Saravanan Ramanathan, Arvind Easwaran, Sebastian Steinhorst. 991-994 [doi]
- ⋆Vladimir Herdt, Daniel Große, Rolf Drechsler. 995-998 [doi]
- Post-Silicon Validation of the IBM POWER9 ProcessorTom Kolan, Hillel Mendelson, Vitali Sokhin, Kevin Reick, Elena Tsanko, Greg Wetli. 999-1002 [doi]
- On the Task Mapping and Scheduling for DAG-based Embedded Vision Applications on Heterogeneous Multi/Many-core ArchitecturesStefano Aldegheri, Nicola Bombieri, Hiren D. Patel. 1003-1006 [doi]
- Are Cloud FPGAs Really Vulnerable to Power Analysis Attacks?Ognjen Glamocanin, Louis Coulon, Francesco Regazzoni 0001, Mirjana Stojilovic. 1007-1010 [doi]
- Efficient Training on Edge Devices Using Online QuantizationMichael H. Ostertag, Sarah Al-Doweesh, Tajana Rosing. 1011-1014 [doi]
- Multi-Agent Actor-Critic Method for Joint Duty-Cycle and Transmission Power ControlSota Sawaguchi, Jean-Frédéric Christmann, Anca Molnos, Carolynn Bernier, Suzanne Lesecq. 1015-1018 [doi]
- An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar ArraysShruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran. 1019-1024 [doi]
- Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging MemoriesShanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu. 1025-1030 [doi]
- Automated Test Generation for Trojan Detection using Delay-based Side Channel AnalysisYangdi Lyu, Prabhat Mishra 0001. 1031-1036 [doi]
- Microfluidic Trojan Design in Flow-based BiochipsMohammed Shayan, Sukanta Bhattacharjee, Yong-Ak Song, Krishnendu Chakrabarty, Ramesk Karri. 1037-1042 [doi]
- Towards Malicious Exploitation of Energy Management MechanismsSafouane Noubir, Maria Mendez Real, Sébastien Pillement. 1043-1048 [doi]
- ESP4ML: Platform-Based Design of Systems-on-Chip for Embedded Machine LearningDavide Giri, Kuan-Lin Chiu, Giuseppe Di Guglielmo, Paolo Mantovani, Luca P. Carloni. 1049-1054 [doi]
- Probabilistic Sequential Multi-Objective Optimization of Convolutional Neural NetworksZixuan Yin, Warren J. Gross, Brett H. Meyer. 1055-1060 [doi]
- ARS: Reducing F2FS Fragmentation for Smartphones using Decision TreesLihua Yang, Fang Wang, Zhipeng Tan, Dan Feng, Jiaxing Qian, Shiyun Tu. 1061-1066 [doi]
- TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRERohit Prasad, Satyajit Das, Kevin J. M. Martin, Giuseppe Tagliavini, Philippe Coussy, Luca Benini, Davide Rossi. 1067-1072 [doi]
- Modeling and Designing of a PVT Auto-tracking Timing-speculative SRAMShan Shen, Tianxiang Shao, Ming Ling, Jun Yang, Longxing Shi. 1073-1078 [doi]
- Solving Constraint Satisfaction Problems Using the Loihi Spiking Neuromorphic ProcessorChris Yakopcic, Nayim Rahman, Tanvir Atahary, Tarek M. Taha, Scott Douglass. 1079-1084 [doi]
- Accurate Power Density Map Estimation for Commercial Multi-Core MicroprocessorsJinwei Zhang, Sheriff Sadiqbatcha, Wentian Jin, Sheldon X.-D. Tan. 1085-1090 [doi]
- Analysis and Solution of CNN Accuracy Reduction over Channel Loop TilingYesung Kang, Yoonho Park, Sunghoon Kim, Eunji Kwon, Taeho Lim, Sangyun Oh, Mingyu Woo, Seokhyeong Kang. 1091-1096 [doi]
- DC-CNN: Computational Flow Redefinition for Efficient CNN through Structural DecouplingFuxun Yu, Zhuwei Qin, Di Wang, Ping Xu, Chenchen Liu, Zhi Tian, Xiang Chen. 1097-1102 [doi]
- ABC: Abstract prediction Before ConcretenessJung-Eun Kim, Richard M. Bradford, Man-Ki Yoon, Zhong Shao. 1103-1108 [doi]
- A compositional approach using Keras for neural networks in real-time systemsXin Yang, Partha S. Roop, Hammond A. Pearce, Jin Woo Ro. 1109-1114 [doi]
- rACE: Reverse-Order Processor Reliability AnalysisAthanasios Chatzidimitriou, Dimitris Gizopoulos. 1115-1120 [doi]
- DEFCON: Generating and Detecting Failure-prone Instruction Sequences via Stochastic SearchIoannis Tsiokanos, Lev Mukhanov, Giorgis Georgakoudis, Dimitrios S. Nikolopoulos, Georgios Karakonstantis. 1121-1126 [doi]
- LAD-ECC: Energy-Efficient ECC Mechanism for GPGPUs Register FileXiaohui Wei, Hengshan Yue, Jingweijia Tan. 1127-1132 [doi]
- Floating Random Walk Based Capacitance Solver for VLSI Structures with Non-Stratified DielectricsMingye Song, Ming Yang, Wenjian Yu. 1133-1138 [doi]
- Making the Relationship between Uncertainty Estimation and Safety Less UncertainVincent Aravantinos, Peter Schlicht. 1139-1144 [doi]
- Towards Serial-Equivalent Multi-Core Parallel Routing for FPGAsMinghua Shen, Nong Xiao. 1139-1144 [doi]
- Self-Aligned Double-Patterning Aware LegalizationHua Xiang, Gi-Joon Nam, Gustavo E. Téllez, Shyam Ramji, Xiaoqing Xu. 1145-1150 [doi]
- Explainable DRC Hotspot Prediction with Random Forest and SHAP Tree ExplainerWei Zeng, Azadeh Davoodi, Rasit Onur Topaloglu. 1151-1156 [doi]
- Study on the Compensation of Silicon Photonics-Based Modulators in DCI ApplicationsNaim Ben Hamida, Ahmad Abdo, Xueyang Li, Md Samiul Alam, Mahdi Parvizi, Claude D'Amours, David V. Plant. 1157-1162 [doi]
- DeepRacing: A Framework for Autonomous RacingTrent Weiss, Madhur Behl. 1163-1168 [doi]
- Fail-Operational Automotive Software Design Using Agent-Based Graceful DegradationPhilipp Weiss, Andreas Weichslgartner, Felix Reimann, Sebastian Steinhorst. 1169-1174 [doi]
- A Distributed Safety Mechanism using Middleware and Hypervisors for Autonomous VehiclesTjerk Bijlsma, Andrii Buriachevskyi, Alessandro Frigerio, Yuting Fu, Kees Goossens, Ali Osman Örs, Pieter J. van der Perk, Andrei Sergeevich Terechko, Bart Vermeulen. 1175-1180 [doi]
- Fledge: Flexible Edge Platforms Enabled by In-memory ComputingKamalika Datta, Arko Dutt, Ahmed Zaky, Umesh Chand, Devendra Singh, Yida Li, Jackson Chun-Yang Huang, Aaron Thean, Mohamed M. Sabry Aly. 1181-1186 [doi]
- Computational SRAM Design Automation using Pushed-Rule Bitcells for Energy-Efficient Vector ProcessingJean-Philippe Noël, V. Egloff, Maha Kooli, R. Gauchi, Jean Michel Portal, H.-P. Charles, Pascal Vivet, Bastien Giraud. 1187-1192 [doi]
- ProxSim: GPU-based Simulation Framework for Cross-Layer Approximate DNN OptimizationCecilia De la Parra, Andre Guntoro, Akash Kumar. 1193-1198 [doi]
- PCM: Precision-Controlled Memory System for Energy Efficient Deep Neural Network TrainingBoyeal Kim, Sang Hyun Lee, Hyun Kim, Duy Thanh Nguyen, Minh-Son Le, Ik Joon Chang, Dohun Kwon, Jin Hyeok Yoo, Jun Won Choi, Hyuk-Jae Lee. 1199-1204 [doi]
- ReD-CaNe: A Systematic Methodology for Resilience Analysis and Design of Capsule Networks under ApproximationsAlberto Marchisio, Vojtech Mrazek, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 1205-1210 [doi]
- Impact of Magnetic Coupling and Density on STT-MRAM PerformanceLizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui. 1211-1216 [doi]
- High-Density, Low-Power Voltage-Control Spin Orbit Torque Memory with Synchronous Two-Step Write and Symmetric Read TechniquesHaotian Wang, Wang Kang, Liuyang Zhang, He Zhang, Brajesh Kumar Kaushik, Weisheng Zhao. 1217-1222 [doi]
- Design of Almost-Nonvolatile Embedded DRAM Using Nanoelectromechanical Relay DevicesHongtao Zhong, Mingyang Gu, Juejian Wu, Huazhong Yang, Xueqing Li. 1223-1228 [doi]
- Thermal-Cycling-aware Dynamic Reliability Management in Many-Core System-on-ChipMohammad Hashem Haghbayan, Antonio Miele, Zhuo Zou, Hannu Tenhunen, Juha Plosila. 1229-1234 [doi]
- Deterministic Cache-based Execution of On-line Self-Test Routines in Multi-core Automotive System-on-ChipsAndrea Floridia, Tzamn Melendez Carmona, Davide Piumatti, Annachiara Ruospo, Ernesto Sánchez 0001, Sergio de Luca, Rosario Martorana, Mose Alessandro Pernice. 1235-1240 [doi]
- FT-ClipAct: Resilience Analysis of Deep Neural Networks and Improving their Fault Tolerance using Clipped ActivationLe Ha Hoang, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 1241-1246 [doi]
- Q-learning Based Backup for Energy Harvesting Powered Embedded SystemsWei Fan, Yujie Zhang, Weining Song, Mengying Zhao, Zhaoyan Shen, Zhiping Jia. 1247-1252 [doi]
- A Novel TIGFET-based DFF Design for Improved Resilience to Power Side-Channel AttacksMohammad Mehdi Sharifi, Ramin Rajaei, Patsy Cadareanu, Pierre-Emmanuel Gaillardon, Yier Jin, Michael T. Niemier, Xiaobo Sharon Hu. 1253-1258 [doi]
- Low Complexity Multi-directional In-Air Ultrasonic Gesture Recognition Using a TCNEmad A. Ibrahim, Marc Geilen, Jos Huisken, Min Li, José Pineda de Gyvez. 1259-1264 [doi]
- PIM-Aligner: A Processing-in-MRAM Platform for Biological Sequence AlignmentShaahin Angizi, Jiao Sun, Wei Zhang, Deliang Fan. 1265-1270 [doi]
- HIT: A Hidden Instruction Trojan Model for ProcessorsJiaqi Zhang, Ying Zhang 0040, Huawei Li, Jianhui Jiang. 1271-1274 [doi]
- Bitstream Modification Attack on SNOW 3GMichail Moraitis, Elena Dubrova. 1275-1278 [doi]
- A Machine Learning Based Write Policy for SSD Cache in Cloud Block StorageYu Zhang, Ke Zhou, Ping Huang, Hua Wang, Jianying Hu, Yangtao Wang, Yongguang Ji, Bin Cheng. 1279-1282 [doi]
- You Only Search Once: A Fast Automation Framework for Single-Stage DNN/Accelerator Co-designWeiwei Chen, Ying Wang, Shuang Yang, Chen Liu, Lei Zhang. 1283-1286 [doi]
- When Sorting Network Meets Parallel Bitstreams: A Fault-Tolerant Parallel Ternary Neural Network Accelerator based on Stochastic ComputingYawen Zhang, Sheng Lin, Runsheng Wang, Yanzhi Wang, Yuan Wang 0001, Weikang Qian, Ru Huang. 1287-1290 [doi]
- WavePro: Clock-less Wave-Propagated Pipeline Compiler for Low-Power and High-Throughput ComputationYehuda Kra, Tzachi Noy, Adam Teman. 1291-1294 [doi]
- DeepNVM: A Framework for Modeling and Analysis of Non-Volatile Memory Technologies for Deep Learning ApplicationsAhmet Fatih Inci, Mehmet Meric Isgenc, Diana Marculescu. 1295-1298 [doi]
- Efficient Embedded Machine Learning applications using Echo State NetworksLuca Cerina, Marco D. Santambrogio, G. Franco, Claudio Gallicchio, Alessio Micheli. 1299-1302 [doi]
- ExplFrame: Exploiting Page Frame Cache for Fault Analysis of Block CiphersAnirban Chakraborty, Sarani Bhattacharya, Sayandeep Saha, Debdeep Mukhopadhyay. 1303-1306 [doi]
- XGBIR: An XGBoost-based IR Drop Predictor for Power Delivery NetworkChi-Hsien Pao, An-Yu Su, Yu-Min Lee. 1307-1310 [doi]
- On Pre-Assignment Route Prototyping for Irregular Bumps on BGA PackagesJyun-Ru Jiang, Yun-Chih Kuo, Simon Yi-Hung Chen, Hung-Ming Chen. 1311-1314 [doi]
- Towards Best-effort Approximation: Applying NAS to General-purpose Approximate ComputingWeiwei Chen, Ying Wang, Shuang Yang, Chen Liu, Lei Zhang. 1315-1318 [doi]
- On the Automatic Exploration of Weight Sharing for Deep Neural Network CompressionEtienne Dupuis, David Novo, Ian O'Connor, Alberto Bosio. 1319-1322 [doi]
- Robust and High-Performance 12-T Interlocked SRAM for In-Memory ComputingNeelam Surana, Mili Lavania, Abhishek Barma, Joycee Mekie. 1323-1326 [doi]
- High Density STT-MRAM compiler design, validation and characterization methodology in 28nm FDSOI technologyPiyush Jain, Akshay Kumar, Nicolaas Van Winkelhoff, Didier Gayraud, Surya Gupta, Abdelali El Amraoui, Giorgio Palma, Alexandra Gourio, Laurent Vachez, Luc Palau, Jean-Christophe Buy, Cyrille Dray. 1327-1330 [doi]
- An Approximation-based Fault Detection Scheme for Image Processing ApplicationsMatteo Biasielli, Luca Cassano, Antonio Miele. 1331-1334 [doi]
- Transport-Free Module Binding for Sample Preparation using Microfluidic Fully Programmable Valve ArraysGautam Choudhary, Sandeep Pal, Debraj Kundu, Sukanta Bhattacharjee, Shigeru Yamashita, Bing Li 0005, Ulf Schlichtmann, Sudip Roy 0001. 1335-1338 [doi]
- System Theoretic View on UncertaintiesRoman Gansch, Ahmad Adee. 1345-1350 [doi]
- Detection of False Positive and False Negative Samples in Semantic SegmentationMatthias Rottmann, Kira Maag, Robin Chan, Fabian Hüger, Peter Schlicht, Hanno Gottschalk. 1351-1356 [doi]
- Next Generation Arithmetic for Edge ComputingAndre Guntoro, Cecilia De la Parra, Farhad Merchant, Florent de Dinechin, John L. Gustafson, Martin Langhammer, Rainer Leupers, Sangeeth Nambiar. 1357-1365 [doi]
- REALM: Reduced-Error Approximate Log-based Integer MultiplierHassaan Saadat, Haris Javaid, Aleksandar Ignjatovic, Sri Parameswaran. 1366-1371 [doi]
- A fast BDD Minimization Framework for Approximate ComputingAndreas Wendler, Oliver Keszöcze. 1372-1377 [doi]
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- Fast Kriging-based Error Evaluation for Approximate Computing SystemsJustine Bonnot, Daniel Ménard, Karol Desnos. 1384-1389 [doi]
- Communication-efficient View-Pooling for Distributed Multi-View Neural NetworksManik Singhal, Vijay Raghunathan, Anand Raghunathan. 1390-1395 [doi]
- An Anomaly Comprehension Neural Network for Surveillance Videos on Terminal DevicesYuan Cheng, Guangtai Huang, Peining Zhen, Bin Liu, Hai-Bao Chen, Ngai Wong, Hao Yu. 1396-1401 [doi]
- BYNQNet: Bayesian Neural Network with Quadratic Activations for Sampling-Free Uncertainty Estimation on FPGAHiromitsu Awano, Masanori Hashimoto. 1402-1407 [doi]
- Capturing and Obscuring Ping-Pong Patterns to Mitigate Continuous AttacksKai Wang, Fengkai Yuan, Rui Hou, Zhenzhou Ji, Dan Meng. 1408-1413 [doi]
- Mitigating Cache-Based Side-Channel Attacks through Randomization: A Comprehensive System and Architecture Level AnalysisHan Wang, Hossein Sayadi, Tinoosh Mohsenin, Liang Zhao 0002, Avesta Sasan, Setareh Rafatirad, Houman Homayoun. 1414-1419 [doi]
- Extending the RISC-V Instruction Set for Hardware Acceleration of the Post-Quantum Scheme LACTim Fritzmann, Georg Sigl, Johanna Sepúlveda. 1420-1425 [doi]
- A Pulse-width Modulation Neuron with Continuous Activation for Processing-In-Memory EnginesShuhang Zhang, Bing Li 0005, Hai Helen Li, Ulf Schlichtmann. 1426-1431 [doi]
- Go Unary: A Novel Synapse Coding and Mapping Scheme for Reliable ReRAM-based Neuromorphic ComputingChang Ma, Yanan Sun, Weikang Qian, Ziqi Meng, Rui Yang, Li Jiang 0002. 1432-1437 [doi]
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- System-level Evaluation of Chip-Scale Silicon Photonic Networks for Emerging Data-Intensive ApplicationsAditya Narayan, Yvain Thonnart, Pascal Vivet, Ajay Joshi, Ayse K. Coskun. 1444-1449 [doi]
- OSCAR: An Optical Stochastic Computing AcceleRator for Polynomial FunctionsHassnaa El-Derhalli, Sébastien Le Beux, Sofiène Tahar. 1450-1455 [doi]
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- Emerging Neural Workloads and Their Impact on HardwareDavid Brooks 0001, Martin M. Frank, Tayfun Gokmen, Udit Gupta, Xiaobo Sharon Hu, Shubham Jain, Ann Franchesca Laguna, Michael T. Niemier, Ian O'Connor, Anand Raghunathan, Ashish Ranjan, Dayane Reis, Jacob R. Stevens, Carole-Jean Wu, Xunzhao Yin. 1462-1471 [doi]
- ReBoc: Accelerating Block-Circulant Neural Networks in ReRAMYitu Wang, Fan Chen, Linghao Song, C.-J. Richard Shi, Hai Helen Li, Yiran Chen. 1472-1477 [doi]
- GraphRSim: A Joint Device-Algorithm Reliability Analysis for ReRAM-based Graph ProcessingChin-Fu Nien, Yi-Jou Hsiao, Hsiang-Yun Cheng, Cheng-yu Wen, Ya-Cheng Ko, Che-Ching Lin. 1478-1483 [doi]
- STAIR: High Reliable STT-MRAM Aware Multi-Level I/O Cache Architecture by Adaptive ECC AllocationMostafa Hadizadeh, Elham Cheshmikhani, Hossein Asadi. 1484-1489 [doi]
- Effective Write Disturbance Mitigation Encoding Scheme for High-density PCMMuhammad Imran, TaeHyun Kwon, Joon-Sung Yang. 1490-1495 [doi]
- Unified Thread- and Data-Mapping for Multi-Threaded Multi-Phase Applications on SPM Many-CoresVanchinathan Venkataramani, Anuj Pathania, Tulika Mitra. 1496-1501 [doi]
- Generalized Data Placement Strategies for Racetrack MemoriesAsif Ali Khan, Andrés Goens, Fazal Hameed, Jerónimo Castrillón. 1502-1507 [doi]
- ARM-on-ARM: Leveraging Virtualization Extensions for Fast Virtual PlatformsLukas Jünger, Jan Luca Malte Bölke, Stephan Tobies, Rainer Leupers, Andreas Hoffmann 0002. 1508-1513 [doi]
- Impact of NBTI Aging on Self-Heating in Nanowire FETOm Prakash, Hussam Amrouch, Sanjeev Manhas, Jörg Henkel. 1514-1519 [doi]
- PowerPlanningDL: Reliability-Aware Framework for On-Chip Power Grid Design using Deep LearningSukanta Dey, Sukumar Nandi, Gaurav Trivedi. 1520-1525 [doi]
- An Efficient MILP-Based Aging-Aware Floorplanner for Multi-Context Coarse-Grained Runtime Reconfigurable FPGAsBo Hu, Mustafa M. Shihab, Yiorgos Makris, Benjamin Carrión Schäfer, Carl Sechen. 1526-1531 [doi]
- AMSA: Adaptive Merkle Signature ArchitectureEmanuel Regnath, Sebastian Steinhorst. 1532-1537 [doi]
- DISSECT: Dynamic Skew-and-Split Tree for Memory AuthenticationSaru Vig, Rohan Juneja, Siew Kei Lam. 1538-1543 [doi]
- Design-flow Methodology for Secure Group Anonymous AuthenticationRashmi Agrawal, Lake Bu, Eliakin Del Rosario, Michel A. Kinsy. 1544-1549 [doi]
- Embedded Social Insect-Inspired Intelligence Networks for System-level Runtime ManagementMatthew R. P. Rowlings, Andy M. Tyrrell, Martin A. Trefzer. 1550-1555 [doi]
- Optimising Resource Management for Embedded Machine LearningLei Xun, Long Tran-Thanh, Bashir M. Al-Hashimi, Geoff V. Merrett. 1556-1561 [doi]
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- Statistical Model Checking of Approximate Circuits: Challenges and OpportunitiesJosef Strnadel. 1574-1577 [doi]
- Runtime Accuracy-Configurable Approximate Hardware Synthesis Using Logic Gating and RelaxationTanfer Alan, Andreas Gerstlauer, Jörg Henkel. 1578-1581 [doi]
- Post-Quantum Secure BootVinay B. Y. Kumar, Naina Gupta 0001, Anupam Chattopadhyay, Michael Kasper, Christoph Krauß, Ruben Niederhagen. 1582-1585 [doi]
- ROQ: A Noise-Aware Quantization Scheme Towards Robust Optical Neural Networks with Low-bit ControlsJiaqi Gu, Zheng Zhao, Chenghao Feng, Hanqing Zhu, Ray T. Chen, David Z. Pan. 1586-1589 [doi]
- Statistical Training for Neuromorphic Computing using Memristor-based Crossbars Considering Process Variations and NoiseYing Zhu, Grace Li Zhang, Tianchen Wang, Bing Li 0005, Yiyu Shi, Tsung-Yi Ho, Ulf Schlichtmann. 1590-1593 [doi]
- Computational Restructuring: Rethinking Image Processing using Memristor Crossbar ArraysBaogang Zhang, Necati Uysal, Rickard Ewetz. 1594-1597 [doi]
- SCRIMP: A General Stochastic Computing Architecture using ReRAM in-Memory ProcessingSaransh Gupta, Mohsen Imani, Joonseop Sim, Andrew Huang 0001, Fan Wu, M. Hassan Najafi, Tajana Rosing. 1598-1601 [doi]
- TDO-CIM: Transparent Detection and Offloading for Computation In-memoryKanishkan Vadivel, Lorenzo Chelini, Ali BanaGozar, Gagandeep Singh, Stefano Corda, Roel Jordans, Henk Corporaal. 1602-1605 [doi]
- BackFlow: Backward Edge Control Flow Enforcement for Low End ARM MicrocontrollersCyril Bresch, Roman Lysecky, David Hély. 1606-1609 [doi]
- Delay Sensitivity Polynomials Based Design- Dependent Performance Monitors for Wide Operating RangesRuikai Shi, Liang Yang, Hao Wang. 1610-1613 [doi]
- Mitigation of Sense Amplifier Degradation Using Skewed DesignDaniel Kraak, Mottaqiallah Taouil, Said Hamdioui, Pieter Weckx, Stefan Cosemans, Francky Catthoor. 1614-1617 [doi]
- Blockchain Technology Enabled Pay Per Use Licensing Approach for Hardware IPsKrishnendu Guha, Debasri Saha, Amlan Chakrabarti. 1618-1621 [doi]
- Opportunities for Cross-Layer Design in High-Performance Computing Systems with Integrated Silicon Photonic NetworksAsif Mirza, Shadi Manafi Avari, Ebadollah Taheri, Sudeep Pasricha, Mahdi Nikdast. 1622-1627 [doi]
- Efficient Optical Power Delivery System for Hybrid Electronic-Photonic Manycore ProcessorsShixi Chen, Jiang Xu 0001, Xuanqi Chen, Zhifei Wang, Jun Feng, Jiaxu Zhang, Zhongyuan Tian, Xiao Li. 1628-1633 [doi]
- A Preliminary View on Automotive Cyber Security Management SystemsChristoph Schmittner, Jürgen Dobaj, Georg Macher, Eugen Brenner. 1634-1639 [doi]
- Towards Safety Verification of Direct Perception Neural NetworksChih-Hong Cheng, Chung-Hao Huang, Thomas Brunner, Vahid Hashemi. 1640-1643 [doi]
- Minimizing Execution Duration in the Presence of Learning-Enabled ComponentsKunal Agrawal, Alan Burns, Abhishek Singh, Sanjoy Baruah. 1644-1649 [doi]
- Exploration of Memory Access Optimization for FPGA-based 3D CNN AcceleratorTeng Tian, Xi Jin, Letian Zhao, Xiaotian Wang, Jie Wang, Wei Wu. 1650-1655 [doi]
- A Throughput-Latency Co-Optimised Cascade of Convolutional Neural Network ClassifiersAlexandros Kouris, Stylianos I. Venieris, Christos-Savvas Bouganis. 1656-1661 [doi]
- OrthrusPE: Runtime Reconfigurable Processing Elements for Binary Neural NetworksNael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Walter Stechele. 1662-1667 [doi]
- Towards Generic and Scalable Word-Length OptimizationVan-Phu Ha, Tomofumi Yuki, Olivier Sentieys. 1668-1673 [doi]
- Trading Sensitivity for Power in an IEEE 802.15.4 Conformant Adequate DemodulatorPaul Detterer, Cumhur Erdin, Jos Huisken, Hailong Jiao, Majid Nabi, Twan Basten, José Pineda de Gyvez. 1674-1679 [doi]
- Approximation Trade Offs in an Image-Based Control SystemSayandip De, Sajid Mohamed, Konstantinos Bimpisidis, Dip Goswami, Twan Basten, Henk Corporaal. 1680-1685 [doi]
- CPS-oriented Modeling and Control of Traffic Signals Using Adaptive Back PressureWanli Chang, Debayan Roy, Shuai Zhao 0004, Anuradha Annaswamy, Samarjit Chakraborty. 1686-1691 [doi]
- Network Synthesis for Industry 4.0Enrico Fraccaroli, Alan Michael Padovani, Davide Quaglia, Franco Fummi. 1692-1697 [doi]
- Production Recipe Validation through Formalization and Digital Twin GenerationStefano Spellini, Roberta Chirico, Marco Panato, Michele Lora, Franco Fummi. 1698-1703 [doi]
- Parallel Implementation of Iterative Learning Controllers on Multi-core PlatformsMojtaba Haghi, Yusheng Yao, Dip Goswami, Kees Goossens. 1704-1709 [doi]
- Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect DiagnosisKen Chau-Cheung Cheng, Katherine Shu-Min Li, Andrew Yi-Ann Huang, Ji-Wei Li, Leon Li-Yang Chen, Nova Cheng-Yen Tsai, Sying-Jyan Wang, Chen-Shiun Lee, Leon Chou, Peter Yi-Yu Liao, Hsing-Chung Liang, Jwu E. Chen. 1710-1711 [doi]
- A Method of Via Variation Induced Delay ComputationMoonsu Kim, Yun Heo, Seungjae Jung, Kelvin Le, Nathaniel Conos, Hanif Fatemi, Jongpil Lee, Youngmin Shin. 1712-1713 [doi]
- Fully Automated Analog Sub-Circuit Clustering with Graph Convolutional Neural NetworksKeertana Settaluri, Elias Fallon. 1714-1715 [doi]
- EVPS: An Automotive Video Acquisition and Processing PlatformChristophe Flouzat, Erwan Piriou, Mickaël Guibert, Bojan Jovanovic, Mohamad Oussayran. 1716-1717 [doi]
- An On-board Algorithm Implementation on an Embedded GPU: A Space Case StudyIván Rodriguez, Leonidas Kosmidis, Olivier Notebaert, Francisco J. Cazorla, David Steenari. 1718-1719 [doi]
- TLS-Level Security for Low Power Industrial IoT Network InfrastructuresJochen Mades, Gerd Ebelt, Boris Janjic, Frederik Lauer, Carl Christian Rheinländer, Norbert Wehn. 1720-1721 [doi]
- Tuning the ISA for increased heterogeneous computation in MPSoCsPedro Henrique Exenberger Becker, Jeckson Dellagostin Souza, Antonio C. S. Beck. 1722-1727 [doi]
- User Interaction Aware Reinforcement Learning for Power and Thermal Efficiency of CPU-GPU Mobile MPSoCsSomdip Dey, Amit Kumar Singh, Xiaohang Wang, Klaus D. McDonald-Maier. 1728-1733 [doi]
- Energy-Efficient Two-level Instruction Cache Design for an Ultra-Low-Power Multi-core ClusterChen Jie, Igor Loi, Luca Benini, Davide Rossi. 1734-1739 [doi]
- M3D-ADTCO: Monolithic 3D Architecture, Design and Technology Co-Optimization for High Energy Efficient 3D ICSebastien Thuries, Olivier Billoint, Sylvain Choisnet, Romain Lemaire, Pascal Vivet, Perrine Batude, Didier Lattard. 1740-1745 [doi]
- *Shao-Chun Hung, Krishnendu Chakrabarty. 1746-1751 [doi]
- Power, Performance, and Thermal Trade-offs in M3D-enabled Manycore ChipsShouvik Musavvir, Anwesha Chatterjee, Ryan Gary Kim, Dae-Hyun Kim, Janardhan Rao Doppa, Partha Pratim Pande. 1752-1757 [doi]