Xiaochen Peng - researchr alias

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Viewing Publication 1 - 44 from 44

2024

Non-volatile Memory Technologies for Edge AI ApplicationsXiaoyu Sun 0001, Win-San Khwa, Xiaochen Peng, Meng-Fan Chang, Kerem Akarvardar. iccad 2024: [doi]

Estimating Power, Performance, and Area for On-Sensor Deployment of AR/VR Workloads Using an Analytical FrameworkXiaoyu Sun 0001, Xiaochen Peng, Sai Qian Zhang, Jorge Gomez 0002, Win-San Khwa, Syed Shakib Sarwar, Ziyun Li, Weidong Cao, Zhao Wang, Chiao Liu, Meng-Fan Chang, Barbara De Salvo, Kerem Akarvardar, H.-S. Philip Wong. todaes, 29(6):1-27, 2024. [doi]

Co-Optimization for Robust Power Delivery Design in 3D-Heterogeneous Integration of Compute In-Memory AcceleratorsAnkit Kaul, Madison Manley, James Read, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir. vlsit 2024: 1-2 [doi]

2022

Achieving High In Situ Training Accuracy and Energy Efficiency with Analog Non-Volatile Synaptic DevicesShanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu. todaes, 27(4), 2022. [doi]

Benchmark Framework for 2-D/3-D Integrated Compute-in-Memory Based Machine Learning AcceleratorXiaochen Peng. PhD thesis, Georgia Institute of Technology, Atlanta, GA, USA, 2022. [doi]

2021

Exploiting Process Variations to Protect Machine Learning Inference Engine from Chip CloningShanshi Huang, Xiaochen Peng, Hongwu Jiang, Yandong Luo, Shimeng Yu. iscas 2021: 1-5 [doi]

Secure XOR-CIM Engine: Compute-In-Memory SRAM Architecture With Embedded XOR EncryptionShanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu. tvlsi, 29(12):2027-2039, 2021. [doi]

Thermal Reliability Considerations of Resistive Synaptic Devices for 3D CIM System PerformanceAnkit Kaul, Yandong Luo, Xiaochen Peng, Shimeng Yu, Muhannad S. Bakir. 3dic 2021: 1-5 [doi]

NeuroSim Validation with 40nm RRAM Compute-in-Memory MacroAnni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu. aicas 2021: 1-4 [doi]

Compute-in-RRAM with Limited On-chip ResourcesAnni Lu, Xiaochen Peng, Shimeng Yu. aicas 2021: 1-4 [doi]

A Runtime Reconfigurable Design of Compute-in-Memory based Hardware AcceleratorAnni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu. date 2021: 932-937 [doi]

A Runtime Reconfigurable Design of Compute-in-Memory-Based Hardware Accelerator for Deep Learning InferenceAnni Lu, Xiaochen Peng, Yandong Luo, Shanshi Huang, Shimeng Yu. todaes, 26(6), 2021. [doi]

NeuroSim Simulator for Compute-in-Memory Hardware Accelerator: Validation and BenchmarkAnni Lu, Xiaochen Peng, Wantong Li, Hongwu Jiang, Shimeng Yu. frai, 4:659060, 2021. [doi]

Structured Pruning of RRAM Crossbars for Efficient In-Memory Computing Acceleration of Deep Neural NetworksJian Meng, Li Yang, Xiaochen Peng, Shimeng Yu, Deliang Fan, Jae-sun Seo. tcasII, 68(5):1576-1580, 2021. [doi]

DNN+NeuroSim V2.0: An End-to-End Benchmarking Framework for Compute-in-Memory Accelerators for On-Chip TrainingXiaochen Peng, Shanshi Huang, Hongwu Jiang, Anni Lu, Shimeng Yu. tcad, 40(11):2306-2319, 2021. [doi]

Impact of Multilevel Retention Characteristics on RRAM based DNN Inference EngineWonbo Shim, Jian Meng, Xiaochen Peng, Jae-sun Seo, Shimeng Yu. irps 2021: 1-4 [doi]

Cryogenic Performance for Compute-in-Memory Based Deep Neural Network AcceleratorPanni Wang, Xiaochen Peng, Wriddhi Chakraborty, Asif Khan, Suman Datta, Shimeng Yu. iscas 2021: 1-4 [doi]

Compute-in-Memory: From Device Innovation to 3D System IntegrationShimeng Yu, Wonbo Shim, Jae Hur, Yuan-Chun Luo, Gihun Choe, Wantong Li, Anni Lu, Xiaochen Peng. essderc 2021: 21-28 [doi]

RRAM for Compute-in-Memory: From Inference to TrainingShimeng Yu, Wonbo Shim, Xiaochen Peng, Yandong Luo. tcasI, 68(7):2753-2765, 2021. [doi]

2020

Overcoming Challenges for Achieving High in-situ Training Accuracy with Emerging MemoriesShanshi Huang, Xiaoyu Sun, Xiaochen Peng, Hongwu Jiang, Shimeng Yu. date 2020: 1025-1030 [doi]

XOR-CIM: Compute-In-Memory SRAM Architecture with Embedded XOR EncryptionShanshi Huang, Hongwu Jiang, Xiaochen Peng, Wantong Li, Shimeng Yu. iccad 2020: 1-6 [doi]

MINT: Mixed-Precision RRAM-Based IN-Memory Training ArchitectureHongwu Jiang, Shanshi Huang, Xiaochen Peng, Shimeng Yu. iscas 2020: 1-5 [doi]

CIMAT: A Compute-In-Memory Architecture for On-chip Training Based on Transpose SRAM ArraysHongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu. TC, 69(7):944-954, 2020. [doi]

A Two-way SRAM Array based Accelerator for Deep Neural Network On-chip TrainingHongwu Jiang, Shanshi Huang, Xiaochen Peng, Jian-Wei Su, Yen-Chi Chou, Wei-Hsing Huang, Ta-Wei Liu, Ruhui Liu, Meng-Fan Chang, Shimeng Yu. dac 2020: 1-6 [doi]

Benchmark of the Compute-in-Memory-Based DNN Accelerator With Area ConstraintAnni Lu, Xiaochen Peng, Yandong Luo, Shimeng Yu. tvlsi, 28(9):1945-1952, 2020. [doi]

A Variation Robust Inference Engine Based on STT-MRAM with Parallel Read-OutYandong Luo, Xiaochen Peng, Ryan Hatcher, Titash Rakshit, Jorge Kittl, Mark S. Rodder, Jae-sun Seo, Shimeng Yu. iscas 2020: 1-5 [doi]

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on Processing-in-Memory ArchitecturesXiaochen Peng, Rui Liu 0005, Shimeng Yu. tcas, 67-I(4):1333-1343, 2020. [doi]

Architectural Design of 3D NAND Flash based Compute-in-Memory for Inference EngineWonbo Shim, Hongwu Jiang, Xiaochen Peng, Shimeng Yu. memsys 2020: 77-85 [doi]

Compute-in-Memory with Emerging Nonvolatile-Memories: Challenges and ProspectsShimeng Yu, Xiaoyu Sun, Xiaochen Peng, Shanshi Huang. cicc 2020: 1-4 [doi]

2019

CIMAT: a transpose SRAM-based compute-in-memory architecture for deep neural network on-chip trainingHongwu Jiang, Xiaochen Peng, Shanshi Huang, Shimeng Yu. memsys 2019: 490-496 [doi]

MLP+NeuroSimV3.0: Improving On-chip Learning Performance with Device to Algorithm OptimizationsYandong Luo, Xiaochen Peng, Shimeng Yu. icons2 2019: [doi]

2: An ReRAM-Based Neural Network Accelerator That Maximizes Data Reuse and Area UtilizationManqing Mao, Xiaochen Peng, Rui Liu 0005, Jingtao Li, Shimeng Yu, Chaitali Chakrabarti. esticas, 9(2):398-410, 2019. [doi]

Optimizing Weight Mapping and Data Flow for Convolutional Neural Networks on RRAM Based Processing-In-Memory ArchitectureXiaochen Peng, Rui Liu 0005, Shimeng Yu. iscas 2019: 1-5 [doi]

Inference engine benchmarking across technological platforms from CMOS to RRAMXiaochen Peng, Minkyu Kim, Xiaoyu Sun, Shihui Yin, Titash Rakshit, Ryan M. Hatcher, Jorge A. Kittl, Jae-sun Seo, Shimeng Yu. memsys 2019: 471-479 [doi]

Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm AnalysisWenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao 0006, Hu He, Youhui Zhang, Shimeng Yu, He Qian. dac 2019: 140 [doi]

2018

X-Point PUF: Exploiting Sneak Paths for a Strong Physical Unclonable Function DesignRui Liu 0005, Pai-Yu Chen, Xiaochen Peng, Shimeng Yu. tcas, 65-I(10):3459-3468, 2018. [doi]

NeuroSim: A Circuit-Level Macro Model for Benchmarking Neuro-Inspired Architectures in Online LearningPai-Yu Chen, Xiaochen Peng, Shimeng Yu. tcad, 37(12):3067-3080, 2018. [doi]

Parallelizing SRAM arrays with customized bit-cell for binary neural networksRui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu. dac 2018: [doi]

A Versatile ReRAM-based Accelerator for Convolutional Neural NetworksManqing Mao, Xiaoyu Sun, Xiaochen Peng, Shimeng Yu, Chaitali Chakrabarti. sips 2018: 211-216 [doi]

Benchmark of RRAM based Architectures for Dot-Product ComputationXiaochen Peng, Shimeng Yu. apccas 2018: 378-381 [doi]

XNOR-RRAM: A scalable and parallel resistive synaptic architecture for binary neural networksXiaoyu Sun, Shihui Yin, Xiaochen Peng, Rui Liu, Jae-sun Seo, Shimeng Yu. date 2018: 1423-1428 [doi]

Fully parallel RRAM synaptic array for implementing binary neural network with (+1, -1) weights and (+1, 0) neuronsXiaoyu Sun, Xiaochen Peng, Pai-Yu Chen, Rui Liu, Jae-sun Seo, Shimeng Yu. aspdac 2018: 574-579 [doi]

Design Considerations of Selector Device in Cross-Point RRAM Array for Neuromorphic ComputingJiyong Woo, Xiaochen Peng, Shimeng Yu. iscas 2018: 1-4 [doi]

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