Abstract is missing.
- CEPA: CNN-based Early Performance Assertion Scheme for Analog and Mixed-Signal Circuit SimulationQiaochu Zhang, Shiyu Su, Juzheng Liu, Mike Shuo-Wei Chen. 1-9 [doi]
- Re-examining VLSI Manufacturing and Yield through the Lens of Deep Learning : (Invited Talk)Mohamed Baker Alawieh, Wei Ye, David Z. Pan. 1-8 [doi]
- Noise Resilient Compilation Policies for Quantum Approximate Optimization AlgorithmMahabubul Alam, Abdullah Ash-Saki, Junde Li, Anupam Chattopadhyay, Swaroop Ghosh. 1-7 [doi]
- DeepBurning-GL: an Automated Framework for Generating Graph Neural Network AcceleratorsShengwen Liang, Cheng Liu, Ying Wang, Huawei Li, Xiaowei Li 0001. 1-9 [doi]
- Concurrent Weight Encoding-based Detection for Bit-Flip Attack on Neural Network AcceleratorsQi Liu, Wujie Wen, Yanzhi Wang. 1-8 [doi]
- Contributions to OpenROAD from Abroad: Experiences and Learnings : Invited PaperMateus Fogaça, Eder Monteiro, Marcelo Danigno, Isadora Oliveira, Paulo F. Butzen, Ricardo Reis 0001. 1-8 [doi]
- A Simulator and Compiler Framework for Agile Hardware-Software Co-design Evaluation and ExplorationTyler Sorensen 0001, Aninda Manocha, Esin Tureci, Marcelo Orenes-Vera, Juan L. Aragón, Margaret Martonosi. 1-9 [doi]
- A Non-Gaussian Adaptive Importance Sampling Method for High-Dimensional and Multi-Failure-Region Yield AnalysisXiao Shi, Hao Yan, Chuwen Li, Jianli Chen, Longxing Shi, Lei He 0001. 1-8 [doi]
- Cell Library Characterization using Machine Learning for Design Technology Co-OptimizationFlorian Klemme, Yogesh Singh Chauhan, Jörg Henkel, Hussam Amrouch. 1-9 [doi]
- Hotspot Detection via Attention-based Deep Layout Metric LearningHao Geng, Haoyu Yang, Lu Zhang, Jin Miao, Fan Yang, Xuan Zeng 0001, Bei Yu 0001. 1-8 [doi]
- /TPlace: Machine Learning-Based Delay-Aware Transistor Placement for Standard Cell SynthesisTai-Cheng Lee, Cheng-Yen Yang, Yih-Lang Li. 1-8 [doi]
- Countering Variations and Thermal Effects for Accurate Optical Neural NetworksYing Zhu, Grace Li Zhang, Bing Li 0005, Xunzhao Yin, Cheng Zhuo, Huaxi Gu, Tsung-Yi Ho, Ulf Schlichtmann. 1-7 [doi]
- Early-stage Automated Accelerator Identification Tool for Embedded Systems with Limited AreaParnian Mokri, Mark Hempstead. 1-8 [doi]
- MCell: Multi-Row Cell Layout Synthesis with Resource Constrained MAX-SAT Based Detailed RoutingYih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hidetoshi Onodera. 1-8 [doi]
- The Missing Pieces of Open Design Enablement: A Recent History of Google Efforts : lnvited PaperTim Ansell, Mehdi Saligane. 1-8 [doi]
- Power Side Channel Attack Analysis and DetectionNavyata Gattu, Mohammad Nasim Imtiaz Khan, Asmit De, Swaroop Ghosh. 1-7 [doi]
- Meshed Stack Via Design Considering Complicated Design Rules with Automatic Constraint Generation**This work was partially supported by Synopsys, TSMC, and MOST of Taiwan under Grant No's MOST 109-2636-E-011-002Kai-Chuan Yang, Tao-Chun Yu, Shao-Yun Fang, Teng-Yuan Cheng, Yang-Chun Liu, Cindy Chin-Fang Shen. 1-8 [doi]
- Towards Assurance Evaluation of Autonomous SystemsSteven Beland, Isaac Chang, Alexander Chen, Matthew Moser, James Paunicka, Douglas Stuart, John Vian, Christina Westover, Huafeng Yu. 1-6 [doi]
- Hessian-Driven Unequal Protection of DNN Parameters for Robust InferenceSaurabh Dash, Saibal Mukhopadhyay. 1-9 [doi]
- BoMaNet: Boolean Masking of an Entire Neural NetworkAnuj Dubey, Rosario Cammarota, Aydin Aysu. 1-9 [doi]
- A general approach for identifying hierarchical symmetry constraints for analog circuit layoutKishor Kunal, Jitesh Poojary, Tonmoy Dhar, Meghna Madhusudan, Ramesh Harjani, Sachin S. Sapatnekar. 1-8 [doi]
- Symbolic Uniform Sampling with XOR CircuitsYen-Ting Lin, Jie-Hong R. Jiang, Victor N. Kravets. 1-9 [doi]
- THRIFTY: Training with Hyperdimensional Computing across Flash HierarchySaransh Gupta, Justin Morris, Mohsen Imani, Ranganathan Ramkumar, Jeffrey Yu, Aniket Tiwari, Baris Aksanli, Tajana Simunic Rosing. 1-9 [doi]
- Optimally Approximated and Unbiased Floating-Point Multiplier with Runtime ConfigurabilityChuangtao Chen, Sen Yang, Weikang Qian, Mohsen Imani, Xunzhao Yin, Cheng Zhuo. 1-9 [doi]
- Test Generation using Reinforcement Learning for Delay-based Side-Channel AnalysisZhixin Pan, Jennifer Sheldon, Prabhat Mishra. 1-7 [doi]
- DATC RDF-2020: Strengthening the Foundation for Academic Research in IC Physical DesignJianli Chen, Iris Hui-Ru Jiang, Jinwook Jung, Andrew B. Kahng, Victor N. Kravets, Yih-Lang Li, Shih-Ting Lin, Mingyu Woo. 1-6 [doi]
- Modeling Emerging Technologies using Machine Learning: Challenges and OpportunitiesFlorian Klemme, Jannik Prinz, Victor M. van Santen, Jörg Henkel, Hussam Amrouch. 1-9 [doi]
- DNNExplorer: A Framework for Modeling and Exploring a Novel Paradigm of FPGA-based DNN AcceleratorXiaofan Zhang, Hanchen Ye, Junsong Wang, Yonghua Lin, Jinjun Xiong, Wen-mei Hwu, Deming Chen. 1-9 [doi]
- MobiLattice: A Depth-wise DCNN Accelerator with Hybrid Digital/Analog Nonvolatile Processing-In-Memory BlockQilin Zheng, Xingchen Li, Zongwei Wang, Guangyu Sun, YiMao Cai, Ru Huang, Yiran Chen, Hai Li. 1-9 [doi]
- The ALIGN Open-Source Analog Layout Generator: v1.0 and Beyond (Invited talk)Tonmoy Dhar, Kishor Kunal, Yaguang Li, Yishuang Lin, Meghna Madhusudan, Jitesh Poojary, Arvind K. Sharma, Steven M. Burns, Ramesh Harjani, Jiang Hu, Parijat Mukherjee, Soner Yaldiz, Sachin S. Sapatnekar. 1-2 [doi]
- DAMO: Deep Agile Mask Optimization for Full Chip ScaleGuojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, Bei Yu 0001. 1-9 [doi]
- Electromigration Immortality Check considering Joule Heating Effect for Multisegment Wires**This work is supported in part by NSF grants under No. CCF-1816361, in part by NSF grant under No. CCF-2007135 and No. OISE-1854276Mohammadamir Kavousi, Liang Chen, Sheldon X.-D. Tan. 1-8 [doi]
- SynergicLearning: Neural Network-Based Feature Extraction for Highly-Accurate Hyperdimensional LearningMahdi Nazemi, Amirhossein Esmaili, Arash Fayyazi, Massoud Pedram. 1-9 [doi]
- GridNet: Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid NetworksHan Zhou, Wentian Jin, Sheldon X.-D. Tan. 1-9 [doi]
- An Algorithm for Rule-based Layout Pattern Matching**This work was partially supported by AnaGlobe Technology, IncSheng Hao Wang, Yen-Jong Chen, Ting-Chi Wang, Oscar Chen. 1-8 [doi]
- Fundamental Limits on the Precision of In-memory ArchitecturesSujan K. Gonugondla, Charbel Sakr, Hassan Dbouk, Naresh R. Shanbhag. 1-9 [doi]
- Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-Francesco Regazzoni 0001, Shivam Bhasin, Amir Alipour, Ihab Alshaer, Furkan Aydin, Aydin Aysu, Vincent Beroulle, Giorgio Di Natale, Paul Franzon, David Hély, Naofumi Homma, Akira Ito, Dirmanto Jap, Priyank Kashyap, Ilia Polian, Seetal Potluri, Rei Ueno, Elena Ioana Vatajelu, Ville Yli-Mäyry. 1-6 [doi]
- Bayesian Accuracy Analysis of Stochastic CircuitsTimothy J. Baker, John P. Hayes. 1-9 [doi]
- HAPI: Hardware-Aware Progressive InferenceStefanos Laskaridis, Stylianos I. Venieris, Hyeji Kim, Nicholas D. Lane. 1-9 [doi]
- Modeling and Simulation of NAND Flash Memory Sensing Systems with Cell-to-Cell Vth VariationsNayoung Choi, Jaeha Kim. 1-8 [doi]
- Unlocking Wordline-level Parallelism for Fast Inference on RRAM-based DNN AcceleratorYeonhong Park, Seung Yul Lee, Hoon Shin, Jun Heo 0001, Tae Jun Ham, Jae W. Lee. 1-9 [doi]
- Performance Analysis of Priority-Aware NoCs with Deflection Routing under Traffic CongestionSumit K. Mandal, Anish Krishnakumar, Raid Ayoub, Michael Kishinevsky, Ümit Y. Ogras. 1-9 [doi]
- fuseGNN: Accelerating Graph Convolutional Neural Network Training on GPGPUZhaodong Chen, Mingyu Yan, Maohua Zhu, Lei Deng 0003, Guoqi Li, Shuangchen Li, Yuan Xie 0001. 1-9 [doi]
- ICCAD-2020 CAD Contest in X-value Equivalence Checking and Benchmark Suite : Invited TalkChih-Jen Hsu, Chi-An Wu, Ching-Yi Huang, Kei-Yong Khoo. 1-4 [doi]
- JKQ: JKU Tools for Quantum ComputingRobert Wille, Stefan Hillmich, Lukas Burgholzer. 1-5 [doi]
- COALA: Concurrently Assigning Wire Segments to Layers for 2D Global RoutingYun-Jhe Jiang, Shao-Yun Fang. 1-8 [doi]
- A Thermal-aware Optimization Framework for ReRAM-based Deep Neural Network AccelerationHyein Shin, Myeonggu Kang, Lee-Sup Kim. 1-9 [doi]
- HyperFuzzing for SoC Security ValidationSujit Kumar Muduli, Gourav Takhar, Pramod Subramanyan. 1-9 [doi]
- Full-Chip Thermal Map Estimation for Commercial Multi-Core CPUs with Generative Adversarial Learning**This work is supported in part by NSF grants under No. CCF-1816361, in part by NSF grant under No. CCF-2007135 and No. OISE-1854276Wentian Jin, Sheriff Sadiqbatcha, Jinwei Zhang, Sheldon X.-D. Tan. 1-9 [doi]
- CCCS: Customized SPICE-level Crossbar-array Circuit Simulator for In-Memory ComputingFan Zhang, Miao Hu. 1-8 [doi]
- Building OpenLANE: A 130nm OpenROAD-based Tapeout- Proven Flow : Invited PaperMohamed Shalan, Tim Edwards. 1-6 [doi]
- SWIPE: Enhancing Robustness of ReRAM Crossbars for In-memory ComputingSujan K. Gonugondla, Ameya D. Patil, Naresh R. Shanbhag. 1-9 [doi]
- A Fast Learning-Driven Signoff Power Optimization FrameworkYi-Chen Lu, Siddhartha Nath, Sai Surya Kiran Pentapati, Sung Kyu Lim. 1-9 [doi]
- MLCache: A Space-Efficient Cache Scheme based on Reuse Distance and Machine Learning for NVMe SSDsWeiguang Liu, Jinhua Cui, Junwei Liu, Laurence T. Yang. 1-9 [doi]
- Neural-ILT: Migrating ILT to Neural Networks for Mask Printability and Complexity Co-optimizationBentian Jiang, Lixin Liu, Yuzhe Ma, Hang Zhang 0010, Bei Yu 0001, Evangeline F. Y. Young. 1-9 [doi]
- Hybrid-Shield: Accurate and Efficient Cross-Layer Countermeasure for Run-Time Detection and Mitigation of Cache-Based Side-Channel AttacksHan Wang, Hossein Sayadi, Avesta Sasan, Setareh Rafatirad, Houman Homayoun. 1-9 [doi]
- NNgSAT: Neural Network guided SAT Attack on Logic Locked Complex StructuresKimia Zamiri Azar, Hadi Mardani Kamali, Houman Homayoun, Avesta Sasan. 1-9 [doi]
- Layout Pattern Generation and Legalization with Generative Learning ModelsXiaopeng Zhang, James Shiely, Evangeline F. Y. Young. 1-9 [doi]
- DREAMPlace 3.0: Multi-Electrostatics Based Robust VLSI Placement with Region ConstraintsJiaqi Gu, Zixuan Jiang, Yibo Lin, David Z. Pan. 1-9 [doi]
- Opportunities for RTL and Gate Level Simulation using GPUs (Invited Talk)Yanqing Zhang, Haoxing Ren, Brucek Khailany. 1-5 [doi]
- Information Leakage from FPGA Routing and Logic ElementsIlias Giechaskiel, Jakub Szefer. 1-9 [doi]
- Guiding Template Design for Lamellar DSA with Multiple Patterning and Self-Aligned Via Process**This work was partially supported by Synopsys, TSMC, and MOST of Taiwan under Grant No's MOST 109-2636-E-011-002An-Jie Shih, Shao-Yun Fang, Yi-Yu Liu. 1-6 [doi]
- IoT-CAD: Context-Aware Adaptive Anomaly Detection in IoT Systems Through Sensor AssociationRozhin Yasaei, Felix Hernandez, Mohammad Abdullah Al Faruque. 1-9 [doi]
- Challenges for Building a Cloud Native Scalable and Trustable Multi-tenant AIoT PlatformJinjun Xiong, Huamin Chen. 1-8 [doi]
- Dynamic IR-Drop ECO Optimization by Cell Movement with Current Waveform Staggering and Machine Learning GuidanceXuan-Xue Huang, Hsien-Chia Chen, Sheng-Wei Wang, Iris Hui-Ru Jiang, Yih-Chih Chou, Cheng-Hong Tsai. 1-9 [doi]
- Exploring Target Function Approximation for Stochastic Circuit MinimizationChen Wang, Weihua Xiao, John P. Hayes, Weikang Qian. 1-9 [doi]
- EDA for Autonomous Behavior AssuranceSelma Saidi, Dirk Ziegenbein, Jyotirmoy V. Deshmukh, Rolf Ernst. 1-3 [doi]
- DRAMA: An Approximate DRAM Architecture for High-performance and Energy-efficient Deep Training SystemDuy Thanh Nguyen, Changhong Min, Nhut-Minh Ho, Ik Joon Chang. 1-8 [doi]
- On Uniformly Sampling Traces of a Transition SystemSupratik Chakraborty, Aditya A. Shrotri, Moshe Y. Vardi. 1-9 [doi]
- ICCAD-2020 CAD contest in Routing with Cell Movement : Invited TalkKai-Shun Hu, Ming-Jen Yang, Tao-Chun Yu, Guan-Chuen Chen. 1-4 [doi]
- Automated Synthesis of Custom Networks-on-Chip for Real World ApplicationsAnup Gangwar, Nitin Kumar Agarwal, Ravishankar Sreedharan, Ambica Prasad, Sri Harsha Gade, Zheng Xu. 1-9 [doi]
- Optimal Layout Synthesis for Quantum ComputingBochen Tan, Jason Cong. 1-9 [doi]
- Effective Analog/Mixed-Signal Circuit Placement Considering System Signal FlowKeren Zhu 0001, Hao Chen, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan. 1-9 [doi]
- Just Say Zero: Containing Critical Bit-Error Propagation in Deep Neural Networks With Anomalous Feature SuppressionElbruz Ozen, Alex Orailoglu. 1-9 [doi]
- Pin-3D: A Physical Synthesis and Post-Layout Optimization Flow for Heterogeneous Monolithic 3D ICsSai Surya Kiran Pentapati, Kyungwook Chang, Vassilios Gerousis, Rwik Sengupta, Sung Kyu Lim. 1-9 [doi]
- Faultless to a Fault? The Case of Threshold Implementations of Crypto-systems vs Fault Template AttacksDebdeep Mukhopadhyay. 1-9 [doi]
- RIMI: Instruction-level Memory Isolation for Embedded Systems on RISC-VHaeyoung Kim, Jinjae Lee, Derry Pratama, Asep Muhamad Awaludin, Howon Kim, Donghyun Kwon. 1-9 [doi]
- Efficient Hardware/Software Co-Design for Post-Quantum Crypto Algorithm SIKE on ARM and RISC-V based MicrocontrollersDebapriya Basu Roy, Tim Fritzmann, Georg Sigl. 1-9 [doi]
- Mining Biochemical Circuits from Enzyme Databases via Boolean ReasoningYu-Chou Lin, Jie-Hong R. Jiang. 1-9 [doi]
- Automatic-SSD: Full Hardware Automation over New Memory for High Performance and Energy Efficient PCIe Storage CardsGyuyoung Park, Myoungsoo Jung. 1-9 [doi]
- Problem C: GPU Accelerated Logic Re-simulation : (Invited Talk)Yanqing Zhang, Haoxing Ren, Ben Keller, Brucek Khailany. 1-4 [doi]
- GPU Acceleration in VLSI Back-end Design: Overview and Case StudiesYibo Lin. 1-4 [doi]
- CU.POKer: Placing DNNs on Wafer-Scale Al Accelerator with Optimal Kernel SizingBentian Jiang, Jingsong Chen, Jinwei Liu, Lixin Liu, Fangzhou Wang, Xiaopeng Zhang, Evangeline F. Y. Young. 1-9 [doi]
- GAMMA: Automating the HW Mapping of DNN Models on Accelerators via Genetic AlgorithmSheng-Chun Kao, Tushar Krishna. 1-9 [doi]
- ECC Cache: A Lightweight Error Detection for Phase-Change Memory Stuck-At FaultsChao Zhang 0039, Khaled Abdelaal, Angel Chen, Xinhui Zhao, Wujie Wen, Xiaochen Guo. 1-9 [doi]
- A CAD-based methodology to optimize HLS code via the Roofline modelMarco Siracusa, Marco Rabozzi, Emanuele Del Sozzo, Lorenzo Di Tucci, Samuel Williams, Marco D. Santambrogio. 1-9 [doi]
- A General-purpose Parallel and Heterogeneous Task Programming System for VLSI CADTsung-Wei Huang. 1-2 [doi]
- Adaptable and Divergent Synthetic Benchmark Generation for Hardware SecuritySarah Amir, Domenic Forte. 1-9 [doi]
- SETGAN: Scale and Energy Trade-off GANs for Image Applications on Mobile PlatformsNitthilan Kanappan Jayakodi, Janardhan Rao Doppa, Partha Pratim Pande. 1-9 [doi]
- Toward Silicon-Proven Detailed Routing for Analog and Mixed-Signal CircuitsHao Chen, Keren Zhu 0001, Mingjie Liu, Xiyuan Tang, Nan Sun, David Z. Pan. 1-8 [doi]
- DaDu Series - Fast and Efficient Robot AcceleratorsYinhe Han, Yuxin Yang, Xiaoming Chen, Shiqi Lian. 1-8 [doi]
- New Passive and Active Attacks on Deep Neural Networks in Medical ApplicationsCheng Gongye, Hongjia Li, Xiang Zhang, Majid Sabbagh, Geng Yuan, Xue Lin, Thomas Wahl, Yunsi Fei. 1-9 [doi]
- Considering Decoherence Errors in the Simulation of Quantum Circuits Using Decision DiagramsThomas Grurl, Jürgen Fuß, Robert Wille. 1-7 [doi]
- On EDA Solutions for Reconfigurable Memory-Centric AI Edge ApplicationsHung-Ming Chen, Chia-Lin Hu, Kang-Yu Chang, Alexandra Küster, Yu-Hsien Lin, Po-Shen Kuo, Wei-Tung Chao, Bo-Cheng Lai, Chien-Nan Liu, Shyh-Jye Jou. 1-8 [doi]
- Seed-and-Vote based In-Memory Accelerator for DNA Read MappingAnn Franchesca Laguna, Hasindu Gamaarachchi, Xunzhao Yin, Michael T. Niemier, Sri Parameswaran, Xiaobo Sharon Hu. 1-9 [doi]
- Power Distribution Network Generation for Optimizing IR-Drop Aware TimingWen-Hsiang Chang, Li-Yi Lin, Yu-Guang Chen, Mango C.-T. Chao. 1-9 [doi]
- SODA: a New Synthesis Infrastructure for Agile Hardware Design of Machine Learning AcceleratorsMarco Minutoli, Vito Giovanni Castellana, Cheng Tan, Joseph B. Manzano, Vinay Amatya, Antonino Tumeo, David Brooks 0001, Gu-Yeon Wei. 1-7 [doi]
- CONTRA: Area-Constrained Technology Mapping Framework For Memristive Memory Processing UnitDebjyoti Bhattacharjee, Anupam Chattopadhyay, Srijit Dutta, Ronny Ronen, Shahar Kvatinsky. 1-9 [doi]
- Transfer Learning with Bayesian Optimization-Aided Sampling for Efficient AMS Circuit ModelingJuzheng Liu, Mohsen Hassanpourghadi, Qiaochu Zhang, Shiyu Su, Mike Shuo-Wei Chen. 1-9 [doi]
- NEST: DIMM based Near-Data-Processing Accelerator for K-mer CountingWenqin Huangfu, Krishna T. Malladi, Shuangchen Li, Peng Gu, Yuan Xie 0001. 1-9 [doi]
- The Safe and Effective Application of Probabilistic Techniques in Safety-Critical SystemsKunal Agrawal, Sanjoy Baruah, Zhishan Guo, Jing Li 0025. 1-9 [doi]
- GPU-Accelerated Static Timing AnalysisZizheng Guo, Tsung-Wei Huang, Yibo Lin. 1-9 [doi]
- Know the Unknowns: Addressing Disturbances and Uncertainties in Autonomous Systems : Invited PaperQi Zhu 0002, Wenchao Li, Hyoseung Kim, Yecheng Xiang, Kacper Wardega, Zhilu Wang, Yixuan Wang, Hengyi Liang, Chao Huang, Jiameng Fan, Hyunjong Choi. 1-9 [doi]
- Fast IR Drop Estimation with Machine Learning : Invited PaperZhiyao Xie, Hai Li, Xiaoqing Xu, Jiang Hu, Yiran Chen. 1-8 [doi]
- Energy-Efficient Control Adaptation with Safety Guarantees for Learning-Enabled Cyber-Physical SystemsYixuan Wang, Chao Huang, Qi Zhu. 1-9 [doi]
- Routability-Aware Pin Access Optimization for Monolithic 3D DesignsRun-Yi Wang, Yao-Wen Chang. 1-6 [doi]
- Towards Cardiac Intervention Assistance: Hardware-aware Neural Architecture Exploration for Real-Time 3D Cardiac Cine MRI SegmentationDewen Zeng, Weiwen Jiang, Tianchen Wang, Xiaowei Xu 0004, Haiyun Yuan, Meiping Huang, Jian Zhuang, Jingtong Hu, Yiyu Shi. 1-8 [doi]
- VLSI Placement Parameter Optimization using Deep Reinforcement LearningAnthony Agnesina, Kyungwook Chang, Sung Kyu Lim. 1-9 [doi]
- ASAP: An Analytical Strategy for AQFP PlacementYi-Chen Chang, Hongjia Li, Olivia Chen, Yanzhi Wang, Nobuyuki Yoshikawa, Tsung-Yi Ho. 1-7 [doi]
- A Many-Core Accelerator Design for On-Chip Deep Reinforcement LearningYing Wang, Mengdi Wang, Bing Li, Huawei Li, Xiaowei Li 0001. 1-7 [doi]
- HitM: High-Throughput ReRAM-based PIM for Multi-Modal Neural NetworksBing Li, Ying Wang, Yiran Chen. 1-7 [doi]
- ABACUS: Address-partitioned Bloom filter on Address Checking for UniquenesS in IoT BlockchainTianyu Wang, Wenbin Zhu, Qun Ma, Zhaoyan Shen, Zili Shao. 1-7 [doi]
- Structural Synthesis of Operational Amplifiers Based on Functional Block ModelingInga Abel, Helmut Graeb. 1-6 [doi]
- AxHLS: Design Space Exploration and High-Level Synthesis of Approximate Accelerators using Approximate Functional Units and Analytical ModelsJorge Castro-Godínez, Julián Mateus-Vargas, Muhammad Shafique 0001, Jörg Henkel. 1-9 [doi]
- DP-MAP: Towards Resistive Dot-Product Engines with Improved PrecisionNecati Uysal, Baogang Zhang, Sumit Kumar Jha 0001, Rickard Ewetz. 1-9 [doi]
- Dual-Output LUT Merging during FPGA Technology MappingFeng Wang, Liren Zhu, Jiaxi Zhang, Lei Li, Yang Zhang, Guojie Luo. 1-9 [doi]
- Bridging Academic Open-Source EDA to Real-World UsabilityAustin Rovinski, Tutu Ajayi, Minsoo Kim, Guanru Wang, Mehdi Saligane. 1-7 [doi]
- RTL-to-GDS Design Tools for Monolithic 3D ICsJinwoo Kim, Gauthaman Murali, Pruek Vanna-Iampikul, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Krishnendu Chakrabarty, Saibal Mukhopadhyay, Sung Kyu Lim. 1-8 [doi]
- HyperTune: Dynamic Hyperparameter Tuning for Efficient Distribution of DNN Training Over Heterogeneous SystemsAli Heydari Gorji, Siavash Rezaei, Mahdi Torabzadehkashi, Hossein Bobarshad, Vladimir Castro Alves, Pai H. Chou. 1-8 [doi]
- Modeling Techniques for Logic LockingJoseph Sweeney, Marijn J. H. Heule, Lawrence T. Pileggi. 1-9 [doi]
- A Crowd-Based Explosive Detection System with Two-Level Feedback Sensor CalibrationChengmo Yang, Patrick Cronin, Agamyrat Agambayev, Sule Ozev, A. Enis Çetin, Alex Orailoglu. 1-9 [doi]
- A Quantitative Defense Framework against Power Attacks on Multi-tenant FPGAYukui Luo, Xiaolin Xu. 1-4 [doi]
- Hardware Acceleration of Robot Scene Perception AlgorithmsYanqi Liu, Can Eren Derman, Giuseppe Calderoni, R. Iris Bahar. 1-8 [doi]
- Encoding, Model, and Architecture: Systematic Optimization for Spiking Neural Network in FPGAsHaowen Fang, Zaidao Mei, Amar Shrestha, Ziyi Zhao, Yilan Li, Qinru Qiu. 1-9 [doi]
- Electromigration Checking Using a Stochastic Effective Current ModelAdam Issa, Valeriy Sukharev, Farid N. Najm. 1-8 [doi]
- Aadam: A Fast, Accurate, and Versatile Aging-Aware Cell Library Delay Model using Feed-Forward Neural NetworkSeyed Milad Ebrahimipour, Behnam Ghavami, Hamid Mousavi, Mohsen Raji, Zhenman Fang, Lesley Shannon. 1-9 [doi]
- Counteracting Adversarial Attacks in Autonomous DrivingQi Sun, Arjun Ashok Rao, Xufeng Yao, Bei Yu 0001, Shiyan Hu. 1-7 [doi]
- Energy-efficient XNOR-free In-Memory BNN Accelerator with Input Distribution RegularizationHyungJun Kim, Hyunmyung Oh, Jae-Joon Kim. 1-9 [doi]
- FPGA-based Low-Batch Training Accelerator for Modern CNNs Featuring High Bandwidth MemoryShreyas K. Venkataramanaiah, Han-Sok Suh, Shihui Yin, Eriko Nurvitadhi, Aravind Dasu, Yu Cao 0001, Jae-sun Seo. 1-8 [doi]
- Laser Attack Benchmark SuiteBurin Amornpaisannon, Andreas Diavastos, Li-Shiuan Peh, Trevor E. Carlson. 1-9 [doi]
- PROS: A Plug-in for Routability Optimization applied in the State-of-the-art commercial EDA tool using deep learningJingsong Chen, Jian Kuang 0001, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young. 1-8 [doi]
- Dynamic Minimization of Bi-Kronecker Functional Decision DiagramsXuanxiang Huang, Haipeng Che, Liangda Fang, Qingliang Chen, Quanlong Guan, Yuhui Deng, Kaile Su. 1-9 [doi]
- F2VD: Fluid Rates to Virtual Deadlines for Precise Mixed-Criticality Scheduling on a Varying-Speed ProcessorKecheng Yang 0001, Ashikahmed Bhuiyan, Zhishan Guo. 1-9 [doi]
- CleaNN: Accelerated Trojan Shield for Embedded Neural NetworksMojan Javaheripi, Mohammad Samragh, Gregory Fields, Tara Javidi, Farinaz Koushanfar. 1-9 [doi]
- Accurate Operation Delay Prediction for FPGA HLS Using Graph Neural NetworksEcenur Ustun, Chenhui Deng, Debjit Pal, Zhijing Li 0002, Zhiru Zhang. 1-9 [doi]
- SF-GRASS: Solver-Free Graph Spectral SparsificationYing Zhang, Zhiqiang Zhao, Zhuo Feng. 1-8 [doi]
- Agile SoC Development with Open ESP : Invited PaperPaolo Mantovani, Davide Giri, Giuseppe Di Guglielmo, Luca Piccolboni, Joseph Zuckerman, Emilio G. Cota, Michele Petracca, Christian Pilato, Luca P. Carloni. 1-9 [doi]
- Your Agile Open Source HW Stinks (Because It Is Not a System)Michael Bedford Taylor. 1-6 [doi]
- PUF-G: A CAD Framework for Automated Assessment of Provable Learnability from Formal PUF RepresentationsDurba Chatterjee, Debdeep Mukhopadhyay, Aritra Hazra. 1-9 [doi]
- SuSy: A Programming Model for Productive Construction of High-Performance Systolic Arrays on FPGAsYi-Hsiang Lai, Hongbo Rong, Size Zheng 0001, Weihao Zhang, Xiuping Cui, Yunshan Jia, Jie Wang 0002, Brendan Sullivan, Zhiru Zhang, Yun Liang 0001, Youhui Zhang, Jason Cong, Nithin George, Jose Alvarez, Christopher J. Hughes, Pradeep Dubey. 1-9 [doi]
- NeuroMAX: A High Throughput, Multi-Threaded, Log-Based Accelerator for Convolutional Neural NetworksMahmood Azhar Qureshi, Arslan Munir. 1-9 [doi]
- NASCaps: A Framework for Neural Architecture Search to Optimize the Accuracy and Hardware Efficiency of Convolutional Capsule NetworksAlberto Marchisio, Andrea Massa, Vojtech Mrazek, Beatrice Bussolino, Maurizio Martina, Muhammad Shafique 0001. 1-9 [doi]
- Retiming for High-performance Superconductive Circuits with Register Energy MinimizationTing-Ru Lin, Massoud Pedram. 1-9 [doi]
- Detection Through Deep Neural Networks: A Reservoir Computing Approach for MIMO-OFDM Symbol DetectionKangjun Bai, Lingjia Liu 0001, Zhou Zhou, Yang Yi 0002. 1-7 [doi]
- FlowTune: Practical Multi-armed Bandits in Boolean OptimizationCunxi Yu. 1-9 [doi]
- Coupling Extraction and Optimization for Heterogeneous 2.5D Chiplet-Package Co-DesignM. D. Arafat Kabir, Dusan Petranovic, Yarui Peng. 1-8 [doi]
- Intelligent Design Automation for 2.5/3D Heterogeneous SoC IntegrationIris Hui-Ru Jiang, Yao-Wen Chang, Jiun-Lang Huang, Chung-Ping Chen. 1-7 [doi]
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