Table of Contents

• LAMA: Link-Aware Hybrid Management for Memory Accesses in Emerging CPU-FPGA PlatformsLiang Feng, Jieru Zhao, Tingyuan Liang, Sharad Sinha, Wei Zhang. 1 [doi]
• Thread Weaving: Static Resource Scheduling for Multithreaded High-Level SynthesisHsuan Hsiao, Jason Anderson. 2 [doi]
• Exact and Heuristic Allocation of Multi-kernel Applications to Multi-FPGA PlatformsJunnan Shan, Mario R. Casu, Jordi Cortadella, Luciano Lavagno, Mihai T. Lazarescu. 3 [doi]
• A Flat Timing-Driven Placement Flow for Modern FPGAsTimothy Martin, Dani Maarouf, Ziad Abuowaimer, Abeer Alhyari, Gary Gréwal, Shawki Areibi. 4 [doi]
• Accuracy vs. Efficiency: Achieving Both through FPGA-Implementation Aware Neural Architecture SearchWeiwen Jiang, Xinyi Zhang, Edwin Hsing-Mean Sha, Lei Yang 0018, Qingfeng Zhuge, Yiyu Shi, Jingtong Hu. 5 [doi]
• CANN: Curable Approximations for High-Performance Deep Neural Network AcceleratorsMuhammad Abdullah Hanif, Faiq Khalid, Muhammad Shafique 0001. 6 [doi]
• Successive Log Quantization for Cost-Efficient Neural Networks Using Stochastic ComputingSugil Lee, Hyeon Uk Sim, Jooyeon Choi, Jongeun Lee. 7 [doi]
• ARGA: Approximate Reuse for GPGPU AccelerationDaniel Peroni, Mohsen Imani, Hamid Nejatollahi, Nikil D. Dutt, Tajana Rosing. 8 [doi]
• Assessing the Adherence of an Industrial Autonomous Driving Framework to ISO 26262 Software GuidelinesHamid Tabani, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla, Guillem Bernat. 9 [doi]
• Tighter Dimensioning of Heterogeneous Multi-Resource Autonomous CPS with Control Performance GuaranteesDebayan Roy, Wanli Chang, Sanjoy K. Mitter, Samarjit Chakraborty. 10 [doi]
• Dynamic Switching Speed Reconfiguration for Engine Performance OptimizationChao Peng, Yecheng Zhao, Haibo Zeng. 11 [doi]
• A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling RepresentationHe Zhou, Sunil P. Khatri, Jiang Hu, Frank Liu. 12 [doi]
• Process, Circuit and System Co-optimization of Wafer Level Co-Integrated FinFET with Vertical Nanosheet Selector for STT-MRAM ApplicationsTrong Huynh Bao, Anabela Veloso, Sushil Sakhare, Philippe Matagne, Julien Ryckaert, Manu Perumkunnil, Davide Crotti, Farrukh Yasin, Alessio Spessot, Arnaud Furnemont, Gouri Sankar Kar, Anda Mocuta. 13 [doi]
• LL-PCM: Low-Latency Phase Change Memory ArchitectureNam Sung Kim, Choungki Song, Woo Young Cho, Jian Huang, Myoungsoo Jung. 14 [doi]
• What does Vibration do to Your SSD?Janki Bhimani, Tirthak Patel, Ningfang Mi, Devesh Tiwari. 15 [doi]
• Ultra-thin Skin Electronics for High Quality and Continuous Skin-Sensor-Silicon InterfacingLeilai Shao, Sicheng Li, Ting Lei, Tsung-Ching Huang, Raymond G. Beausoleil, Zhenan Bao, Kwang-Ting Cheng. 16 [doi]
• Enabling High-Dimensional Bayesian Optimization for Efficient Failure Detection of Analog and Mixed-Signal CircuitsHanbin Hu, Peng Li, Jianhua Z. Huang. 17 [doi]
• High Performance Graph Convolutional Networks with Applications in Testability AnalysisYuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, Bei Yu 0001. 18 [doi]
• MRLoc: Mitigating Row-hammering based on memory LocalityJung Min You, Joon-Sung Yang. 19 [doi]
• System-level hardware failure prediction using deep learningXiaoyi Sun, Krishnendu Chakrabarty, Ruirui Huang, Yiquan Chen, Bing Zhao, Hai Cao, Yinhe Han, Xiaoyao Liang, Li Jiang. 20 [doi]
• Enabling Practical Processing in and near Memory for Data-Intensive ComputingOnur Mutlu, Saugata Ghose, Juan Gómez-Luna, Rachata Ausavarungnirun. 21 [doi]
• Practical Near-Data Processing to Evolve Memory and Storage Devices into Mainstream Heterogeneous Computing SystemsNam Sung Kim, Pankaj Mehra. 22 [doi]
• HeadStart: Enforcing Optimal Inceptions in Pruning Deep Neural Networks for Efficient Inference on GPGPUsNing Lin, Hang Lu, Xin Wei, Xiaowei Li 0001. 23 [doi]
• GATE: A Generalized Dataflow-level Approximation Tuning Engine For Data Parallel ArchitecturesSeokwon Kang, Yongseung Yu, Jiho Kim, Yongjun Park. 24 [doi]
• LSIM: Ultra Lightweight Similarity Measurement for Mobile Graphics ApplicationsYu-Chuan Chang, Wei-Ming Chen, Pi-Cheng Hsiu, Yen-Yu Lin, Tei-Wei Kuo. 25 [doi]
• Efficient State Retention through Paged Memory Management for Reactive Transient ComputingSivert T. Sliper, Domenico Balsamo, Nikos Nikoleris, William Wang, Alex S. Weddell, Geoff V. Merrett. 26 [doi]
• NAPEL: Near-Memory Computing Application Performance Prediction via Ensemble LearningGagandeep Singh, Juan Gómez-Luna, Giovanni Mariani, Geraldo F. Oliveira, Stefano Corda, Sander Stuijk, Onur Mutlu, Henk Corporaal. 27 [doi]
• DREDGE: Dynamic Repartitioning during Dynamic Graph ExecutionAndrew McCrabb, Eric Winsor, Valeria Bertacco. 28 [doi]
• ROC: DRAM-based Processing with Reduced Operation CyclesXin Xin, Youtao Zhang, Jun Yang. 29 [doi]
• NV-BNN: An Accurate Deep Convolutional Neural Network Based on Binary STT-MRAM for Adaptive AI EdgeChih-Cheng Chang, Ming-Hung Wu, Jia-Wei Lin, Chun-Hsien Li, Vivek Parmar, Heng-Yuan Lee, Jeng-Hua Wei, Shyh-Shyuan Sheu, Manan Suri, Tian-Sheuan Chang, Tuo-Hung Hou. 30 [doi]
• No Compromises: Secure NVM with Crash Consistency, Write-Efficiency and High-PerformanceFan Yang, Youyou Lu, Youmin Chen, Haiyu Mao, Jiwu Shu. 31 [doi]
• In-process Memory Isolation Using Hardware WatchpointJinsoo Jang, Brent ByungHoon Kang. 32 [doi]
• H-ORAM: A Cacheable ORAM Interface for Efficient I/O AccessesLiang Liu, Rujia Wang, Youtao Zhang, Jun Yang. 33 [doi]
• RansomBlocker: a Low-Overhead Ransomware-Proof SSDJisung Park, Youngdon Jung, Jonghoon Won, Minji Kang, Sungjin Lee, Jihong Kim. 34 [doi]
• Transmit or Discard: Optimizing Data Freshness in Networked Embedded Systems with Energy Harvesting SourcesZimeng Zhou, Chenchen Fu, Chun Jason Xue, Song Han. 35 [doi]
• FPGA-Based Emulation of Embedded DRAMs for Statistical Error Resilience Evaluation of Approximate Computing SystemsMarco Widmer, Andrea Bonetti, Andreas Burg. 36 [doi]
• Adapting Layer RBERs Variations of 3D Flash Memories via Multi-granularity Progressive LDPC ReadingYajuan Du, Yao Zhou, Meng Zhang, Wei Liu, Shengwu Xiong. 37 [doi]
• A Hybrid Agent-based Design Methodology for Dynamic Cross-layer Reliability in Heterogeneous Embedded SystemsSiva Satyendra Sahoo, Bharadwaj Veeravalli, Akash Kumar 0001. 38 [doi]
• PRIMAL: Power Inference using Machine LearningYuan Zhou, Haoxing Ren, Yanqing Zhang, Ben Keller, Brucek Khailany, Zhiru Zhang. 39 [doi]
• Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate CircuitsIlaria Scarabottolo, Giovanni Ansaloni, George A. Constantinides, Laura Pozzi. 40 [doi]
• Performance, Power and Cooling Trade-Offs with NCFET-based Many-CoresMartin Rapp, Sami Salamin, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel. 41 [doi]
• STFL: Energy-Efficient Data Movement with Slow Transition Fast Level SignalingPayman Behnam, Mahdi Nazm Bojnordi. 42 [doi]
• Formal Verification of Security Critical Hardware-Firmware Interactions in Commercial SoCsSayak Ray, Nishant Ghosh, Ramya Jayaram Masti, Arun K. Kanuparthi, Jason M. Fung. 43 [doi]
• In Hardware We Trust: Gains and Pains of Hardware-assisted SecurityLejla Batina, Patrick Jauernig, Nele Mentens, Ahmad-Reza Sadeghi, Emmanuel Stapf. 44 [doi]
• Protecting RISC-V against Side-Channel AttacksElke De Mulder, Samatha Gummalla, Michael Hutter. 45 [doi]
• ANN Based Admission Control for On-Chip NetworksBoqian Wang, Zhonghai Lu, Shenggang Chen. 46 [doi]
• An Energy-Efficient Network-on-Chip Design using Reinforcement LearningHao Zheng 0005, Ahmed Louri. 47 [doi]
• Lightweight Mitigation of Hardware Trojan Attacks in NoC-based Manycore ComputingVenkata Yaswanth Raparti, Sudeep Pasricha. 48 [doi]
• Sparse 3-D NoCs with Inductive CouplingMichihiro Koibuchi, Lambert Leong, Tomohiro Totoki, Naoya Niwa, Hiroki Matsutani, Hideharu Amano, Henri Casanova. 49 [doi]
• Surf-Bless: A Confined-interference Routing for Energy-Efficient Communication in NoCsPeng Wang, Sobhan Niknam, Sheng Ma, Zhiying Wang, Todor P. Stefanov. 50 [doi]
• Effect of Distributed Directories in Mesh InterconnectsMarcos Horro, Mahmut T. Kandemir, Louis-Noël Pouchet, Gabriel Rodríguez 0001, Juan Touriño. 51 [doi]
• BRIC: Locality-based Encoding for Energy-Efficient Brain-Inspired Hyperdimensional ComputingMohsen Imani, Justin Morris, John Messerly, Helen Shu, Yaobang Deng, Tajana Rosing. 52 [doi]
• Fast and Efficient Information Transmission with Burst Spikes in Deep Spiking Neural NetworksSeongsik Park, Sei Joon Kim, Hyeokjun Choe, Sungroh Yoon. 53 [doi]
• Deep-DFR: A Memristive Deep Delayed Feedback Reservoir Computing System with Hybrid Neural Network TopologyKangjun Bai, Qiyuan An, Yang Yi 0002. 54 [doi]
• A Fault-Tolerant Neural Network ArchitectureTao Liu, Wujie Wen, Lei Jiang 0001, Yanzhi Wang, Chengmo Yang, Gang Quan. 55 [doi]
• A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAMZhenhua Zhu, Hanbo Sun, Yujun Lin, Guohao Dai, Lixue Xia, Song Han, Yu Wang, Huazhong Yang. 56 [doi]
• Noise Injection Adaption: End-to-End ReRAM Crossbar Non-ideal Effect Adaption for Neural Network MappingZhezhi He, Jie Lin, Rickard Ewetz, Jiann-shiun Yuan, Deliang Fan. 57 [doi]
• A Novel Covert Channel Attack Using Memory Encryption Engine CacheYoungkwang Han, John Kim. 58 [doi]
• Designing Secure Cryptographic Accelerators with Information Flow Enforcement: A Case Study on AESZhenghong Jiang, Hanchen Jin, G. Edward Suh, Zhiru Zhang. 59 [doi]
• SafeSpec: Banishing the Spectre of a Meltdown with Leakage-Free SpeculationKhaled N. Khasawneh, Esmaeil Mohammadian Koruyeh, Chengyu Song, Dmitry Evtyushkin, Dmitry Ponomarev, Nael B. Abu-Ghazaleh. 60 [doi]
• SpectreGuard: An Efficient Data-centric Defense Mechanism against Spectre AttacksJacob Fustos, Farzad Farshchi, Heechul Yun. 61 [doi]
• PAPP: Prefetcher-Aware Prime and Probe Side-channel AttackDaimeng Wang, Zhiyun Qian, Nael B. Abu-Ghazaleh, Srikanth V. Krishnamurthy. 62 [doi]
• HardScope: Hardening Embedded Systems Against Data-Oriented AttacksThomas Nyman, Ghada Dessouky, Shaza Zeitouni, Aaro Lehikoinen, Andrew Paverd, N. Asokan, Ahmad-Reza Sadeghi. 63 [doi]
• An Efficient Multi-fidelity Bayesian Optimization Approach for Analog Circuit SynthesisShuhan Zhang, Wenlong Lyu, Fan Yang, Changhao Yan, Dian Zhou, Xuan Zeng 0001, Xiangdong Hu. 64 [doi]
• Rethinking Sparsity in Performance Modeling for Analog and Mixed Circuits using Spike and Slab ModelsMohamed Baker Alawieh, Sinead A. Williamson, David Z. Pan. 65 [doi]
• WellGAN: Generative-Adversarial-Network-Guided Well Generation for Analog/Mixed-Signal Circuit LayoutBiying Xu, Yibo Lin, Xiyuan Tang, Shaolan Li, Linxiao Shen, Nan Sun, David Z. Pan. 66 [doi]
• Digital Compatible Synthesis, Placement and Implementation of Mixed-Signal Time-Domain ComputingZhengyu Chen, Hai Zhou, Jie Gu. 67 [doi]
• A Rigorous Approach for the Sparsification of Dense Matrices in Model Order Reduction of RLC CircuitsCharalampos Antoniadis, Nestor E. Evmorfopoulos, Georgios I. Stamoulis. 68 [doi]
• Enabling Complex Stimuli in Accelerated Mixed-Signal SimulationSara Divanbeigi, Evan Aditya, Zhongpin Wang, Markus Olbrich. 69 [doi]
• Scalable Generic Logic Synthesis: One Approach to Rule Them AllHeinz Riener, Eleonora Testa, Winston Haaswijk, Alan Mishchenko, Luca Amarù, Giovanni De Micheli, Mathias Soeken. 70 [doi]
• Comprehensive Search for ECO Rectification Using Symbolic SamplingVictor N. Kravets, Nian-Ze Lee, Jie-Hong R. Jiang. 71 [doi]
• Embedding Functions Into Reversible Circuits: A Probabilistic Approach to the Number of LinesNiels Gleinig, Frances Ann Hubis, Torsten Hoefler. 72 [doi]
• Disjoint-Support Decomposition and Extraction for Interconnect-Driven Threshold Logic SynthesisHao Chen, Shao-Chun Hung, Jie-Hong R. Jiang. 73 [doi]
• Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security ApplicationsEleonora Testa, Mathias Soeken, Luca Amarù, Giovanni De Micheli. 74 [doi]
• SMatch: Structural Matching for Fast Resynthesis in FPGAsRafael Trapani Possignolo, Jose Renau. 75 [doi]
• Toward an Open-Source Digital Flow: First Learnings from the OpenROAD ProjectTutu Ajayi, Vidya A. Chhabria, Mateus Fogaça, Soheil Hashemi, Abdelrahman Hosny, Andrew B. Kahng, Minsoo Kim, Jeongsup Lee, Uday Mallappa, Marina Neseem, Geraldo Pradipta, Sherief Reda, Mehdi Saligane, Sachin S. Sapatnekar, Carl Sechen, Mohamed Shalan, William Swartz, Lutong Wang, Zhehong Wang, Mingyu Woo, Bangqi Xu. 76 [doi]
• ALIGN: Open-Source Analog Layout Automation from the Ground UpKishor Kunal, Meghna Madhusudan, Arvind K. Sharma, Wenbin Xu, Steven M. Burns, Ramesh Harjani, Jiang Hu, Desmond A. Kirkpatrick, Sachin S. Sapatnekar. 77 [doi]
• Essential Building Blocks for Creating an Open-source EDA ProjectTsung-Wei Huang, Chun-Xun Lin, Guannan Guo, Martin D. F. Wong. 78 [doi]
• Open-Source EDA Tools and IP, A View from the TrenchesElad Alon, Krste Asanovic, Jonathan Bachrach, Borivoje Nikolic. 79 [doi]
• A 1.17 TOPS/W, 150fps Accelerator for Multi-Face Detection and AlignmentHuiyu Mo, Leibo Liu, Wenping Zhu, Qiang Li, Hong Liu, Wenjing Hu, Yao Wang, Shaojun Wei. 80 [doi]
• Analog/Mixed-Signal Hardware Error Modeling for Deep Learning InferenceAngad S. Rekhi, Brian Zimmer, Nikola Nedovic, Ningxi Liu, Rangharajan Venkatesan, Miaorong Wang, Brucek Khailany, William J. Dally, C. Thomas Gray. 81 [doi]
• A 3T/Cell Practical Embedded Nonvolatile Memory Supporting Symmetric Read and Write Access Based on Ferroelectric FETsJuejian Wu, Hongtao Zhong, Kai Ni, Yongpan Liu, Huazhong Yang, Xueqing Li. 82 [doi]
• A Fast, Reliable and Wide-Voltage-Range In-Memory Computing ArchitectureWilliam Andrew Simon, Juan Galicia, Alexandre Levisse, Marina Zapater, David Atienza. 83 [doi]
• BitBlade: Area and Energy-Efficient Precision-Scalable Neural Network Accelerator with Bitwise SummationSungju Ryu, HyungJun Kim, Wooseok Yi, Jae-Joon Kim. 84 [doi]
• Acceleration of DNN Backward Propagation by Selective Computation of GradientsGunhee Lee, Hanmin Park, Namhyung Kim, Joonsang Yu, Sujeong Jo, Kiyoung Choi. 85 [doi]
• C3-Flow: Compute Compression Co-Design Flow for Deep Neural NetworksMatthew Sotoudeh, Sara S. Baghsorkhi. 86 [doi]
• ABM-SpConv: A Novel Approach to FPGA-Based Acceleration of Convolutional Neural Network InferenceDong Wang, Ke Xu, Qun Jia, Soheil Ghiasi. 87 [doi]
• Pushing the speed limit of constant-time discrete Gaussian sampling. A case study on the Falcon signature schemeAngshuman Karmakar, Sujoy Sinha Roy, Frederik Vercauteren, Ingrid Verbauwhede. 88 [doi]
• Full-Lock: Hard Distributions of SAT instances for Obfuscating Circuits using Fully Configurable Logic and Routing BlocksHadi Mardani Kamali, Kimia Zamiri Azar, Houman Homayoun, Avesta Sasan. 89 [doi]
• A Cellular Automata Guided Obfuscation Strategy For Finite-State-Machine SynthesisRajit Karmakar, Suman Sekhar Jana, Santanu Chattopadhyay. 90 [doi]
• An Efficient Spare-Line Replacement Scheme to Enhance NVM SecurityJie Xu, Dan Feng 0001, Yu Hua 0001, Fangting Huang, Wen Zhou, Wei Tong, Jingning Liu. 91 [doi]
• Analyzing Parallel Real-Time Tasks Implemented with Thread PoolsDaniel Casini, Alessandro Biondi, Giorgio C. Buttazzo. 92 [doi]
• Scheduling and Analysis of Parallel Real-Time Tasks with SemaphoresXu Jiang, Nan Guan, Weichen Liu, Maolin Yang. 93 [doi]
• Real-Time Scheduling and Analysis of Synchronous OpenMP Task Systems with Tied TasksJinghao Sun, Nan Guan, Xiaoqing Wang, Chenhan Jin, Yaoyao Chi. 94 [doi]
• DCFNoC: A Delayed Conflict-Free Time Division Multiplexing Network on ChipTomás Picornell, José Flich, Carles Hernández, José Duato. 95 [doi]
• Learning Temporal Specifications from Imperfect Traces Using Bayesian InferenceArtur Mrowca, Martin Nocker, Sebastian Steinhorst, Stephan Günnemann. 96 [doi]
• Accelerating FPGA Prototyping through Predictive Model-Based HLS Design Space ExplorationShuangnan Liu, Francis C. M. Lau 0002, Benjamin Carrión Schäfer. 97 [doi]
• Sample-Guided Automated Synthesis for CCSL SpecificationsMing Hu, Tongquan Wei, Min Zhang, Frédéric Mallet, Mingsong Chen. 98 [doi]
• DHOOM: Reusing Design-for-Debug Hardware for Online MonitoringNeetu Jindal, Sandeep Chandran, Preeti Ranjan Panda, Sanjiva Prasad, Abhay Mitra, Kunal Singhal, Shubham Gupta, Shikhar Tuli. 99 [doi]
• Efficient System Architecture in the Era of Monolithic 3D: Dynamic Inter-tier Interconnect and Processing-in-MemoryDylan Stow, Itir Akgun, Wenqin Huangfu, Yuan Xie 0001, Xueqi Li, Gabriel H. Loh. 100 [doi]
• RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICsHeechun Park, Kyungwook Chang, Bon Woong Ku, Jinwoo Kim, Edward Lee, Daehyun Kim, Arjun Chaudhuri, Sanmitra Banerjee, Saibal Mukhopadhyay, Krishnendu Chakrabarty, Sung Kyu Lim. 101 [doi]
• MobiEye: An Efficient Cloud-based Video Detection System for Real-time Mobile ApplicationsJiachen Mao, Qing Yang, Ang Li, Hai Li, Yiran Chen. 102 [doi]
• Enabling File-Oriented Fast Secure Deletion on Shingled Magnetic Recording DrivesShuo-Han Chen, Ming-Chang Yang, Yuan-Hao Chang, Chun-Feng Wu. 103 [doi]
• Enabling Failure-resilient Intermittently-powered Systems Without Runtime CheckpointingWei-Ming Chen, Pi-Cheng Hsiu, Tei-Wei Kuo. 104 [doi]
• Sensor Drift Calibration via Spatial Correlation Model in Smart BuildingTinghuan Chen, Bingqing Lin, Hao Geng, Bei Yu 0001. 105 [doi]
• Machine Learning-Based Pre-Routing Timing Prediction with Reduced PessimismErick Carvajal Barboza, Nishchal Shukla, Yiran Chen, Jiang Hu. 106 [doi]
• LithoGAN: End-to-End Lithography Modeling with Generative Adversarial NetworksWei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan. 107 [doi]
• A General Cache Framework for Efficient Generation of Timing Critical PathsKuan-Ming Lai, Tsung-Wei Huang, Tsung-Yi Ho. 108 [doi]
• Effective-Resistance Preserving Spectral Reduction of GraphsZhiqiang Zhao, Zhuo Feng. 109 [doi]
• Revisiting the ARM Debug Facility for OS Kernel SecurityJinsoo Jang, Brent ByungHoon Kang. 110 [doi]
• Low-Overhead Power Trace Obfuscation for Smart Meter PrivacyDaniele Jahier Pagliari, Sara Vinco, Enrico Macii, Massimo Poncino. 111 [doi]
• ARM2GC: Succinct Garbled Processor for Secure ComputationEbrahim M. Songhori, M. Sadegh Riazi, Siam U. Hussain, Ahmad-Reza Sadeghi, Farinaz Koushanfar. 112 [doi]
• Filianore: Better Multiplier Architectures for LWE-based Post-Quantum Key ExchangeSong Bian, Masayuki Hiromoto, Takashi Sato. 113 [doi]
• Adaptive Granularity Encoding for Energy-efficient Non-Volatile Main MemoryJie Xu, Dan Feng 0001, Yu Hua 0001, Wei Tong, Jingning Liu, Chunyan Li, Gaoxiang Xu, Yiran Chen. 114 [doi]
• Magma: A Monolithic 3D Vertical Heterogeneous ReRAM-based Main Memory ArchitectureFarzaneh Zokaee, Mingzhe Zhang, Xiaochun Ye, Dongrui Fan, Lei Jiang 0001. 115 [doi]
• A Wear-Leveling-Aware Fine-Grained Allocator for Non-Volatile MemoryXianzhang Chen, Qingfeng Zhuge, Qiang Sun, Edwin Hsing-Mean Sha, Shouzhen Gu, Chaoshu Yang, Chun Jason Xue. 116 [doi]
• DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI PlacementYibo Lin, Shounak Dhar, Wuxi Li, Haoxing Ren, Brucek Khailany, David Z. Pan. 117 [doi]
• BiG: A Bivariate Gradient-Based Wirelength Model for Analytical Circuit PlacementFan-Keng Sun, Yao-Wen Chang. 118 [doi]
• Routability-driven Mixed-size Placement Prototyping Approach Considering Design Hierarchy and Indirect Connectivity Between MacrosJai-Ming Lin, Szu-Ting Li, Yi-ting Wang. 119 [doi]
• NCTUcell: A DDA-Aware Cell Library Generator for FinFET Structure with Implicitly Adjustable Grid MapYih-Lang Li, Shih-Ting Lin, Shinichi Nishizawa, Hong-Yan Su, Ming-Jie Fong, Oscar Chen, Hidetoshi Onodera. 120 [doi]
• Design Principles for True Random Number Generators for Security ApplicationsMilos Grujic, Vladimir Rozic, David Johnston, John Kelsey, Ingrid Verbauwhede. 121 [doi]
• Rapid Generation of High-Qality RISC-V Processors from Functional Instruction Set SpecificationsGai Liu, Joseph Primmer, Zhiru Zhang. 122 [doi]
• autoAx: An Automatic Design Space Exploration and Circuit Building Methodology utilizing Libraries of Approximate ComponentsVojtech Mrazek, Muhammad Abdullah Hanif, Zdenek Vasícek, Lukás Sekanina, Muhammad Shafique 0001. 123 [doi]
• Graph-Morphing: Exploiting Hidden Parallelism of Non-Stencil Computation in High-Level SynthesisYu Zou, Mingjie Lin. 124 [doi]
• Overcoming Data Transfer Bottlenecks in FPGA-based DNN Accelerators via Layer Conscious Memory ManagementXuechao Wei, Yun Liang 0001, Jason Cong. 125 [doi]
• High-Level Synthesis of Resource-oriented Approximate Designs for FPGAsMarcos T. Leipnitz, Gabriel L. Nazar. 126 [doi]
• Improving Scalability of Exact Modulo Scheduling with Specialized Conflict-Driven LearningSteve Dai, Zhiru Zhang. 127 [doi]
• LAcc: Exploiting Lookup Table-based Fast and Accurate Vector Multiplication in DRAM-based CNN AcceleratorQuan Deng, Youtao Zhang, Minxuan Zhang, Jun Yang. 128 [doi]
• DRIS-3: Deep Neural Network Reliability Improvement Scheme in 3D Die-Stacked Memory based on Fault AnalysisJae-San Kim, Joon-Sung Yang. 129 [doi]
• X-MANN: A Crossbar based Architecture for Memory Augmented Neural NetworksAshish Ranjan, Shubham Jain, Jacob R. Stevens, Dipankar Das 0002, Bharat Kaul, Anand Raghunathan. 130 [doi]
• On-Chip Memory Technology Design Space Explorations for Mobile Deep Neural Network AcceleratorsHaitong Li, Mudit Bhargava, Paul N. Whatmough, H.-S. Philip Wong. 131 [doi]
• SkippyNN: An Embedded Stochastic-Computing Accelerator for Convolutional Neural NetworksReza Hojabr, Kamyar Givaki, S. M. Reza Tayaranian, Parsa Esfahanian, Ahmad Khonsari, Dara Rahmati, M. Hassan Najafi. 132 [doi]
• ZARA: A Novel Zero-free Dataflow Accelerator for Generative Adversarial Networks in 3D ReRAMFan Chen, Linghao Song, Hai Helen Li, Yiran Chen. 133 [doi]
• X-DeepSCA: Cross-Device Deep Learning Side Channel AttackDebayan Das, Anupam Golder, Josef Danial, Santosh Ghosh, Arijit Raychowdhury, Shreyas Sen. 134 [doi]
• Attacking Split Manufacturing from a Deep Learning PerspectiveHaocheng Li, Satwik Patnaik, Abhrajit Sengupta, Haoyu Yang, Johann Knechtel, Bei Yu 0001, Evangeline F. Y. Young, Ozgur Sinanoglu. 135 [doi]
• ALAFA: Automatic Leakage Assessment for Fault Attack CountermeasuresSayandeep Saha, S. Nishok Kumar, Sikhar Patranabis, Debdeep Mukhopadhyay, Pallab Dasgupta. 136 [doi]
• ChipSecure: A Reconfigurable Analog eFlash-Based PUF with Machine Learning Attack Resiliency in 55nm CMOSMohammad Reza Mahmoodi, Hussein Nili, Shabnam Larimian, Xinjie Guo, Dmitri B. Strukov. 137 [doi]
• Adversarial Attack against Modeling Attack on PUFsSying-Jyan Wang, Yu-Shen Chen, Katherine Shu-Min Li. 138 [doi]
• RFTC: Runtime Frequency Tuning Countermeasure Using FPGA Dynamic Reconfiguration to Mitigate Power Analysis AttacksDarshana Jayasinghe, Aleksandar Ignjatovic, Sri Parameswaran. 139 [doi]
• Design Guidelines of RRAM based Neural-Processing-Unit: A Joint Device-Circuit-Algorithm AnalysisWenqiang Zhang, Xiaochen Peng, Huaqiang Wu, Bin Gao 0006, Hu He, Youhui Zhang, Shimeng Yu, He Qian. 140 [doi]
• QURE: Qubit Re-allocation in Noisy Intermediate-Scale Quantum ComputersAbdullah Ash-Saki, Mahabubul Alam, Swaroop Ghosh. 141 [doi]
• Mapping Quantum Circuits to IBM QX Architectures Using the Minimal Number of SWAP and H OperationsRobert Wille, Lukas Burgholzer, Alwin Zulehner. 142 [doi]
• Computing Radial Basis Function Support Vector Machine using DNA via Fractional CodingXingyi Liu, Keshab K. Parhi. 143 [doi]
• AlignS: A Processing-In-Memory Accelerator for DNA Short Read Alignment Leveraging SOT-MRAMShaahin Angizi, Jiao Sun, Wei Zhang, Deliang Fan. 144 [doi]
• MiniControl: Synthesis of Continuous-Flow Microfluidics with Strictly Constrained Control PortsXing Huang, Tsung-Yi Ho, Wenzhong Guo, Bing Li, Ulf Schlichtmann. 145 [doi]
• Faster Region-based Hotspot DetectionRan Chen, Wei Zhong, Haoyu Yang, Hao Geng, Xuan Zeng 0001, Bei Yu 0001. 146 [doi]
• Efficient Layout Hotspot Detection via Binarized Residual Neural NetworkYiyang Jiang, Fan Yang, Hengliang Zhu, Bei Yu 0001, Dian Zhou, Xuan Zeng 0001. 147 [doi]
• DeePattern: Layout Pattern Generation with Transforming Convolutional Auto-EncoderHaoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu 0001. 148 [doi]
• GAN-SRAF: Sub-Resolution Assist Feature Generation Using Conditional Generative Adversarial NetworksMohamed Baker Alawieh, Yibo Lin, Zaiwei Zhang, Meng Li 0004, Qixing Huang, David Z. Pan. 149 [doi]
• Meta-Model based High-Dimensional Yield Analysis using Low-Rank Tensor ApproximationXiao Shi, Hao Yan, Qiancun Huang, Jiajia Zhang, Longxing Shi, Lei He. 150 [doi]
• Novel Guiding Template and Mask Assignment for DSA-MP Hybrid Lithography Using Multiple BCP MaterialsYi-Ting Lin, Iris Hui-Ru Jiang. 151 [doi]
• Actors Revisited for Time-Critical SystemsMarten Lohstroh, Martin Schoeberl, Andrés Goens, Armin Wasicek, Christopher Gill, Marjan Sirjani, Edward A. Lee. 152 [doi]
• Time-Predictable Computing by Design: Looking Back, Looking ForwardTulika Mitra. 153 [doi]
• Consolidating High-Integrity, High-Performance, and Cyber-Security Functions on a Manycore ProcessorBenoît Dupont de Dinechin. 154 [doi]
• Efficient GPU NVRAM Persistence with Helper WarpsSui Chen, Faen Zhang, Lei Liu, Lu Peng. 155 [doi]
• FlashGPU: Placing New Flash Next to GPU CoresJie Zhang 0048, Miryeong Kwon, Hyojong Kim, Hyesoon Kim, Myoungsoo Jung. 156 [doi]
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