Table of Contents

• FireGuard: A Generalized Microarchitecture for Fine-Grained Security Analysis on OoO Superscalar CoresZhe Jiang, Sam Ainsworth 0001, Timothy M. Jones 0001. [doi]
• DCDiff: Enhancing JPEG Compression via Diffusion-based DC Coefficients EstimationZiyuan Zhang, Han Qiu 0001, Tianwei Zhang 0004, Bin Chen 0011, Chao Zhang 0008. 1-7 [doi]
• Process-Variation-Aware Design Optimization for Wavelength-Routed Optical Networks-on-ChipLiaoyuan Cheng, Mengchu Li, Tsun-Ming Tseng, Martin Schottenloher, Ulf Schlichtmann. 1-7 [doi]
• Scalable Community Detection Using Quantum Hamiltonian Descent and QUBO FormulationJinglei Cheng, Ruilin Zhou, Yuhang Gan, Chen Qian 0001, Junyu Liu. 1-7 [doi]
• SpecASR: Accelerating LLM-based Automatic Speech Recognition via Speculative DecodingLinye Wei, Shuzhang Zhong, Songqiang Xu, Runsheng Wang, Ru Huang 0001, Meng Li 0004. 1-7 [doi]
• Late Breaking Results: The Hidden Risks of Activation Duration in PLPUFsMohamed Alsharkawy, Jan Zwerschke, Hassan Nassar, Jeferson González-Gómez, Jörg Henkel. 1-2 [doi]
• DROIDFUZZ: Proprietary Driver Fuzzing for Embedded Android DevicesJianzhong Liu, Yuheng Shen, Yifei Chu, Qiang Zhang, Heyuan Shi, Wanli Chang 0001, Yu Jiang 0001. 1-7 [doi]
• InsightAlign: A Transferable Physical Design Recipe Recommender Based on Design InsightsHao-Hsiang Hsiao, Sudipto Kundu, Wei Zeng, Wei-Ting Chan, Deyuan Guo, Sung Kyu Lim. 1-7 [doi]
• Approximate SMT Counting Beyond Discrete DomainsArijit Shaw, Kuldeep S. Meel. 1-7 [doi]
• Ragnar: Exploring Volatile-Channel Vulnerabilities on RDMA NICYunpeng Xu, Yuchen Fan, Teng Ma, Shuwen Deng. 1-7 [doi]
• Secondary-Power-Cell-Aware Detailed Placement in Multiple Power Domain DesignsYu-wei Chang, Shao-Yun Fang, Kai-Chuan Yang, Min-Ching Lin. 1-7 [doi]
• Invited: Enhancing Test Quality by Targeting Timing Marginalities Due to Process VariationsAdit D. Singh, Mukarram Ali Faridi. 1-4 [doi]
• Weighted Range-Constrained Ising-Model Decoder for Quantum Error CorrectionXinyi Guo, Hiromitsu Awano, Takashi Sato 0001. 1-7 [doi]
• UniCAIM: A Unified CAM/CIM Architecture with Static-Dynamic KV Cache Pruning for Efficient Long-Context LLM InferenceWeikai Xu, Wenxuan Zeng, Qianqian Huang, Meng Li 0004, Ru Huang 0001. 1-7 [doi]
• BitPattern: Enabling Efficient Bit-Serial Acceleration of Deep Neural Networks through Bit-Pattern PruningGang Wang 0063, Siqi Cai, Zhenyu Li, Wenjie Li 0003, Dongxu Lyu, Yanan Sun 0003, Jianfei Jiang 0001, Guanghui He. 1-7 [doi]
• NeuralMesh: Neural Network For FEM Mesh Generation in 2.5D/3D Chiplet Thermal SimulationPengju Chen, Dan Niu, Dekang Zhang, Wenhao Wang, Depeng Xie, Zhou Jin 0001, Wei W. Xing, Lei He 0001. 1-7 [doi]
• SAGA: A Memory-Efficient Accelerator for GANN Construction via Harnessing Vertex SimilarityRuiyang Chen, Xueyuan Liu 0001, Chunyu Qi, Yuanzheng Yao, Yanan Sun 0003, Xiaoyao Liang, Zhuoran Song. 1-7 [doi]
• PyraNet: A Multi-Layered Hierarchical Dataset for VerilogBardia Nadimi, Ghali Omar Boutaib, Hao Zheng 0001. 1-7 [doi]
• Data Oblivious CPU: Microarchitectural Side-channel Leakage-Resilient ProcessorBehnam Omidi, Ihsen Alouani, Khaled N. Khasawneh. 1-7 [doi]
• Harnessing Conventional Video Processing Insights for Emerging 3D Video Generation Models: A Comprehensive Attention-aware WayTianlang Zhao, Jun Liu 0071, Xingyang Li, Li Ding 0012, Jinhao Li 0006, Shuaiheng Li, Jinbo Hu, Guohao Dai. 1-7 [doi]
• Device-Algorithm Co-Design of Ferroelectric Compute-in-Memory In-Situ Annealer for Combinatorial Optimization ProblemsYu Qian, Xianmin Huang, Ranran Wang, Zeyu Yang, Min Zhou, Thomas Kämpfe, Cheng Zhuo, Xunzhao Yin. 1-7 [doi]
• Swift or Exact? Boosting Efficient Microarchitecture DSE via Multi-fidelity Partial Order PredictionHang Liu, Hao Geng, Zhuolun He, Qi Sun 0002, Cheng Zhuo. 1-7 [doi]
• NoiseZO: RRAM Noise-Driven Zeroth-Order Optimization for Efficient Forward-Only TrainingShuqi Wang, Zhengwu Liu, Chenchen Ding, Chen Zhang, Taiqiang Wu, Jiajun Zhou, Ngai Wong 0001. 1-7 [doi]
• An Input-Aware Sparse Tensor Compiler Empowered by Vectorized AccelerationXianhao He, Haotian Wang 0006, Jiapeng Zhang, Wangdong Yang, Anthony Theodore Chronopoulos, Kenli Li 0001. 1-7 [doi]
• PacQ: A SIMT Microarchitecture for Efficient Dataflow in Hyper-asymmetric GEMMsRuokai Yin, Yuhang Li 0001, Priyadarshini Panda. 1-7 [doi]
• FF-INT8: Efficient Forward-Forward DNN Training on Edge Devices with INT8 PrecisionJingxiao Ma, Priyadarshini Panda, Sherief Reda. 1-7 [doi]
• PipeLink: A Pipelined Resource Sharing System for Dataflow High-Level SynthesisRui Li 0103, Lincoln Berkley, Rajit Manohar. 1-7 [doi]
• Towards Secure Data Management using Multi-Cryptographic Solutions (Invited)Shufan Zhang 0001, Xi He 0001, Ashish Kundu, Sujaya Maiyya, Sharad Mehrotra, Shantanu Sharma 0001. 1-4 [doi]
• BlockPIM: Optimizing Memory Management for PIM-enabled Long-Context LLM InferenceZhichun Li, Jun Zhou, Xueqi Li 0001, Ninghui Sun. 1-7 [doi]
• DBC: Drift-aware Binary Code for Drift-tolerant Deep Neural NetworksInsu Choi, Jaeyong Chung, Joon-Sung Yang. 1-7 [doi]
• GoPTX: Fine-grained GPU Kernel Fusion by PTX-level Instruction Flow WeavingKan Wu, Zejia Lin 0001, Mengyue Xi, Zhongchun Zheng, Wenxuan Pan, Xianwei Zhang 0001, Yutong Lu. 1-7 [doi]
• Hardware-Software Co-design for Distributed Quantum ComputingJi Liu, Allen Zang, Martin Suchara, Tian Zhong, Paul D. Hovland. 1-6 [doi]
• Sphinx: A High-Performance Hybrid Index for Disaggregated Memory With Succinct Filter CacheJingxiang Li, Shengan Zheng, Bowen Zhang 0012, Hankun Dong, Linpeng Huang. 1-7 [doi]
• Enhancing LLM-based Quantum Code Generation with Multi-Agent Optimization and Quantum Error CorrectionCharlie Campbell, Hao Mark Chen, Wayne Luk, Hongxiang Fan. 1-7 [doi]
• ASRR-PINN: Adaptive Sub-Regional Random Resampling-Based PINN for Thermal Analysis of 3D-ICsZijian Zhou, Min Tang, Liang Chen. 1-7 [doi]
• STREAMINGGS: Voxel-Based Streaming 3D Gaussian Splatting with Memory Optimization and Architectural SupportChenqi Zhang, Yu Feng 0007, Jieru Zhao, Guangda Liu, Wenchao Ding 0001, Chentao Wu, Minyi Guo. 1-7 [doi]
• Device-Aware Test: A Means to Attack Unmodelled Defects (Invited)Said Hamdioui, Mottaqiallah Taouil. 1-4 [doi]
• CREST-CiM: Cross-Coupling-Enhanced Differential STT-MRAM for Robust Computing-in-Memory in Binary Neural NetworksImtiaz Ahmed, Akul Malhotra, Sumeet Kumar Gupta. 1-7 [doi]
• Late Breaking Results: Advanced PCB Placement with Irregular Components for Efficient Collision Detection and Routability OptimizationChien-Hao Tsou, Zhu-Xun Lee, Yao-Wen Chang. 1-2 [doi]
• A Fast, Iterative Clock Skew Scheduling Algorithm with Dynamic Sequential Graph ExtractionShijian Chen, Yihang Qiu, Biwei Xie, Mingyu Chen 0001, Xingquan Li. 1-7 [doi]
• Enabling Data-Deduplication-Assisted Data Relocation for Interlaced Magnetic RecordingChen-Jui Tu, Shuo-Han Chen. 1-6 [doi]
• SNAPPIX: Efficient-Coding-Inspired In-Sensor Compression for Edge VisionWeikai Lin, Tianrui Ma, Adith Boloor, Yu Feng 0007, Ruofan Xing, Xuan Zhang 0001, Yuhao Zhu 0001. 1-7 [doi]
• Principle-based Dataflow Optimization for Communication Lower Bound in Operator-Fused Tensor AcceleratorLei Xu, Chen Yin, Zelong Yuan, Weiguang Sheng, Jianfei Jiang 0001, Qin Wang 0009, Naifeng Jing. 1-7 [doi]
• A High-Precision and Low-Cost Approximate Transform Accelerator for Video CodingZhijian Hao, Jiaming Liu, Chenlong He, Qi Zheng 0004, ShuShi Chen, Jinchang Xu, Yue Hao 0001, Xiao Yan, Xiaohua Ma 0001. 1-7 [doi]
• Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL DesignJie Zhou, Youshu Ji, Ning Wang 0071, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao 0004, Nan Guan, Zhe Jiang 0004. 1-7 [doi]
• LMM-IR: Large-Scale Netlist-Aware Multimodal Framework for Static IR-Drop PredictionKai Ma, Zhen Wang, Hongquan He, Qi Xu 0004, Tinghuan Chen, Hao Geng. 1-7 [doi]
• FastPath: A Hybrid Approach for Efficient Hardware Security VerificationLucas Deutschmann, Andres Meza 0001, Dominik Stoffel, Wolfgang Kunz, Ryan Kastner. 1-7 [doi]
• Configurable DSP-Based CAM Architecture for Data-Intensive Applications on FPGAsYao Chen 0008, Feng Yu 0003, Di Wu, Weng-Fai Wong, Bingsheng He. 1-7 [doi]
• CXL-INTERPLAY: Unraveling and Characterizing CXL Interference in Modern Computer SystemsShunyu Mao, Jiajun Luo, Yixin Li, Jiapeng Zhou, Weidong Zhang, Zheng Liu, Teng Ma, Shuwen Deng. 1-7 [doi]
• Mitigating Routability Problems in Complementary-FET-based VLSI DesignsJunghyun Yoon, Heechun Park. 1-7 [doi]
• ChipletEM: Physics-Based 2.5D and 3D Chiplet Heterogeneous Integration Electromigration Signoff Tool Using Coupled Stress and Thermal SimulationZeyu Sun, Weijie Tong, Xiaoning Ma, He Cao, Jianyun Liu, Zhiqiang Li, Qinzhi Xu. 1-7 [doi]
• GraphAccel: An In-Storage Accelerator for Efficient Graph-Based Vector Similarity Search Using Page Packing and Speculative Search OptimizationYoonyoung Kwon, Yunjong Boo, Hyungmin Cho. 1-7 [doi]
• LLMs: A Driving Force in Next Generation Digital Design AutomationMatheus T. Moreira, Aram H. Markosyan, Chris Cummins, Warren Hunt, Gabriel Synnaeve, Edith Beigné. 1-6 [doi]
• DRAFT: Decoupling Backpropagation from Pre-trained Backbone for Efficient Transformer Fine-Tuning on EdgeZhirui Huang, Shiwei Liu 0002, Haozhe Zhu, Qi Liu 0010, Chixiao Chen. 1-7 [doi]
• REMU: Memory-aware Radiation Emulation via Dual Addressing for In-orbit Deep Learning SystemLongnv Xu, Meiqi Wang, Han Qiu 0001, Jun Liu 0063, Yuanjie Li, Hewu Li. 1-7 [doi]
• GSAcc: Accelerate 3D Gaussian Splatting via Depth Speculation and Gaussian-centric RasterizationMengtian Yang, Yipeng Wang 0017, Chieh-Pu Lo, Xiuhao Zhang, Sirish Oruganti, Jaydeep P. Kulkarni. 1-7 [doi]
• Late Breaking Results: Breaking Symmetry - Unconventional Placement of Analog Circuits using Multi-Level Multi-Agent Reinforcement LearningSupriyo Maji, Linran Zhao, Souradip Poddar, David Z. Pan. 1-2 [doi]
• Monolithic 3D FPGA Design and Synthesis with Back-End-of-Line Configuration MemoriesFaaiq Waqar, Jiahao Zhang, Anni Lu, Zifan He, Jason Cong, Shimeng Yu. 1-7 [doi]
• Intermittent Systems at Small Scale: Execution Model and Design GuidelinesYoungbin Kim, Yoojin Lim. 1-7 [doi]
• DyREM: Dynamically Mitigating Quantum Readout Error with Embedded AcceleratorKaiwen Zhou, Liqiang Lu, Hanyu Zhang, Debin Xiang, Chenning Tao, Xinkui Zhao, Size Zheng 0001, Jianwei Yin. 1-7 [doi]
• Learning-Aided Safe Controller Synthesis with Formal Guarantees via Vector Barrier CertificatesXia Zeng, Mengxin Ren, Zhiming Liu, Zhengfeng Yang. 1-7 [doi]
• ResISC: Residue Number System-Based Integrated Sensing and Computing for Efficient Edge AISepehr Tabrizchi, Samin Sohrabi, Mohamadreza Mohammadi, Ramtin Zand, Shaahin Angizi, Arman Roohi. 1-7 [doi]
• AdreamDCO: AI-Driven Robust and Efficient Design Automation for Digitally Controlled OscillatorsYaolong Hu, Hao Guo, Shikai Wang, Jiaqi Liu, Weidong Cao, Taiyun Chi. 1-7 [doi]
• Self-Attention to Operator Learning-based 3D-IC Thermal SimulationZhen Huang, Hong Wang, Wenkai Yang, Muxi Tang, Depeng Xie, Ting-Jung Lin, Yu Zhang 0086, Wei W. Xing, Lei He 0001. 1-7 [doi]
• UniCoS: A Unified Neural and Accelerator Co-Search Framework for CNNs and ViTsWei Fu, Wenqi Lou, Cheng Tang 0004, Hongbing Wen, Yunji Qin, Lei Gong, Chao Wang 0003, Xuehai Zhou. 1-6 [doi]
• Late Breaking Results: Novel Design of MTJ-Based Unified LIF Spiking Neuron and PUFMilad Tanavardi Nasab, Wu Yang, Himanshu Thapliyal. 1-2 [doi]
• Adora Compiler: End-to-End Optimization for High-Efficiency Dataflow Acceleration and Task Pipelining on CGRAsJiahang Lou, Qilong Zhu, Yuan Dai, Zewei Zhong, Wenbo Yin, Lingli Wang. 1-7 [doi]
• Enabling On-Tiny-Device Model Personalization via Gradient Condensing and Alternant Partial UpdateZhenge Jia, Yiyang Shi, Zeyu Bao, Zirui Wang, Xin Pang, Huiguo Liu, Yu Duan, Zhaoyan Shen, Mengying Zhao. 1-7 [doi]
• AmpereBleed: Exploiting On-chip Current Sensors for Circuit-Free Attacks on ARM-FPGA SoCsXin Zhang 0110, Yi Yang, Jiajun Zou, Qingni Shen, Zhi Zhang 0001, Yansong Gao 0001, Zhonghai Wu, Trevor E. Carlson. 1-7 [doi]
• Efficient Recycling Subspace Truncation Method for Periodic Small-Signal AnalysisYuncheng Xu, Fan Yang, Yangfeng Su. 1-7 [doi]
• Late Breaking Results: Warpage-Aware Generative Floorplanning for Reliable Advanced PackagingMin-Hung Chen, Cheng Yen Li, Chuan-Chi Su, Yao-Wen Chang, Tung-Chieh Chen. 1-2 [doi]
• CAE-DFKD: Bridging the Transferability Gap in Data-Free Knowledge DistillationZherui Zhang, Changwei Wang 0001, Rongtao Xu, Wenhao Xu, Shibiao Xu, Yu Zhang 0133, Jie Zhou, Li Guo 0004. 1-7 [doi]
• CaMDN: Enhancing Cache Efficiency for Multi-tenant DNNs on Integrated NPUsTianhao Cai, Liang Wang 0020, Limin Xiao, Meng Han, Zeyu Wang, Lin Sun, Xiaojian Liao. 1-7 [doi]
• InfScaler: Enabling Efficient ML Inference Serving on Multi-Accelerator Edge Devices via Asymmetric Auto-ScalingBorui Li, Tiange Xia, Shuai Wang, Shuai Wang. 1-7 [doi]
• YOCO: A Hybrid In-Memory Computing Architecture with 8-bit Sub-PetaOps/W In-Situ Multiply Arithmetic for Large-Scale AIZihao Xuan, Yuxuan Yang, Wei Xuan, Zijia Su, Song Chen 0001, Yi Kang. 1-7 [doi]
• LeakyDSP: Exploiting Digital Signal Processing Blocks to Sense Voltage Fluctuations in FPGAsXin Zhang 0110, Jiajun Zou, Yi Yang, Qingni Shen, Zhi Zhang 0001, Yansong Gao 0001, Zhonghai Wu, Trevor E. Carlson. 1-7 [doi]
• EnQode: Fast Amplitude Embedding for Quantum Machine Learning Using Classical DataJason Han, Nicholas S. DiBrita, Younghyun Cho, Hengrui Luo, Tirthak Patel. 1-7 [doi]
• Power-Constrained Printed Neuromorphic Hardware TrainingTara Gheshlaghi, Haibin Zhao, Priyanjana Pal, Michael Hefenbrock, Michael Beigl, Mehdi B. Tahoori. 1-7 [doi]
• Accelerating design-technology co-development using neural compact modeling and data-driven SPICE simulationYongjeong Lee, Seungsoo Lee, Jeongyeol Kim, Jungyun Choi, Zhaojie Li, Dehuang Wu, Joddy Wang. 1-6 [doi]
• Easz: An Agile Transformer-based Image Compression Framework for Resource-constrained IoTsYu Mao 0001, Jingzong Li, Jun Wang, Hong Xu 0001, Tei-Wei Kuo, Nan Guan, Chun Jason Xue. 1-7 [doi]
• PISA: Efficient Precision-Slice Framework for LLMs with Adaptive Numerical TypeNing Yang, Zongwu Wang, Qingxiao Sun, Liqiang Lu, Fangxin Liu. 1-7 [doi]
• A Data-Centric Hardware Accelerator for Efficient Adaptive Radix TreeJin Zhao 0003, Yu Zhang 0027, Jun Huang, Weihang Yin, Hui Yu, Hao Qi 0004, Zixiao Wang 0005, Longlong Lin, Xiaofei Liao, Hai Jin 0001. 1-7 [doi]
• PastATPG: A Hybrid ATPG Framework for Better Test Compaction with Partial Assignment SATZhiteng Chao, Xindi Zhang, Xinyu Zhang, Jianan Mu, Zizhen Liu, Shengwen Liang, Shaowei Cai 0001, Jing Ye 0001, Xiaowei Li 0001, Huawei Li 0001. 1-7 [doi]
• PICK: An SRAM-based Processing-in-Memory Accelerator for K-Nearest-Neighbor Search in Point CloudsChen Nie, Chao Jiang, Liming Xiao, Weifeng Zhang 0003, Zhezhi He. 1-7 [doi]
• On Bit-level Reverse Engineering of Vehicular CAN BusYunlang Cai, Hanxue Shi, Xiaohang Wang, Haoting Shen, Li Lu 0008, Kui Ren 0001. 1-7 [doi]
• Identifying System-on-Chip Security Assets with Structure-Based AnalysisWei-Kai Liu, Benjamin Tan 0001, Krishnendu Chakrabarty. 1-7 [doi]
• ESM: A Framework for Building Effective Surrogate Models for Hardware-Aware Neural Architecture SearchAzaz-Ur-Rehman Nasir, Samroz Ahmad Shoaib, Muhammad Abdullah Hanif, Muhammad Shafique 0001. 1-7 [doi]
• Comprehensive Placement and Routing Framework with Guaranteed In-Cell Routability for Synthesizing Complementary-FET CellsZhengzhe Zheng, Yinuo Wu, Keyu Peng, Chao Wang, Ziran Zhu. 1-6 [doi]
• GPart: A GNN-Enabled Multilevel Graph PartitionerMagi Chen, Ting-Chi Wang. 1-7 [doi]
• Leveraging Critical Proof Obligations for Efficient IC3 VerificationLingfeng Zhu, Xindi Zhang, Yongjian Li, Shaowei Cai 0001. 1-7 [doi]
• ATLAS: A Self-Supervised and Cross-Stage Netlist Power Model for Fine-Grained Time-Based Layout Power AnalysisWenkai Li, Yao Lu, Wenji Fang, Jing Wang 0171, Qijun Zhang, Zhiyao Xie. 1-7 [doi]
• Exploiting Power Side-Channel Vulnerabilities in XGBoost AcceleratorYimeng Xiao, Archit Gajjar, Aydin Aysu, Paul Franzon. 1-7 [doi]
• Late Breaking Results: Source-Aware Adaptive Cache Management for CXL-enabled Disaggregated Memory SharingQianyu Cheng, Jiajun Ji, Teng Wang, Zihan Wang, Lei Gong, Chao Wang 0003, Xuehai Zhou. 1-2 [doi]
• MHDiff: Memory- and Hardware-Efficient Diffusion Acceleration via Focal Pixel Aware QuantizationChunyu Qi, Xuhang Wang, Ruiyang Chen, Yuanzheng Yao, Naifeng Jing, Chen Zhang, Jun Wang, Zhihui Fu, Xiaoyao Liang, Zhuoran Song. 1-7 [doi]
• Security Opportunities and Challenges for Disaggregated Architectures (Invited)Elisa Bertino, Imtiaz Karim, Ashish Kundu. 1-4 [doi]
• ADVISOR: Approximate Computing-frienDly High-LeVel Synthesis DesIgn Space ExplORerBaharealsadat Parchamdar, Benjamin Carrión Schäfer. 1-7 [doi]
• ALLMod: Exploring Area-Efficiency of LUT-based Large Number Modular Reduction via Hybrid WorkloadsFangxin Liu, Haomin Li 0002, Zongwu Wang, Bo Zhang, Mingzhe Zhang, Shoumeng Yan, Li Jiang 0002, Haibing Guan. 1-7 [doi]
• Power-Grid Structure Exploration with Unified Sequence-based Learning FrameworkYi-Lin Chuang, Hao-Wei Chan, Chih-Yun Yen, Shih-An Hsieh, Ching-Feng Chen, Sheng-Te Lai. 1-7 [doi]
• CognitiveArm: Enabling Real-Time EEG-Controlled Prosthetic Arm Using Embodied Machine LearningAbdul Basit, Maha Nawaz, Saim Rehman, Muhammad Shafique 0001. 1-7 [doi]
• Energy-Efficient Large-Scale Vector Similarity Search in NAND-Flash via Hybrid MatchingChih-Yu Hu, Chi-Tse Huang, Hao-Wei Chiang, Hsiang-Yun Cheng, Po-Hao Tseng, Ming-Hsiu Lee, An-Yeu Andy Wu. 1-7 [doi]
• Uncertainty-Aware Energy Management for Wearable IoT Devices with Conformal PredictionDina Hussein, Chibuike E. Ugwu, Ganapati Bhat, Janardhan Rao Doppa. 1-7 [doi]
• RAP-Track: Efficient Control Flow Attestation via Parallel Tracking in Commodity MCUsAntonio Joia Neto, Adam Caulfield, Ivan De Oliveira Nunes. 1-7 [doi]
• DDRoute: a Novel Depth-Driven Approach to the Qubit Routing ProblemAlessandro Annechini, Marco Venere, Donatella Sciuto, Marco D. Santambrogio. 1-7 [doi]
• Real-Time Dynamic IR-drop Prediction for IR ECOYu-Che Lee, Yu-Hsuan Chen, Yu-Chen Cheng, Yong-Fong Chang, Jia-Wei Lin, Hsun-Wei Pao, Yung-Chih Chen, Yi-Ting Li, Wuqian Tang, Shih-Chieh Chang, Chun-Yao Wang. 1-7 [doi]
• Mr.TPL: A Method for Multi-Pin Net Router in Triple Patterning LithographyChengkai Wang, Weiqing Ji, Mingyang Kou, Zhiyang Chen 0006, Fei Li, Nengyong Zhu, Hailong Yao. 1-6 [doi]
• DM-Tune: Quantizing Diffusion Models with Mixture-of-Gaussian Guided Noise TuningPouya Haghi, Ali Falahati, Zahra Azad, Chunshu Wu, Ruibing Song, Chuan Liu 0001, Ang Li 0006, Tong Geng. 1-7 [doi]
• MAS-ISP: A Proxy-Free Online Hyperparameter Optimization Framework for ISP Hardware SystemJiaming Liu, Xuan Huang, Zhijian Hao, Ruoxi Zhu, Qi Zheng 0004, Shuocheng Wang, ShuShi Chen, Chang Liu, Leilei Huang, Jun Tao 0001, Yibo Fan. 1-7 [doi]
• TetrisLock: Quantum Circuit Split Compilation with Interlocking PatternsQian Wang, Jayden John, Ben Dong, Yuntao Liu. 1-7 [doi]
• NDFT: Accelerating Density Functional Theory Calculations via Hardware/Software Co-Design on Near-Data Computing SystemQingcai Jiang, Buxin Tu, Xiaoyu Hao, Junshi Chen, Hong An. 1-7 [doi]
• Espresso: Exploiting the Sparsity Property in Event Sensors with Spatiotemporal OrderingLeshan Li, Hongyi Li, Qingyuan Yang, Mingtao Ou, Rong Zhao, Xinglong Ji. 1-7 [doi]
• HeteroSVD: Efficient SVD Accelerator on Versal ACAP with Algorithm-Hardware Co-DesignXinya Luan, Zhe Lin 0001, Kai Shi, Jianwang Zhai, Kang Zhao. 1-7 [doi]
• PIMDup: An Optimized Deduplication Design on a Real Processing-in-Memory SystemChun-Le Yeh, Liang-Chi Chen, Chien-Chung Ho, Yu-Ming Chang, Da-Wei Chang. 1-7 [doi]
• SimPhony: A Device-Circuit-Architecture Cross-Layer Modeling and Simulation Framework for Heterogeneous Electronic-Photonic AI SystemZiang Yin, Meng Zhang 0023, Nicholas Gangi, Z. Rena Huang, Jeff Jun Zhang, Jiaqi Gu 0002. 1-7 [doi]
• PoP-ECC: Robust and Flexible Error Correction against Multi-Bit Upsets in DNN AcceleratorsTaewon Park, Saeid Gorgin, Dongwhee Kim, Jaeho Shin, Michael B. Sullivan, Jungrae Kim. 1-7 [doi]
• Look Before You Leap: A Self-Review Bayesian Optimization Method for Constrained High-Dimensional Design Space ExplorationXuyang Zhao, Yiyang Zhao, Zheng Wu, Tianning Gao, Zhaori Bi, Changhao Yan, Dian Zhou, Xuan Zeng 0001. 1-7 [doi]
• iTaskSense: Task-Oriented Object Detection in Resource-Constrained EnvironmentsSungheon Jeon, Hamza Errahmouni Barkam, Hyunwoo Oh, Hanning Chen, Tamoghno Das, Zhen Ye, Mohsen Imani. 1-7 [doi]
• RUPlace: Optimizing Routability via Unified Placement and Routing FormulationYifan Chen, Jing Mai, Zuodong Zhang, Yibo Lin. 1-7 [doi]
• GSIM: Accelerating RTL Simulation for Large-Scale DesignsLu Chen, Dingyi Zhao, Zihao Yu, Ninghui Sun, Yungang Bao. 1-7 [doi]
• Quantum-Resistant Security: PQC Readiness and Research Challenges (Invited)Ashish Kundu, Ramana Kompella. 1-4 [doi]
• DenSparSA: A Balanced Systolic Array Approach for Dense and Sparse Matrix MultiplicationZiheng Wang, Ruiqi Sun, Xin He, Tianrui Ma, An Zou. 1-7 [doi]
• LEMOE: LLM-Enhanced Multi-Objective Bayesian Optimization for Microarchitecture ExplorationJingyuan Li, Jianrong Zhang, Ye Li, Wenbo Yin, Lingli Wang. 1-7 [doi]
• Supporting Register-based Addressing Modes for in-DRAM PIM ISAsSeok Young Kim, Byung Ho Choi, Seokwon Kang, Yongjun Park, Seon Wook Kim. 1-6 [doi]
• Leopard: Hardware Pass-Through Remote Storage Access with Queue Concurrency for Edge Intelligent WorkstationsWenjie Wang, Bo Peng, Jianguo Yao, Haibing Guan. 1-7 [doi]
• G-SpNN: GPU-Accelerated Passivity Enforcement for S-Parameter Modeling with Neural NetworksLijie Zeng, Jiatai Sun, Xiao Wu, Dan Niu, Tianshi Wang, Yibo Lin, Zuochang Ye, Zhou Jin 0001. 1-7 [doi]
• LLMShare: Optimizing LLM Inference Serving with Hardware Architecture ExplorationHongduo Liu, Chen Bai, Peng Xu, Lihao Yin, Xianzhi Yu, Hui-Ling Zhen, Mingxuan Yuan, Tsung-Yi Ho, Bei Yu 0001. 1-7 [doi]
• CXL-ECC: an Efficient LRC-based on-CXL-Memory-eXpander-Controller ECC to Enhance Reliability and Performance of DRAM Error CorrectionYixuan Liu, Yunfei Gu, Junhao Dai, Xinyuan Wu, Chentao Wu, Xinfei Guo, Jieru Zhao, Jie Li 0002, Minyi Guo. 1-7 [doi]
• SynCircuit: Automated Generation of New Synthetic RTL Circuits Can Enable Big Data in CircuitsShang Liu 0006, Jing Wang 0171, Wenji Fang, Zhiyao Xie. 1-7 [doi]
• FactorHD: A Hyperdimensional Computing Model for Multi-Object Multi-Class Representation and FactorizationYifei Zhou, Xuchu Huang, Chenyu Ni, Min Zhou, Zheyu Yan, Xunzhao Yin, Cheng Zhuo. 1-7 [doi]
• MemSens: Significantly Reducing Memory Overhead in Adjoint Sensitivity Analysis Using Novel Error-Bounded Lossy CompressionChenxi Li, Yihang Feng, Fuxing Deng, Dingwen Tao, Weifeng Liu 0002, Zhou Jin 0001. 1-7 [doi]
• Centralized Training and Decentralized Control through the Actor-Critic Paradigm for Highly Optimized MulticoresBenedikt Dietrich, Heba Khdr, Jörg Henkel. 1-7 [doi]
• VEDA: Efficient LLM Generation Through Voting-based KV Cache Eviction and Dataflow-flexible AcceleratorZhican Wang, Hongxiang Fan, Haroon Waris, Gang Wang 0063, Zhenyu Li, Jianfei Jiang 0001, Yanan Sun 0003, Guanghui He. 1-7 [doi]
• To Tackle Cost-Skew Tradeoff: An Adaptive Learning Approach for Hub Node SelectionGuowei Sun, Lin Chen, Qiming Huang, Hu Ding. 1-7 [doi]
• SQ-DM: Accelerating Diffusion Models with Aggressive Quantization and Temporal SparsityZichen Fan, Steve Dai, Rangharajan Venkatesan, Dennis Sylvester, Brucek Khailany. 1-7 [doi]
• Expanding Logical Space Freely: A Memory-efficient Mapping Table Design for Compressional SSDsZixuan Huang, Tianyu Wang 0009, Kecheng Huang, Zelin Du, Zili Shao. 1-7 [doi]
• StreamCSD: SSD-Autonomous Stream Management via In-Storage Content LearningWenjie Li, Xiang Chen, Yelin Shan, Jiapin Wang, Yunxin Huang, Yafei Yang, Tao Lu, You Zhou 0009, Fei Wu 0005. 1-7 [doi]
• INSIGHT: A Universal Neural Simulator Framework for Analog Circuits with Autoregressive TransformersSouradip Poddar, Youngmin Oh, Yao Lai, Hanqing Zhu, Bosun Hwang, David Z. Pan. 1-7 [doi]
• YAP: Yield Modeling and Simulation for Advanced PackagingZhichao Chen, Puneet Gupta. 1-7 [doi]
• Decoupling Analog Circuit Representation from Technology for Behavior-Centric OptimizationJintao Li, Haochang Zhi, Jiang Xiao, Keren Zhu 0001, Yun Li 0002. 1-7 [doi]
• Efficient Weight Mapping and Resource Scheduling on Crossbar-based Multi-core CIM SystemsHanjie Liu, Sifan Sun, Aifei Zhang, Haiyan Qin, Yutong Wu, Minhao Gu, Shihang Fu, Shuaikai Liu, Baosen Liu, Wang Kang 0001. 1-6 [doi]
• SDM-PEB: Spatial-Depthwise Mamba for Enhanced Post-Exposure Bake SimulationZiyang Yu, Peng Xu, Zixiao Wang, Binwu Zhu, Qipan Wang, Yibo Lin, Runsheng Wang, Bei Yu 0001, Martin D. F. Wong. 1-7 [doi]
• Accuracy Is Not Always We Need: Precision-Aware Bayesian Yield OptimizationJing Kou, Zidong Chen, Liang Zhang, Haiyan Qin, Wang Kang 0001, Wei W. Xing. 1-7 [doi]
• PiSPICE: Accelerating Post-Layout SPICE Simulation via Essential Parasitic IdentificationZhou Jin, Jing Li, Jian-xin, Tianjia Zhou, Xiao Wu, Dan Niu, Zuochang Ye. 1-7 [doi]
• GTN-Path: Efficient Path Timing Prediction through Waveform Propagation with Graph TransformerLihao Liu, Beisi Lu, Yunhui Li, Li Shang, Fan Yang. 1-7 [doi]
• Late Breaking Results: Multi-Objective Multi-Bit Flip-Flop Placement Considering Pre-Placed CellsCheng Yen Li, Chuan-Chi Su, Zheng-Wei Chen, Shao-Hsiang Chen, Yao-Wen Chang. 1-2 [doi]
• "OOPS!": Out-Of-Band Remote Power Side-Channel Attacks on Intel SGX and TDXNimish Mishra, Kislay Arya, Sarani Bhattacharya, Paritosh Saxena, Debdeep Mukhopadhyay. 1-7 [doi]
• AutoSkewBMT: Autonomously Synthesizing Optimized Integrity Authentication Mechanism for DNN AcceleratorsRakin Muhammad Shadab, Sanjay Gandham, Mingjie Lin. 1-7 [doi]
• HPIM-NoC: A Priori-Knowledge-Based Optimization Framework for Heterogeneous PIM-Based NoCsShuai Yuan 0016, Angxin Cai, Qiushi Lin, Guoxing Wang, Yu Wang, Zhenhua Zhu, Yanan Sun 0003. 1-7 [doi]
• SeDA: Secure and Efficient DNN Accelerators with Hardware/Software SynergyWei Xuan, Zhongrui Wang, Lang Feng 0001, Ning Lin, Zihao Xuan, Rongliang Fu, Tsung-Yi Ho, Yuzhong Jiao, Luhong Liang. 1-7 [doi]
• 3D-SubG: A 3D Stacked Hybrid Processing Near/In-Memory Accelerator for Subgraph GNNsGuoxiang Li, Runnan Xu, Ruohang Xu, Yikan Qiu, Renati Tuerhong, Muhan Zhang, Le Ye, Yufei Ma 0002. 1-7 [doi]
• Efficient Continuous Logic Optimization with Diffusion ModelYikang Ouyang, Xiaofei Yu, Jiadong Zhu, Tinghuan Chen, Yuzhe Ma. 1-7 [doi]
• FeKAN: Efficient Kolmogorov-Arnold Networks Accelerator Using FeFET-based CAM and LUTXuliang Yu, Yu Qian, Xunzhao Yin, Cheng Zhuo, Liang Zhao. 1-7 [doi]
• Rank-based Multi-objective Approximate Logic Synthesis via Monte Carlo Tree SearchYuyang Ye 0001, Xiangfei Hu, Yuchen Liu, Peng Xu, Yu Gong 0002, Tinghuan Chen, Hao Yan 0002, Bei Yu 0001, Longxing Shi. 1-7 [doi]
• Measurement-based uncomputation of quantum circuits for modular arithmeticAlessandro Luongo, Antonio Michele Miti, Varun Narasimhachar, Adithya Sireesh. 1-7 [doi]
• UPVSS: Jointly Managing Vector Similarity Search with Near-Memory Processing SystemsChun-Chien Liu, Chun-Feng Wu, Yunho Jin. 1-7 [doi]
• HiSpTRSV: Exploring Tile-Level Parallelism for SpTRSV Acceleration on FPGAsFan Sun, Fang Dong 0001, Dian Shen. 1-7 [doi]
• ACRS: Adjacent Computation Resource Sharing among Partitioned GPU Sub-CoresPenghao Song, Chongxi Wang, Chenji Han, Haoyu Zhao, Tingting Zhang, Tianyi Liu, Jian Wang. 1-7 [doi]
• Cayman: Custom Accelerator Generation with Control Flow and Data Access OptimizationYouwei Xiao, Fan Cui, Zizhang Luo, Weijie Peng, Yun Liang 0001. 1-7 [doi]
• Guarder: A Stable and Lightweight Reconfigurable RRAM-based PIM Accelerator for DNN IP ProtectionNing Lin, Yi Li 0049, Jiankun Li, Jichang Yang, Yangu He, Yukui Luo, Dashan Shang, Xiaoming Chen 0003, Xiaojuan Qi 0001, Zhongrui Wang. 1-7 [doi]
• AutoClock: Automated Clock Management for Power-Efficient HLS Designs on FPGAsJiawei Liang, Linfeng Du, Xiaofeng Zhou, Zhe Lin, Jiang Xu, Wei Zhang. 1-7 [doi]
• Query-Based Black-Box Stealthy Sensor Attacks on Cyber-Physical SystemsShixiong Jiang, Weizhe Xu, Mengyu Liu, Fanxin Kong. 1-6 [doi]
• A PulseWidth-IN-PulseWidth-Out Universal Nonlinear Processing Element for Time-Domain In-Memory Computing SystemsYihao Chen, Pengcheng Feng, Zhigang Li, Gang Chen, Rongxuan Shen, Huaxiang Lu, Xiaoxin Xu. 1-6 [doi]
• SSDL-ILT: Efficient ILT utilizing a self-supervised deep learning modelRui Xu, Junqi Yang, Haoxiang Jiang, Ming Fang. 1-6 [doi]
• CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM ArchitecturesYingjie Qi, Jianlei Yang 0001, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao. 1-7 [doi]
• LightRIM: Light Runtime Integrity Measurement for Linux Kernels in Embedded ApplicationsYili Guo, Zhuoran Ma, Xiangyue Li, Jiajia Huang, Wanli Chang 0001. 1-6 [doi]
• IRGNN: A Graph-based Framework Integrating Numerical Solution and Point Cloud for Static IR Drop PredictionFeng Guo, Yueyue Xi, Jianwang Zhai, Jingyu Jia, Jiawei Liu 0006, Kang Zhao, Chuan Shi 0001. 1-7 [doi]
• DIAS: Distance-based Attention Sparsity for Ultra-Long-Sequence Transformer with Tree-like Processing-in-Memory ArchitectureZekai Chen, Yiming Chen, Teng Wan, Tianyi Yu, Yu Wang, Huazhong Yang, Xueqing Li. 1-7 [doi]
• zkVC: Fast Zero-Knowledge Proof for Private and Verifiable ComputingYancheng Zhang, Mengxin Zheng, Xun Chen, Jingtong Hu, Weidong Shi, Lei Ju 0001, Yan Solihin, Qian Lou. 1-7 [doi]
• FlexStep: Enabling Flexible Error Detection in Multi/Many-core Real-time SystemsTinglue Wang, Yiming Li, Wei Tang, Jiapeng Guan, Zhenghui Guo, Renshuang Jiang, Ran Wei, Jing Li 0025, Zhe Jiang 0004. 1-7 [doi]
• Late Breaking Results: On-the-Fly Hadamard Hypervector Processing for Efficient Hyperdimensional ComputingAbu Kaisar Mohammad Masum, Mehran Shoushtari Moghadam, Sabrina Hassan Moon, Ahmed Mamdouh Mohamed Ahmed, M. Hassan Najafi, Dayane Reis, Sercan Aygun. 1-2 [doi]
• Unlocking a New Rust Programming Experience: Fast and Slow Thinking with LLMs to Conquer Undefined BehaviorsRenshuang Jiang, Pan Dong, Zhenling Duan, Yu Shi, Xiaoxiang Fang, Yan Ding, Jun Ma 0015, Shuai Zhao 0004, Zhe Jiang 0004. 1-7 [doi]
• ReSMiPS: A ReRAM-based Sparse Mixed-precision Solver with Fast Matrix Reordering AlgorithmYuyang Fu, Jiancong Li, Jia Chen, Zhiwei Zhou, Houji Zhou, Wenlong Peng, Yi Li 0049, Xiangshui Miao. 1-7 [doi]
• SuperCopyback: Revisiting Copyback on Modern High-Performance NAND Flash-based SSDsDong Huang, Bo Ding, Wei Tong 0001, Dan Feng 0001. 1-7 [doi]
• Generative Model Based Standard Cell Timing Library CharacterizationHao-Yu Wu, Hsin-Tzu Chang, Shiuan-Yun Ding, Iris Hui-Ru Jiang, Benson Tsao, Vinson Wu, Wei-Kai Shih. 1-7 [doi]
• Free and Fair Hardware: A Pathway to Copyright Infringement-Free Verilog Generation using LLMsSam Bush, Matthew DeLorenzo, Phat Tieu, Jeyavijayan Rajendran. 1-7 [doi]
• ChatLS: Multimodal Retrieval-Augmented Generation and Chain-of-Thought for Logic Synthesis Script CustomizationHaisheng Zheng, Haoyuan Wu, Zhuolun He. 1-7 [doi]
• HH-PIM: Dynamic Optimization of Power and Performance with Heterogeneous-Hybrid PIM for Edge AI DevicesSangmin Jeon, Kangju Lee, Kyeongwon Lee, Woojoo Lee. 1-7 [doi]
• HIVE: A High-Priority Victim Cache for Accelerating GPU Memory AccessesYuhan Tang, Jianmin Zhang, Sheng Ma, Tiejun Li, Hanqing Li, Shengbai Luo, Jixuan Tang, Lizhou Wu. 1-7 [doi]
• BLOOM: Bit-Slice Framework for DNN Acceleration with Mixed-PrecisionFangxin Liu, Ning Yang, Zongwu Wang, Xuanpeng Zhu, Haidong Yao, Xiankui Xiong, Li Jiang 0002, Haibing Guan. 1-7 [doi]
• Maximizing Energy Efficiency in Spiking Neural Networks: A Dynamic Joint Pruning FrameworkShuo Chen, Zeshi Liu, Haihang You. 1-7 [doi]
• Logic Optimization Meets SAT: A Novel Framework for Circuit-SAT SolvingZhengyuan Shi, Tiebing Tang, Jiaying Zhu, Sadaf Khan, Hui-Ling Zhen, Mingxuan Yuan, Zhufei Chu, Qiang Xu 0001. 1-7 [doi]
• Mixed-Precision Quantization for Deep Vision Models with Integer Quadratic ProgrammingZihao Deng, Sayeh Sharify, Xin Wang, Michael Orshansky. 1-7 [doi]
• Local-GS: An Order-Independent Gaussian Splatting Training Accelerator Exploiting Splat LocalityYiyang Sun, Qinzhe Zhi, Yiqi Jing, Le Ye, Ru Huang 0001, Tianyu Jia. 1-7 [doi]
• An Enhanced Data Packing Method for General Matrix Multiplication in Brakerski/Fan-Vercauteren SchemeXiangchen Meng, Yan Tan, Zijun Jiang, Yangdi Lyu. 1-7 [doi]
• Graph in the Vault: Protecting Edge GNN Inference with Trusted Execution EnvironmentRuyi Ding, Tianhong Xu, Aidong Adam Ding, Yunsi Fei. 1-7 [doi]
• BoolE: Exact Symbolic Reasoning via Boolean Equality SaturationJiaqi Yin, Zhan Song, Chen Chen, Qihao Hu, Cunxi Yu. 1-7 [doi]
• A Systematic Approach for Multi-objective Double-side Clock Tree SynthesisXun Jiang 0002, Haoran Lu, Yuxuan Zhao 0001, Jiarui Wang, Zizheng Guo, Heng Wu 0007, Bei Yu 0001, Sung Kyu Lim, Runsheng Wang, Ru Huang 0001, Yibo Lin. 1-7 [doi]
• Near-Memory LLM Inference Processor based on 3D DRAM-to-logic Hybrid BondingSangHyeok Han, Byungkuk Yoon, Gyeonghwan Park, Choungki Song, Dongkyun Kim, Jae-Joon Kim. 1-7 [doi]
• Multi-Agent Yield Analysis For Circuit DesignHaiyan Qin, Jing Kou, Liang Zhang, Wang Kang 0001, Wei W. Xing. 1-7 [doi]
• High-Performance Computing Architecture Exploration with Stage-Enhanced Bayesian OptimizationVincent Fu, Mohamed Benazouz, Lilia Zaourar, Alix Munier Kordon. 1-7 [doi]
• ELF: Efficient Logic Synthesis by Pruning Redundancy in RefactoringDimitris Tsaras, Xing Li, Lei Chen, Zhiyao Xie, Mingxuan Yuan. 1-7 [doi]
• Pipirima: Predicting Patterns in Sparsity to Accelerate Matrix AlgebraUbaid Bakhtiar, Donghyeon Joo, Bahar Asgari. 1-7 [doi]
• RADiT: Redundancy-Aware Diffusion Transformer Acceleration Leveraging Timestep SimilarityYoungjun Park, Sangyeon Kim, Yeonggeon Kim, Gisan Ji, Sungju Ryu. 1-7 [doi]
• DAWN: Accelerating Point Cloud Object Detection via Object-Aware Partitioning and 3D Similarity-Based FilteringDongdong Tang, Yu Mao 0001, Weilan Wang, Nan Guan, Tei-Wei Kuo, Chun Jason Xue. 1-7 [doi]
• Scaling Laws of Graph Neural Networks for Atomistic Materials ModelingChaojian Li, Zhifan Ye, Massimiliano Lupo Pasini, Jong Youl Choi, Cheng Wan 0005, Prasanna Balaprakash. 1-7 [doi]
• CMFuzz: Parallel Fuzzing of IoT Protocols by Configuration Model Identification and SchedulingQi Xu, Fuchen Ma, Yuanliang Chen, Wanli Chen, Feifan Wu, Yanyang Zhao, Heyuan Shi, Yu Jiang 0001. 1-7 [doi]
• BirdMoE: Reducing Communication Costs for Mixture-of-Experts Training Using Load-Aware Bi-random QuantizationDonglei Wu, Weihao Yang, Xiangyu Zou, Jinda Jia, Dingwen Tao, Wen Xia, Zhihong Tian. 1-7 [doi]
• KVO-LLM: Boosting Long-Context Generation Throughput for Batched LLM InferenceZhenyu Li, Dongxu Lyu, Gang Wang 0063, Yuzhou Chen, Liyan Chen, Wenjie Li 0003, Jianfei Jiang 0001, Yanan Sun 0003, Guanghui He. 1-7 [doi]
• An Energy-Efficient Kalman Filter Architecture with Tunable Accuracy for Brain-Computer InterfacesGuy Eichler, Joseph Zuckerman, Luca P. Carloni. 1-7 [doi]
• Lookup Table-based Multiplication-free All-digital DNN Accelerator Featuring Self-Synchronous Pipeline AccumulationHiroto Tagata, Takashi Sato 0001, Hiromitsu Awano. 1-7 [doi]
• SSpMV: A Sparsity-aware SpMV Framework Empowered by Multimodal Machine LearningShengle Lin, Chubo Liu, Yan Ding 0004, Joey Tianyi Zhou, Kenli Li 0001, Wangdong Yang. 1-7 [doi]
• April: Accuracy-Improved Floating-Point Approximation For Neural Network AcceleratorsYonghao Chen, Jiaxiang Zou, Xinyu Chen. 1-7 [doi]
• Constraint Graph-based PCB Legalization Considering Dense, Heterogeneous, Irregular-Shaped, and Any-oriented ComponentsChiao-Yu Ou, Yan-Jen Chen, Yao-Wen Chang. 1-7 [doi]
• AttenPIM: Accelerating LLM Attention with Dual-mode GEMV in Processing-in-MemoryLiyan Chen, Dongxu Lyu, Zhenyu Li, Jianfei Jiang 0001, Qin Wang 0009, Zhigang Mao, Naifeng Jing. 1-7 [doi]
• Gem5-AcceSys: Enabling System-Level Exploration of Standard Interconnects for Novel AcceleratorsQunyou Liu, Marina Zapater, David Atienza. 1-7 [doi]
• X-SAT: An Efficient Circuit-Based SAT SolverYuhang Qian, Zhihan Chen, Xindi Zhang, Shaowei Cai 0001. 1-7 [doi]
• ArbiterQ: Improving QNN Convergency and Accuracy by Applying Personalized Model on Heterogeneous Quantum DevicesTianyao Chu, Siwei Tan, Liqiang Lu, Jingwen Leng, Fangxin Liu, Congliang Lang, Yifan Guo, Jianwei Yin. 1-7 [doi]
• Cost-Distance Steiner Trees for Timing-Constrained Global RoutingStephan Held, Edgar Perner. 1-6 [doi]
• WISEDRAM: A Reliable Bitwise In-DRAM AcceleratorMohammad Arman Soleimani, Nezam Rohbani, Adrián Cristal Kestelman, Osman S. Unsal, Hamid Sarbazi-Azad. 1-7 [doi]
• CirSTAG: Circuit Stability Analysis on Graph-based ManifoldsWuxinlin Cheng, Yihang Yuan, Chenhui Deng, Ali Aghdaei, Zhiru Zhang, Zhuo Feng. 1-7 [doi]
• Holistic Design towards Resource-Stringent Binary Vector Symbolic ArchitectureShijin Duan, Nuntipat Narkthong, Yukui Luo, Shaolei Ren, Xiaolin Xu 0001. 1-7 [doi]
• Efficient Edge Vision Transformer Accelerator with Decoupled Chunk Attention and Hybrid Computing-In-MemoryYi Li 0049, Zijian Ye, Xiangqu Fu, Songqi Wang, Shucheng Du, Ning Lin, Dashan Shang, Jinshan Yue, Zhongrui Wang, Xiaojuan Qi 0001, Feng Zhang 0014, Han Wang. 1-7 [doi]
• ReaLM: Reliable and Efficient Large Language Model Inference with Statistical Algorithm-Based Fault ToleranceTong Xie, Jiawang Zhao, Zishen Wan, Zuodong Zhang, Yuan Wang 0001, Runsheng Wang, Ru Huang 0001, Meng Li 0004. 1-7 [doi]
• A Memory-Efficient LLM Accelerator with Q-K Correlation Prediction using Cluster-Based Associative Array for Selective KV AccessingZikang Zhou, Kaiqi Chen, Xuyang Duan, Jun Han 0003. 1-7 [doi]
• LA-MTL: Latency-Aware Automated Multi-Task LearningShambhavi Balamuthu Sampath, Sami Sawani, Moritz Thoma, Lukas Frickenstein, Pierpaolo Morì, Nael Fasfous, Manoj Rohit Vemparala, Alexander Frickenstein, Ulf Schlichtmann, Claudio Passerone, Walter Stechele. 1-7 [doi]
• Few-shot Learning on AMS Circuits and Its Application to Parasitic Capacitance PredictionShan Shen, Yibin Zhang, Hector Rodriguez Rodriguez, Wenjian Yu. 1-7 [doi]
• 3D-TokSIM: Stacking 3D Memory with Token-Stationary Compute-in-Memory for Speculative LLM InferenceWentao Zhao, Boya Lv, Meng Wu 0005, Peiyu Chen, Fengyun Yan, Yufei Ma 0002, Tianyu Jia, Ru Huang 0001, Le Ye. 1-7 [doi]
• P-DAC: Power-Efficient Photonic Accelerators for LLM InferenceWen-Tse Chang, Chun-Feng Wu, Yun-Chen Lo. 1-7 [doi]
• A Novel Image-Graph Heterogeneous Fusion Framework for Static IR Drop PredictionDan Niu, Dekang Zhang, Yichao Cao, Zhou Jin 0001, Chao Wang 0120, Yichao Dong, Changyin Sun 0001. 1-7 [doi]
• Towards Training Robustness Against Dynamic Errors in Quantum Machine LearningShijin Duan, Gaowen Liu, Charles Fleming, Ramana Kompella, Xiaolin Xu 0001, Shaolei Ren. 1-7 [doi]
• DataMaestro: A Versatile and Efficient Data Streaming Engine Bringing Decoupled Memory Access To Dataflow AcceleratorsXiaoling Yi, Yunhao Deng, Ryan Antonio, Fanchen Kong, Guilherme Paim, Marian Verhelst. 1-7 [doi]
• AcclMT: A Highly Resource-Efficient and Flexible Poseidon Hash-Based Merkle Tree ArchitectureChangxu Liu, Hao Zhou 0015, Lan Yang, Yifei Feng, Zheng Wu, Zhuoyuan Yang, Yinlong Li, Shiyong Wu, Fan Yang 0001. 1-7 [doi]
• Hybrid Embedding Framework for Memory-Efficient Recommendation SystemsSeung-Jin Yang, Hyuk-Jae Lee, Chae-Eun Rhee. 1-7 [doi]
• An Energy-Efficient High-Utilization Hardware Architecture for Attention Mechanism in Transformer using Balanced Systolic Array and Multi-Row Interleaved Operation OrderingHaiyang Zhou, Hongyang Hu, Jinshan Yue, Hanghang Gao, Yuanlu Xie, Xiaoxin Xu, Chunmeng Dou, Ming Liu 0022. 1-7 [doi]
• Late Breaking Results: Automated Topology Generation for Power Amplifier Designs through BiLSTM-based DNN and Multi-objective OptimizationsLida Kouhalvandi, Sercan Aygun, M. Hassan Najafi, Arman Roohi. 1-2 [doi]
• E-morphic: Scalable Equality Saturation for Structural Exploration in Logic SynthesisChen Chen, Guangyu Hu, Cunxi Yu, Yuzhe Ma, Hongce Zhang. 1-7 [doi]
• ReChisel: Effective Automatic Chisel Code Generation by LLM with ReflectionJuxin Niu, Xiangfeng Liu, Dan Niu, Xi Wang 0009, Zhe Jiang 0004, Nan Guan. 1-7 [doi]
• Optimizing windowed arithmetic for quantum attacks against RSA-2048Alessandro Luongo, Varun Narasimhachar, Adithya Sireesh. 1-7 [doi]
• Late Breaking Results: A Geometric Diffusion Model for Macro Placement GenerationJongho Yoon, Jinsung Jeon, Seokhyeong Kang. 1-2 [doi]
• From Flatland to Forest: Exploring Pareto-optimal Design through RTL Hierarchy TreesDonger Luo, Qi Sun 0002, Xingheng Li, Cheng Zhuo, Bei Yu 0001, Hao Geng. 1-7 [doi]
• Asymmetric Predictive Testing for Aging in SRAMsYunkun Lin, Mingye Li, Sandeep Gupta. 1-7 [doi]
• Late Breaking Results: Encoder-Decoder Generative Diffusion Transformer Towards Push-Button Analog IC SizingFilipe Azevedo 0001, Nuno Lourenço 0003, Ricardo Martins 0003. 1-2 [doi]
• MIA-aware FinFlex Cell Legalization with Power-Driven Cell Version SubstitutionDa Wei Huang, Shao-Yun Fang. 1-7 [doi]
• MambaOPU: An FPGA Overlay Processor for State-space-duality-based Mamba ModelsShaoqiang Lu, Xuliang Yu, Tiandong Zhao, Siyuan Miao, Xinsong Sheng, Chen Wu, Liang Zhao, Ting-Jung Lin, Lei He 0001. 1-7 [doi]
• An Efficient Compute-in-Memory based Accelerator for Point-based Point Cloud Neural NetworksXipeng Lin, Cong Wang, Shanshi Huang, Hongwu Jiang. 1-7 [doi]
• SuperFast: Fast Supernet Training Using Initial KnowledgeMoritz Thoma, Emad Aghajanzadeh, Shambhavi Balamuthu Sampath, Pierpaolo Morì, Nael Fasfous, Alexander Frickenstein, Manoj Rohit Vemparala, Daniel Mueller-Gritschneder, Ulf Schlichtmann. 1-7 [doi]
• Towards In-Situ Neuromorphic Computing Architecture for Event Stream Super-ResolutionYihe Yu, Bo Li, Kexin Huang, Wei Liu, Jinghai Wang, Yue Liu, Zhiyi Yu, Shanlin Xiao. 1-7 [doi]
• LearnGraph: A Learning-Based Architecture for Dynamic Graph ProcessingLingling Zhang, Yijian Wu, Hong Jiang, Ziyu Zhou, Tiancheng Lu. 1-7 [doi]
• A Novel Covert Timing Channel for Cloud FPGAsBrian Udugama, Darshana Jayasinghe, Hassaan Saadat, Aleksandar Ignjatovic, Sri Parameswaran. 1-7 [doi]
• Harrow: Synthesis of Optical Logic Circuits via Harmonic Mean and Integer PartitionJun-Wei Liang, Iris Hui-Ru Jiang, Kai-Hsiang Chiu. 1-7 [doi]
• AutoPower: Automated Few-Shot Architecture-Level Power Modeling by Power Group DecouplingQijun Zhang, Yao Lu, Mengming Li, Zhiyao Xie. 1-7 [doi]
• Late Breaking Results: Utilization of Hybrid Threshold-Voltage Flip-flops for Power RecoverySehyeon Chung, Hyun-chul Hwang, Byung-Su Kim, Jaeha Lee, Kunhyuk Kang, Taewhan Kim. 1-2 [doi]
• SynGPU: Synergizing CUDA and Bit-Serial Tensor Cores for Vision Transformer Acceleration on GPUYuanzheng Yao, Chen Zhang, Chunyu Qi, Ruiyang Chen, Jun Wang, Zhihui Fu, Naifeng Jing, Xiaoyao Liang, Zhuoran Song. 1-7 [doi]
• Late Breaking Results: Statistical Timing Graph Scheduling Algorithm for GPU ComputationChih-Chun Chang, Tsung-Wei Huang. 1-2 [doi]
• MEEK: Re-thinking Heterogeneous Parallel Error Detection Architecture for Real-World OoO Superscalar ProcessorsZhe Jiang, Minli Liao, Sam Ainsworth 0001, Dean You, Timothy M. Jones 0001. 1-7 [doi]
• ADVeRL-ELF: ADVersarial ELF Malware Generation using Reinforcement LearningAkshara Ravi, Vivek Chaturvedi, Muhammad Shafique 0001. 1-7 [doi]
• Joint Cutting for Hybrid Schrödinger-Feynman Simulation of Quantum CircuitsLaura S. Herzog, Lukas Burgholzer, Christian Ufrecht, Daniel D. Scherer, Robert Wille. 1-7 [doi]
• PatternPaint: Practical Layout Pattern Generation Using Diffusion-Based InpaintingGuanglei Zhou, Bhargav Korrapati, Gaurav Rajavendra Reddy, Chen-Chia Chang, Jingyu Pan, Jiang Hu, Yiran Chen 0001, Dipto G. Thakurta. 1-7 [doi]
• Late Breaking Results: Scalable GPU-Friendly Parallelization for Sweep-Based Maze RoutingCheng-Yu Chiang, Zong-Ying Cai, Chao-Chi Lan, Yan-Jen Chen, Yang Hsu, Yao-Wen Chang, Hung-Ming Chen. 1-2 [doi]
• GLOVA: Global and Local Variation-Aware Analog Circuit Design with Risk-Sensitive Reinforcement LearningDongjun Kim, Junwoo Park, Chaehyeon Shin, Jaeheon Jung, Kyungho Shin, Seungheon Baek, Sanghyuk Heo, Woongrae Kim, In-Chul Jeong, Joohwan Cho, Jongsun Park. 1-7 [doi]
• Chameleon-SAT: An Adaptive Boolean Satisfiability Accelerator Using Mixed-Signal In-Memory Computing for Versatile SAT ProblemsIris Ying Chou, Hao Kong, Yi Huang 0036, Jianfeng Zhu 0001, Wenping Zhu, Shaojun Wei, Aoyang Zhang, Leibo Liu. 1-7 [doi]
• MemSeer: Leverage Memory Failure Distinctions and Multi-Grained Prediction in Ultra-Scale Heterogeneous X86/ARM ClustersYunfei Gu, Yixuan Liu, Xinyuan Wu, Bo Shao, Chentao Wu, Shiyi Li, Jieru Zhao, Jie Li 0002, Minyi Guo, Kunlin Yang, Wengui Zhang, Feilong Lin. 1-7 [doi]
• GS-TG: 3D Gaussian Splatting Accelerator with Tile Grouping for Reducing Redundant Sorting while Preserving Rasterization EfficiencyJoongho Jo, Jongsun Park. 1-7 [doi]
• ReVeil: Unconstrained Concealed Backdoor Attack on Deep Neural Networks using Machine UnlearningManaar Alam, Hithem Lamri, Michail Maniatakos. 1-7 [doi]
• ParGNN: A Scalable Graph Neural Network Training Framework on multi-GPUsJunyu Gu, Shunde Li, Rongqiang Cao, Jue Wang 0013, Zijian Wang, Zhiqiang Liang, Fang Liu, Shigang Li 0002, Chunbao Zhou, Yangang Wang, Xuebin Chi. 1-7 [doi]
• DuQTTA: Dual Quantized Tensor-Train Adaptation with Decoupling Magnitude-Direction for Efficient Fine-Tuning of LLMsHaoyan Dong, Hai-Bao Chen, Jingjing Chang, Yixin Yang 0004, Ziyang Gao, Zhigang Ji, Runsheng Wang, Ru Huang 0001. 1-7 [doi]
• GLiTCH: GLiTCH induced Transitions for Secure Crypto-HardwareC. Rohin Menon, Jayanth Balasubramanian, E. Akshay Kumar, Annapurna Valiveti, Chester Rebeiro, Janakiraman Viraraghavan. 1-7 [doi]
• Late Breaking Results: Versatile 4:1 Multiplexer Using 1T1R RRAM Crossbar for High Speed In-Memory ComputingB. Vinodh Kumar, Binsu J. Kailath. 1-2 [doi]
• DSPlacer: DSP Placement for FPGA-based CNN AcceleratorBaohui Xie, Xinrui Zhu, Zhiyuan Lu, Yuan Pu 0001, Tongkai Wu, Xiaofeng Zou, Bei Yu 0001, Tinghuan Chen. 1-7 [doi]
• DuoQ: A DSP Utilization-aware and Outlier-free Quantization for FPGA-based LLMs AccelerationZhuoquan Yu, Huidong Ji, Yue Cao, Junfu Wu, Xiaoze Yan, Lirong Zheng 0001, Zhuo Zou. 1-7 [doi]
• A Mixed-Signal Photonic SRAM-based High-Speed Energy-Efficient Photonic Tensor Core with Novel Electro-Optic ADCMd. Abdullah-Al Kaiser, Sugeet Sunder, Ajey P. Jacob, Akhilesh R. Jaiswal. 1-7 [doi]
• CND-IDS: Continual Novelty Detection for Intrusion Detection SystemsSean Fuhrman, Onat Güngör, Tajana Rosing. 1-7 [doi]
• Optimizing Recovery Logic in Speculative High-Level SynthesisDylan Leothaud, Jean-Michel Gorius, Simon Rokicki, Steven Derrien. 1-7 [doi]
• EPICS: Efficient Parallel Pattern Fault Simulation for Sequential Circuits via Strongly Connected ComponentsMingjun Wang, Hui Wang 0152, Jianan Mu, Xinyu Zhang, Bin Sun, Yihan Wen, Zizhen Liu, Feng Gu, Jun Gao, Shengwen Liang, Jing Ye 0001, Xiaowei Li 0001, Huawei Li 0001. 1-7 [doi]
• Efficient Rectification Signal Validation for Optimal Functional ECO Patch GenerationTzu-Yu Tung, Yu-Ling Hsu, Shao-Lun Huang, Chung-Yang Ric Huang. 1-6 [doi]
• AASD: Accelerate Inference by Aligning Speculative Decoding in Multimodal Large Language ModelsChaoqun Yang, Ran Chen, Muyang Zhang, Weiguang Pang, Yuzhi Chen, Rongtao Xu, Kexue Fu 0001, Changwei Wang 0001, Longxiang Gao. 1-7 [doi]
• PatLabor: Pareto Optimization of Timing-Driven Routing TreesZhiyang Chen, Hailong Yao, Xia Yin. 1-7 [doi]
• Computational Advantage in Hybrid Quantum Neural Networks: Myth or Reality?Muhammad Kashif, Alberto Marchisio, Muhammad Shafique 0001. 1-7 [doi]
• Late Breaking Results: Hybrid Logic Optimization with Predictive Self-SupervisionRongliang Fu, Ran Zhang, Ziyang Zheng, Zhengyuan Shi, Yuan Pu 0001, Junying Huang, Qiang Xu 0001, Tsung-Yi Ho. 1-2 [doi]
• Towards Uncertainty-aware Robotic Perception via Mixed-signal BNN Engine Leveraging Probabilistic Quantum TunnelingLikai Pei, Yu Zhou, Xingtian Wang, Xueji Zhao, Wanxin Huang, Boyang Cheng, Halid Mulaosmanovic, Stefan Dünkel, Dominik Kleimaier, Sven Beyer, Kai Ni 0004, Mengxue Hou, Michael T. Niemier, Ningyuan Cao. 1-7 [doi]
• AutoRE: Bayesian-Optimization-based Automatic Reliability Enhancement Tool for Flow-based Microfluidic BiochipsSiyuan Liang, Yushen Zhang, Mengchu Li, Tsun-Ming Tseng, Ulf Schlichtmann, Tsung-Yi Ho. 1-7 [doi]
• NN-AdderNet: Nonnegative and Sparse Weight Optimization Towards Ultra-Low Bitwidth AdderNet Quantization and CompressionYunxiang Zhang, Gengchen Sun, Lizhi Fang, Biao Sun, Wenfeng Zhao. 1-7 [doi]
• Multicore Environment State Representation for Agent-Directed Test GenerationBruno D. Miranda, Luiz M. V. Pereira, Márcio Castro, Luiz C. V. dos Santos. 1-7 [doi]
• SSFT: Algorithm and Hardware Co-design for Structured Sparse Fine-Tuning of Large Language ModelsMiao Yu, Trevor E. Carlson. 1-7 [doi]
• New Time-Domain Preconditioners for HB Jacobian of RF CircuitsChenyi Tan, Yangfeng Su, Fan Yang 0001, Xuan Zeng 0001. 1-7 [doi]
• High-throughput Point-Cloud Accelerator with Sparsity-aware Hierarchical Neighbor Voxel Search and SkippingYun-Chia Yu, Suraj Pn Reddy, Aryan Devrani, Anirudh Srinivasan, Saianudeep Reddy Nayini, Sohyeon Kim, Sung-Joon Jang, Sang-Seol Lee, Mingu Kang. 1-7 [doi]
• FT-MUX: A Fault-Tolerant Microfluidic Multiplexer DesignMengchu Li, Jiahui Peng, Tsun-Ming Tseng, Ulf Schlichtmann. 1-7 [doi]
• ZXNet: ZX Calculus-Driven Graph Neural Network Framework for Quantum Circuit Equivalence CheckingNavnil Choudhury, Ameya S. Bhave, Kanad Basu. 1-7 [doi]
• FedEDA: Federated Learning Framework for Privacy-Preserving Machine Learning in EDAJoonseok Kim, Donggyu Kim, SeongHyeon Park, Seokhyeong Kang. 1-7 [doi]
• A Cross-model Fusion-aware Framework for Optimizing (gather-matmul-scatter)s WorkloadYaoxiu Lian, Zhihong Gou, Yibo Han, Zhongming Yu, Jiaming Xu, Sheng Yuan, Zhilin Pei, Xingcheng Zhang, Ningyi Xu, Guohao Dai. 1-7 [doi]
• EPOC: An Efficient Pulse Generation Framework with Advanced Synthesis for Quantum CircuitsJinglei Cheng, Yuchen Zhu, Yidong Zhou, Hang Ren, Zhixin Song, Zhiding Liang. 1-7 [doi]
• Late Breaking Results: Fine-Tuning LLMs for Test Stimuli GenerationHyeonwoo Park, SeongHyeon Park, Seokhyeong Kang. 1-2 [doi]
• VISTA: Optimizing GPU Scheduling through Versatile Locality-Aware Data SharingHajar Falahati, Negin Mahani, Adrián Cristal, Osman S. Unsal. 1-7 [doi]
• Speculative Decoding for Verilog: Speed and Quality, All in OneChangran Xu, Yi Liu 0081, Yunhao Zhou, Shan Huang 0010, Ningyi Xu, Qiang Xu 0001. 1-7 [doi]
• iG-kway: Incremental k-way Graph Partitioning on GPUWan-Luan Lee, Shui Jiang, Dian-Lun Lin, Che Chang, Boyang Zhang, Yi-Hua Chung, Ulf Schlichtmann, Tsung-Yi Ho, Tsung-Wei Huang. 1-7 [doi]
• APSQ: Additive Partial Sum Quantization with Algorithm-Hardware Co-DesignYonghao Tan, Pingcheng Dong, Yongkun Wu, Yu Liu 0007, Xuejiao Liu, Peng Luo, Shih-Yang Liu, Xijie Huang, Dong Zhang, Luhong Liang, Kwang-Ting Cheng. 1-7 [doi]
• Design and Technology Co-optimization Utilizing Flip-FET (FFET) Standard CellsJaehoon Ahn, Taewhan Kim. 1-7 [doi]
• CVMAX: Accelerator Architecture with Polar Form Multiplication for Complex-Valued Neural NetworksHyunwuk Lee, Sungbin Kim, Sungwoo Kim 0003, Won Woo Ro. 1-7 [doi]
• Ensembler: Protect Collaborative Inference Privacy from Model Inversion Attack via Selective EnsembleDancheng Liu, Chenhui Xu, Jiajie Li 0002, Amir Nassereldine, Jinjun Xiong. 1-7 [doi]
• VSpGEMM: Exploiting Versal ACAP for High-Performance SpGEMM AccelerationKai Shi, Zhe Lin 0001, Xinya Luan, Jianwang Zhai, Kang Zhao. 1-7 [doi]
• Introducing Instruction-Accurate Simulators for Performance Estimation of Autotuning WorkloadsRebecca Pelke, Nils Bosbach, Lennart M. Reimann, Rainer Leupers. 1-7 [doi]
• Finding the Pareto Frontier of Low-Precision Data Formats and MAC Architecture for LLM InferenceBrian Crafton, Xiaochen Peng, Xiaoyu Sun 0001, Ashwin Sanjay Lele, Bo Zhang, Win-San Khwa, Kerem Akarvardar. 1-7 [doi]
• PairGraph: An Efficient Search-space-aware Accelerator for High-performance Concurrent Pairwise QueriesYutao Fu, Zhongtian Long, Yu Zhang 0027, Zirui He, Jin Zhao 0003, Qiyuan Niu, Zixiao Wang 0005, Hai Jin 0001. 1-7 [doi]
• McPAL: Scaling Unstructured Sparse Inference with Multi-Chiplet HBM-PIM Architecture for LLMsShiwei Liu 0002, Zhirui Huang, Jiangnan Yu, Qi Liu 0010, Chixiao Chen. 1-7 [doi]
• Routability-aware Packing for High-density Nonvolatile FPGAsHuichuan Zheng, Yuqing Xiong, Jian Zuo, Hao Zhang, Zhenge Jia, Mengying Zhao. 1-7 [doi]
• FineRR-ZNS: Enabling Fine-Granularity Read Refreshing for ZNS SSDsJun Li 0062, Zhibing Sha, Fan Yang 0110, Xiaofei Xu, Xiaobai Chen, Jieming Yin, Jianwei Liao 0001. 1-7 [doi]
• GauRast: Enhancing GPU Triangle Rasterizers to Accelerate 3D Gaussian SplattingSixu Li, Ben Keller, Yingyan Celine Lin, Brucek Khailany. 1-7 [doi]
• Property-driven Parallel Symbolic Model Checking of LTLYuheng Su, Yingcheng Li, Qiusong Yang, Yiwei Ci, Ziyu Huang. 1-7 [doi]
• MetaDSE: A Few-shot Meta-learning Framework for Cross-workload CPU Design Space ExplorationRunzhen Xue, Hao Wu 0070, Mingyu Yan, Ziheng Xiao, Xiaochun Ye, Dongrui Fan. 1-7 [doi]
• Cross-Attention for AES Mode Variation in Side-Channel AnalysisFanliang Hu, Jian Shen 0001, Haoyu Ma, Qingming Jonathan Wu. 1-7 [doi]
• Libra: A Hybrid-Sparse Attention Accelerator Featuring Multi-Level Workload BalanceFaxian Sun, Runzhou Zhang, Zhenyu Liu, Heng Liao, Zhinan Qin, Jianli Chen, Jun Yu, Kun Wang. 1-7 [doi]
• ZenLeak: Practical Last-Level Cache Side-Channel Attacks on AMD Zen ProcessorsHan Wang 0057, Ming Tang 0002, Quancheng Wang, Ke Xu, Yinqian Zhang. 1-7 [doi]
• Synthesis of CFET Cell Library Leveraging Backside Metal RoutingTing Xin Lin, Yih-Lang Li. 1-7 [doi]
• GNN-MLS: Signal Routing in Mixed-Node 3D ICs through GNN-Assisted Metal Layer SharingJiawei Hu, Pruek Vanna-Iampikul, Zhen Zhuang, Tsung-Yi Ho, Sung Kyu Lim. 1-7 [doi]
• CHORD: Composable Hybrid Optical Reconfigurable Diffractive Framework For Optical Neural NetworkZiang Yin, Yu Yao, Jeff Zhang 0001, Jiaqi Gu 0002. 1-7 [doi]
• A Full-system, Programmable, and Extensible In-Memory Computing Simulation Framework for Deep LearningKaining Zhou, Jian Huang 0006, Nam Sung Kim, Naresh Shanbhag. 1-7 [doi]
• NetTAG: A Multimodal RTL-and-Layout-Aligned Netlist Foundation Model via Text-Attributed GraphWenji Fang, Wenkai Li, Shang Liu 0006, Yao Lu, Hongce Zhang, Zhiyao Xie. 1-7 [doi]
• RE3: Finding Refinement Relations with Relational Mapping AbstractionYou Li 0008, Guannan Zhao, Yunqi He, Hai Zhou 0001. 1-7 [doi]
• Construction of DAG Models for Autonomous SystemsJing Huang 0012, Kuan Jiang, Weijie Wang, Wei Liang, Wanli Chang 0001. 1-6 [doi]
• GraphFI: An Efficient Fault Injection Framework for Graph Processing on GPGPUsNan Jiang, Hengshan Yue, Jingweijia Tan, Mengting Zhou, Xiaonan Wang, Yuchun Wang, Wenda Wei, Meikang Qiu, Xiaohui Wei 0002. 1-7 [doi]
• Mixed Structural Choice Operator: Enhancing Technology Mapping with Heterogeneous RepresentationsZhang Hu, Hongyang Pan, Yinshui Xia, Lunyao Wang, Zhufei Chu. 1-7 [doi]
• ZK-Hammer: Leaking Secrets from Zero-Knowledge Proofs via RowhammerJunkai Liang, Xing Zhang 0002, Daqi Hu, Qingni Shen, Yuejian Fang, Zhonghai Wu. 1-7 [doi]
• HoBBy: Hardening Unbalanced Branches against Control Flow Attacks on Intel SGX and AMD SEVChang Liu, Shuaihu Feng, Yuan Li 0061, Dongsheng Wang, Trevor E. Carlson. 1-7 [doi]
• SSDTrain: An Activation Offloading Framework to SSDs for Faster Large Language Model TrainingKun Wu 0002, Jeongmin Brian Park, Xiaofan Zhang 0001, Mert Hidayetoglu, Vikram Sharma Mailthody, Sitao Huang, Steven S. Lumetta, Wen-mei Hwu. 1-7 [doi]
• IntraFuzz: Coverage-Guided Intra-Enclave Fuzzing for Intel SGX ApplicationsJinhua Cui, Qiao Peng, Yiwen Yao, Ke Ye, Jiliang Zhang. 1-7 [doi]
• Contention-Aware Forecasting of Energy Efficiency through Sequence-Based Models in Modern Heterogeneous ProcessorsMohammed Bakr Sikal, Jeferson González-Gómez, Heba Khdr, Jörg Henkel. 1-7 [doi]
• TAXI: Traveling Salesman Problem Accelerator with X-bar-based Ising Macros Powered by SOT-MRAMs and Hierarchical ClusteringSangmin Yoo, Amod Holla, Sourav Sanyal, Dong Eun Kim, Francesca Iacopi, Dwaipayan Biswas, James Myers, Kaushik Roy 0001. 1-7 [doi]
• Grasp: Group-based Prediction of Activation Sparsity for Fast LLM InferenceJiho Shin, Hoeseok Yang, Youngmin Yi. 1-7 [doi]
• Late Breaking Results: Decentralized Voting-Based Attestation for IoT DevicesMohamed Alsharkawy, Eren Sönmez, Jeferson González-Gómez, Hassan Nassar, Jörg Henkel. 1-2 [doi]
• Curvilinear Optical Proximity Correction via Cardinal SplineSu Zheng, Xiaoxiao Liang, Ziyang Yu 0001, Yuzhe Ma, Bei Yu 0001, Martin D. F. Wong. 1-7 [doi]
• BiNeuroRAM: Energy-Efficient ReRAM-Based PIM for Accurate Bipolar Spiking Neural Network AccelerationJun Yan Lee, Chen Nie, Kang You, Yueyang Jia, Rui Yang, Zhezhi He. 1-7 [doi]
• Blaze: An Efficient Bit-Sparse Attention Architecture With Workload Orchestration OptimizationRunzhou Zhang, Faxian Sun, Yiming Wang, Kunchen Zou, Zhinan Qin, Jianli Chen, Jun Yu, Kun Wang. 1-7 [doi]
• Buffer Prospector: Discovering and Exploiting Untapped Buffer Resources in Many-Core DNN AcceleratorsYuchen Wei, Jingwei Cai, Mingyu Gao 0001, Sen Peng, Zuotong Wu, Guiming Shi, Kaisheng Ma. 1-7 [doi]
• On Design Space Exploration of Cache System in Multi-Chiplet SystemsYan Zhang, Xiaohang Wang, Yingtao Jiang, Amit Kumar Singh. 1-7 [doi]
• BEVSA: A Real-Time Bird's-Eye-View Semantic Segmentation Accelerator for Multi-Camera SystemSangho Lee, Jueun Jung, Wuyoung Jang, Jihyeon Hwang, KyuHo Lee. 1-7 [doi]
• Late Breaking Results: BLAST: Bisection-Free Learning Approach for Statistical Timing CharacterizationKai Jing, Tao Bai, Zeyuan Deng, Junming Jiao, Peng Cao 0002. 1-2 [doi]
• DANN: Diffractive Acoustic Neural Network for in-sensor computing system target at multi-biomarker diagnosisLewei He, Ning Lin, Binbin Cui, Xinran Zhang, Shiming Zhang, Zhongrui Wang. 1-7 [doi]
• An Algorithm-Hardware Co-design Based on Revised Microscaling Format Quantization for Accelerating Large Language ModelsYingbo Hao, Huangxu Chen, Yi Zou, Yanfeng Yang. 1-7 [doi]
• Late Breaking Results: FPGen-3D: Automated Framework for 3D-FPGA Architecture Generation and ExplorationIsmael Youssef, Cong Callie Hao. 1-2 [doi]
• 3D-CIMlet: A Chiplet Co-Design Framework for Heterogeneous In-Memory Acceleration of Edge LLM Inference and Continual LearningShuting Du, Luqi Zheng, Aradhana Mohan Parvathy, Feifan Xie, Tiwei Wei, Anand Raghunathan, Haitong Li. 1-7 [doi]
• Efficient and Scalable Architectures for Multi-level Superconducting Qubit ReadoutChaithanya Naik Mude, Satvik Maurya, Benjamin Lienhard, Swamit Tannu. 1-7 [doi]
• Security of Approximate Neural Networks against Power Side-channel AttacksAditya Japa, Jack Miskelly, Máire O'Neill, Chongyan Gu. 1-7 [doi]
• ZION: A Practical Confidential Virtual Machine Architecture on Commodity RISC-V ProcessorsJie Wang 0006, Juan Wang 0006, Yinqian Zhang. 1-7 [doi]
• POLARIS: Explainable Artificial Intelligence for Mitigating Power Side-Channel LeakageTanzim Mahfuz, Sudipta Paria, Tasneem Suha, Swarup Bhunia, Prabuddha Chakraborty. 1-7 [doi]
• MMDFL: Multi-Model-based Decentralized Federated Learning for Resource-Constrained AIoT SystemsDengke Yan, Yanxin Yang, Ming Hu 0003, Xin Fu, Mingsong Chen 0001. 1-7 [doi]
• SAPO: Improving the Scalability and Accuracy of Quantum Linear Solver for Portfolio OptimizationTianze Zhu, Liqiang Lu, Jiajun Chen, Yuhang Chen, Hengrui Chen, Meng Xi, Jinshan Zhang, Xiaoming Sun, Jianwei Yin. 1-7 [doi]
• Invited paper: Enhancing Design Automation with Quantum Algorithms for Chip DesignGabriel P. L. M. Fernandes, Matheus S. Fonseca, Amanda G. Valério, Nicolás A. C. Carpio, João Marcus Epifânio Morais de Assunção, Rafael Vidal Aroca, Celso Jorge Villas-Bôas, Dario Sassi Thober. 1-5 [doi]
• EVA: An Efficient and Versatile Generative Engine for Targeted Discovery of Novel Analog CircuitsJian Gao, Weimin Fu, Xiaolong Guo, Weidong Cao 0001, Xuan Zhang 0001. 1-7 [doi]
• Hypnos: Memory Efficient Homomorphic Processing UnitHaoxuan Wang, Yinghao Yang, Hang Lu, Xiaowei Li. 1-7 [doi]
• PracMHBench: Re-evaluating Model-Heterogeneous Federated Learning Based on Practical Edge Device ConstraintsYuanchun Guo, Bingyan Liu, Yulong Sha, Zhensheng Xian. 1-7 [doi]
• BBAL: A Bidirectional Block Floating Point-Based Quantisation Accelerator for Large Language ModelsXiaomeng Han, Yuan Cheng, Jing Wang, Junyang Lu, Hui Wang, X. X. Zhang, Ning Xu, Dawei Yang, Zhe Jiang 0004. 1-7 [doi]
• 4PUF: A Reliable, Reconfigurable ReRAM-based PUF Resilient to DNN and Side Channel AttacksNing Lin, Yi Li, Yangu He, Songqi Wang, Hegan Chen, Kwunhang Wong, Chuxin Li, Jichang Yang, Yifei Yu, Meng Xu, Yongkang Han, Rui Chen, Xiaoming Chen, Xiaoxin Xu, Jianguo Yang, Dashan Shang, Zhongrui Wang. 1-7 [doi]
• SplitSync: Bank Group-Level Split-Synchronization for High-Performance DRAM PIMByungkuk Yoon, SangHyeok Han, Gyeonghwan Park, Jae-Joon Kim. 1-7 [doi]
• Fast End-to-End Simulation and Exploration of Many-RISCV-Core Baseband Transceivers for Software-Defined Radio-Access NetworksMarco Bertuletti, Yichao Zhang 0003, Mahdi Abdollahpour, Samuel Riedel, Alessandro Vanelli-Coralli, Luca Benini. 1-7 [doi]
• The Unwritten Contract of Cloud-based Elastic Solid-State DrivesYingjia Wang, Ming-Chang Yang. 1-7 [doi]
• Assessing Quantum Layout Synthesis Tools via Known Optimal-SWAP Cost BenchmarksShuohao Ping, Wan-Hsuan Lin, Daniel Bochen Tan, Jason Cong. 1-7 [doi]
• Replay4NCL: An Efficient Memory Replay-based Methodology for Neuromorphic Continual Learning in Embedded AI SystemsMishal Fatima Minhas, Rachmad Vidya Wicaksana Putra, Falah Awwad, Osman Hasan, Muhammad Shafique 0001. 1-7 [doi]
• Quorum: Zero-Training Unsupervised Anomaly Detection using Quantum AutoencodersJason Zev Ludmir, Sophia Rebello, Jacob Ruiz, Tirthak Patel. 1-7 [doi]
• XShift: FPGA-efficient Binarized LLM with Joint Quantization and SparsificationShuai Zhou, Huinan Tian, Sisi Meng, Jianli Chen, Jun Yu 0010, Kun Wang 0005. 1-7 [doi]
• Ares: High Performance Near-Storage Accelerator for FHE-based Private Set IntersectionHaoxuan Wang, Yinghao Yang, Jinkai Zhang, Hang Lu, Xiaowei Li. 1-6 [doi]
• Anchor First, Accelerate Next: Revolutionizing GNNs with PIM by Harnessing Stationary DataJiaxian Chen, Yuxuan Qi, Yongbiao Zhu, Jianan Yuan, Kaoyi Sun, Tianyu Wang 0009, Chenlin Ma, Yi Wang 0003. 1-7 [doi]
• MAGE: A Multi-Agent Engine for Automated RTL Code GenerationYujie Zhao, Hejia Zhang, Hanxian Huang, Zhongming Yu, Jishen Zhao. 1-7 [doi]
• BPUFuzzer: Effective Fuzz Testing for Branching Transient Execution Vulnerabilities of RISC-V CPURihui Sun, Jin Wu, Hanyin Liu, Zikang Tao, Gang Qu 0001, Dong-Sheng Wang 0002, Yongqiang Lyu 0001, Jian Dong 0010. 1-7 [doi]
• MARIO: A Superadditive Multi-Algorithm Interworking Optimization Framework for Analog Circuit SizingWangzhen Li, Yuan Meng, Ruiyu Lyu, Changhao Yan, Keren Zhu 0001, Zhaori Bi, Dian Zhou, Xuan Zeng 0001. 1-7 [doi]
• FPGA-TrustZone: Security Extension of TrustZone to FPGA for SoC-FPGA Heterogeneous ArchitectureShupeng Wang, Xindong Fan, Xiao Xu, Shuchen Wang, Lei Ju, Zimeng Zhou. 1-6 [doi]
• OutlierCIM: Outlier-Aware Digital CIM-Based LLM Accelerator with Hybrid-Strategy Quantization and Unified FP-INT ComputationZihan Zou, Shikuang Chen, Chen Zhang 0001, Xing Wang, Zhichao Liu, Haoran Du, Xin Si, Hao Cai 0001, Bo Liu 0019. 1-7 [doi]
• Hardware Generation with High Flexibility using Reinforcement Learning Enhanced LLMsYifang Zhao, Weimin Fu, Shijie Li 0009, Yi-Xiang Hu, Xiaolong Guo, Yier Jin. 1-7 [doi]
• Clearance-Constrained PCB Global Placement with Heterogeneous ComponentsYan-Jen Chen, Wei-Kai Huang, Chung-Ting Tsai, Chiao-Yu Ou, Yao-Wen Chang. 1-7 [doi]
• LVM-MO: A Large Vision Model Pioneer on Full-Chip Mask OptimizationYiwen Wu, Yuyang Chen, Shuo Yin, Nan Wang, Tao Wu, Xuming He 0001, Hao Geng, Jingyi Yu. 1-7 [doi]
• Late Breaking Results: An Efficient and Scalable Track Assignment with GPU ParallelismGenggeng Liu, Pengcheng Huang, Zepeng Li, Wen-Hao Liu 0001, Xing Huang 0001, Wenzhong Guo. 1-2 [doi]
• LLMs Meet Post-Silicon Test Engineering: A New Era (Invited)Li-C. Wang. 1-5 [doi]
• MILLION: MasterIng Long-Context LLM Inference Via Outlier-Immunized KV Product QuaNtizationZongwu Wang, Peng Xu, Fangxin Liu, Yiwei Hu, Qingxiao Sun, Gezi Li, Cheng Li, Xuan Wang, Li Jiang 0002, Haibing Guan. 1-7 [doi]
• VersaSlot: Efficient Fine-grained FPGA Sharing with Big.Little Slots and Live Migration in FPGA ClusterJianfeng Gu, Hao Wang, Xiaorang Guo, Martin Schulz 0001, Michael Gerndt. 1-7 [doi]
• 333-eDRAM - 3T Embedded DRAM Leveraging Monolithic 3D Integration of 3 Transistor Types: IGZO, Carbon Nanotube and Silicon FETsDavid Kong, Shvetank Prakash, Jedrzej Kufel, Georgios Kyriazidis, Yasmine Omri, David Verity, Emre Ozer, Vijay Janapa Reddi, Gage Hills. 1-7 [doi]
• Can Short Hypervectors Drive Feature-Rich GNNs? Strengthening the Graph Representation of Hyperdimensional Computing for Memory-efficient GNNsJihe Wang, Yuxi Han, Danghui Wang. 1-7 [doi]
• Truly Pre-Routing Timing Prediction via Considering Power Delivery NetworkYuyang Ye 0001, Mingwei He, Lizheng Ren, Jianwang Zhai, Tinghuan Chen, Jun Yang 0006, Longxing Shi. 1-7 [doi]
• KLiNQ: Knowledge Distillation-Assisted Lightweight Neural Network for Qubit Readout on FPGAXiaorang Guo, Tigran Bunarjyan, Dai Liu, Benjamin Lienhard, Martin Schulz 0001. 1-7 [doi]
• Late Breaking Results: Customized Diffusion Model Empowered by Heterogeneous Graph Network for Effective FloorplanningXinglin Zheng, Hao Gu, Keyu Peng, Youwen Wang, Wenxing Zhu, Ziran Zhu. 1-2 [doi]
• Machine Learning-Driven STL Generation for Enhancing Functional Safety of E/E SystemsSanjay Das, Swastik Bhattacharya, Anand Menon, Shamik Kundu, Pooja Madhusoodhanan, Prasanth Viswanathan Pillai, Rubin A. Parekhji, Arnab Raha, Suvadeep Banerjee, Suriyaprakash Natarajan, Kanad Basu. 1-7 [doi]
• H3Match: A Hybrid Heterogeneous Hypergraph Matching Method for Subcircuit IdentificationBoHao Li, Qingsong Peng, Changhong Wang, Tianming Ni, Tinghuan Chen, Qi Sun 0002, Cheng Zhuo. 1-7 [doi]
• HybriMoE: Hybrid CPU-GPU Scheduling and Cache Management for Efficient MoE InferenceShuzhang Zhong, Yanfan Sun, Ling Liang, Runsheng Wang, Ru Huang 0001, Meng Li 0004. 1-7 [doi]
• GEM: GPU-Accelerated Emulator-Inspired RTL SimulationZizheng Guo, Yanqing Zhang 0002, Runsheng Wang, Yibo Lin, Haoxing Ren. 1-7 [doi]
• Reinforcement Learning-Driven Window Selection for Enhanced Window-Based Rip-up and Reroute in Chip Detailed RoutingYu-Chan Keng, Yu-Chun Pai, Wen-Hao Liu 0001, Haoxing Ren, Danny Liu, Rongjian Liang, Mark Ho, Anthony Agnesina, Yih-Lang Li. 1-7 [doi]
• Versatile Cross-platform Compilation Toolchain for Schrödinger-style Quantum Circuit SimulationYuncheng Lu, Shuang Liang 0012, Hongxiang Fan, Ce Guo, Wayne Luk, Paul H. J. Kelly. 1-7 [doi]
• Invited: SambaNova SN40L: Unleashing Agentic AI with DataflowRaghu Prabhakar, Pushkar Nandkar, Darshan Gandhi, Nasim Farahini, Hakan Zeffer. 1-5 [doi]
• Differentiable Net-Moving and Local Congestion Mitigation for Routability-Driven Global PlacementWenchao Li, Hongxi Wu, Duanxiang Liu, Xingquan Li, Wenxing Zhu. 1-7 [doi]
• PIMoE: Towards Efficient MoE Transformer Deployment on NPU-PIM System through Throttle-Aware Task OffloadingLizhou Wu, Haozhe Zhu, Siqi He, Xuanda Lin, Xiaoyang Zeng, Chixiao Chen. 1-7 [doi]
• Me-MPK: Accelerating Krylov Subspace Solvers via Memory-efficient Matrix-Power KernelHaozhong Qiu, Chuanfu Xu, Jianbin Fang, Shengguo Li, Liang Deng, Jian Zhang, Zhe Dai, Yue Ding 0001, Yue Wang, Zhimeng Han, Yonggang Che, Jie Liu 0002. 1-7 [doi]
• Graph-Guided Transfer Learning to Boost the Efficiency of System-Level Optimization of Analog/Mixed-Signal CircuitsJiaqi Wang, Georges G. E. Gielen. 1-7 [doi]
• CIM-BLAS: Computing-in-Memory Accelerator for BLASRui Liu, Zerun Li, Xiaoyu Zhang 0009, Xiaoming Chen 0003, Yinhe Han 0001, Minghua Tang. 1-7 [doi]
• PreDAC: An Efficient Framework of Pre-Refining Enhanced Design Space Exploration for Approximate ComputingZiying Cui, Ke Chen 0018, Bi-Wu, Yu Gong 0002, Chenggang Yan 0002, Weiqiang Liu 0001. 1-7 [doi]
• PacTrain: Pruning and Adaptive Sparse Gradient Compression for Efficient Collective Communication in Distributed Deep LearningYisu Wang, Ruilong Wu, Xinjiao Li, Dirk Kutscher. 1-7 [doi]
• MiniWear: Minimizing Flash Wear via Hybrid Persistent Cache for Extended EF-SMR LifetimeChenlin Ma, Kaoyi Sun, Yuxuan Qi, Jiaxian Chen, Xiaochuan Zheng, Tianyu Wang 0009, Yi Wang 0003. 1-7 [doi]
• A Scalable and Robust Compilation Framework for Emitter-Photonic Graph StateXiangyu Ren, Yuexun Huang, Zhiding Liang, Antonio Barbalace. 1-7 [doi]
• SCONE: A Logic Locking Technique Utilizing SMT Solver and Circuit Encoding Scheme for Efficient Hardware IP ProtectionZhaokun Han, Daniel Xing, Kostas Amberiadis, Ankur Srivastava 0001, Jeyavijayan (JV) Rajendran. 1-7 [doi]
• Dual-Issue Execution of Mixed Integer and Floating-Point Workloads on Energy-Efficient In-Order RISC-V CoresLuca Colagrande, Luca Benini. 1-7 [doi]
• MIRACLE: Multimodal Information Retrieval via a Combined In-Memory Processing and Content Addressable Memory ApproachXuehui Liu, Xueyan Wang, Tianyang Yu, Chen Cheng, Shuo Ran, Bi-Wu, Xiaotao Jia, Weiqiang Liu 0001, Gang Qu 0001, Weisheng Zhao. 1-7 [doi]
• DARIS: An Oversubscribed Spatio-Temporal Scheduler for Real-Time DNN Inference on GPUsAmir Fakhim-Babaei, Thidapat Chantem. 1-7 [doi]
• BlasPart: A Deterministic Parallel Partitioner for Balanced Large-Scale Hypergraph PartitioningShengbo Tong, Chunyan Pei, Wenjian Yu. 1-7 [doi]
• NSFlow: An End-to-End FPGA Framework with Scalable Dataflow Architecture for Neuro-Symbolic AIHanchen Yang, Zishen Wan, Ritik Raj, Joongun Park, Ziwei Li, Ananda Samajdar, Arijit Raychowdhury, Tushar Krishna. 1-7 [doi]
• SeIM: In-Memory Acceleration for Approximate Nearest Neighbor SearchChaoqiang Liu, Dan Chen 0006, Yu Huang 0013, Wenjing Xiao, Haifeng Liu 0003, Yi Zhang 0004, Huize Li, Xiaofei Liao, Hai Jin 0001. 1-7 [doi]
• Live Region Mutation Testing for Commercial Cyber-Physical System Development Tool ChainLehuan Zhang, Shikai Guo, Zixuan Wang, Xiaoyu Wang, Xiaochen Li, He Jiang 0001. 1-7 [doi]
• Invited: EDA for Heterogeneous IntegrationEmad Haque, Pragnya Sudershan Nalla, Chetal Choppali Sudarshan, Divya Yogi, Hangyu Zhang, Chaitali Chakrabarti, Vidya A. Chhabria, Ramesh Harjani, Jeff Zhang 0001, Sachin S. Sapatnekar. 1-4 [doi]
• PASK: Cold Start Mitigation for Inference with Proactive and Selective Kernel Loading on GPUsXuanteng Huang, Jiangsu Du, Nong Xiao 0001, Xianwei Zhang 0001. 1-7 [doi]
• DCO-3D: Differentiable Congestion Optimization in 3D ICsHao-Hsiang Hsiao, Yi-Chen Lu, Pruek Vanna-Iampikul, Anthony Agnesina, Rongjian Liang, Yuan-Hsiang Lu, Haoxing Ren, Sung Kyu Lim. 1-7 [doi]
• An Efficient Bit-level Sparse MAC-accelerated Architecture with SW/HW Co-design on FPGAChenming Zhang, Lei Gong, Chao Wang 0003, Xuehai Zhou. 1-7 [doi]
• Delving into Topology Representation for Layout Pattern: A Novel Contrastive Learning Framework for Hotspot DetectionSilin Chen, Kangjian Di, Guohao Wang, Wenzheng Zhao, Li Du, Ningmu Zou. 1-6 [doi]
• Resilient Federated Learning on Embedded Devices with Constrained Network ConnectivityZihan Li, Han Liu, Ao Li 0006, Ching-Hsiang Chan, Yevgeniy Vorobeychik, William Yeoh 0001, Wenjing Lou, Ning Zhang 0017. 1-7 [doi]
• Hydra: Harnessing Expert Popularity for Efficient Mixture-of-Expert Inference on Chiplet SystemSiqi He, Haozhe Zhu, Jiapei Zheng, Lizhou Wu, Bo Jiao, Qi Liu 0010, Xiaoyang Zeng, Chixiao Chen. 1-7 [doi]
• ChipAlign: Instruction Alignment in Large Language Models for Chip Design via Geodesic InterpolationChenhui Deng, Yunsheng Bai, Haoxing Ren. 1-7 [doi]
• Rewire: Advancing CGRA Mapping Through a Consolidated Routing ParadigmZhaoying Li, Dan Wu, Dhananjaya Wijerathne, Dan Chen 0006, Huize Li, Cheng Tan 0002, Tulika Mitra. 1-7 [doi]
• Dynamic Local Usage: An Accurate Model for Usage of Tile-Internal Wiring in Global RoutingTilmann Bihler, Daniel Blankenburg. 1-6 [doi]
• Automated Generation of Decoders for Irregular Instruction Sets Using Information-Theoretic Decision Tree Construction AlgorithmsLillian Tadros. 1-7 [doi]
• ClusterKV: Manipulating LLM KV Cache in Semantic Space for Recallable CompressionGuangda Liu, Chengwei Li, Jieru Zhao, Chenqi Zhang, Minyi Guo. 1-7 [doi]
• Synergistic Die-Level Router for Multi-FPGA System with Time-Division Multiplexing OptimizationJiarui Wang, Yanjing Liu, Yibo Lin. 1-7 [doi]
• Late Breaking Results: A Diffusion-Based Framework for Configurable and Realistic Multi-Storage Trace GenerationSeohyun Kim, Junyoung Lee, Jongho Park, Jinhyung Koo, Sungjin Lee, Yeseong Kim. 1-2 [doi]
• PARO: Hardware-Software Co-design with Pattern-aware Reorder-based Attention Quantization in Video Generation ModelsXinhao Yang, Tianchen Zhao, Hongyi Wang, Wenheng Ma, Shulin Zeng, Zhenhua Zhu, Xuefei Ning, Huazhong Yang, Yu Wang. 1-7 [doi]
• Location is Key: Leveraging LLM for Functional Bug Localization in Verilog DesignBingkun Yao, Ning Wang 0071, Jie Zhou, Xi Wang 0009, Hong Gao, Zhe Jiang 0004, Nan Guan. 1-7 [doi]
• ARCANE: Adaptive RISC-V Cache Architecture for Near-memory ExtensionsVincenzo Petrolo, Flavia Guella, Michele Caon, Pasquale Davide Schiavone, Guido Masera, Maurizio Martina. 1-6 [doi]
• Late Breaking Results: Less Sense Makes More Sense: In-Sensor Compressive Learning for Efficient Machine VisionYiwen Liang, Weidong Cao. 1-2 [doi]
• A Post-Implementation Performance Prediction Method with HLS Optimization DirectivesJingyu Zhu, Yan Ding 0004, Lu Xiao, Kenli Li 0001, Chubo Liu, Zheng Xiao. 1-6 [doi]
• Logic Restructuring with Preserved Logic BlocksSiang-Yun Lee, Heinz Riener, Sascha Richter, Ankush Sood. 1-6 [doi]
• SDISC: A Spike-Driven Human-Machine Interface with In-Situ Computing for Real-Time Low-Power InteractionFangduo Zhu, Jingyi Chen, Jingsong Zhang, Xumeng Zhang, Siyuan Ouyang, Chenyang, Hao Jiang 0024, Xiaonan Yang, Qi Liu 0010. 1-7 [doi]
• Comparison-Free Bit-Stream Generation for Cost-Efficient Unary ComputingFaeze S. Banitaba, Amir Hossein Jalilvand, M. Hassan Najafi, Sercan Aygun. 1-7 [doi]
• Insights from Rights and Wrongs: A Large Language Model for Solving Assertion Failures in RTL DesignJie Zhou, Youshu Ji, Ning Wang 0071, Yuchen Hu, Xinyao Jiao, Bingkun Yao, Xinwei Fang, Shuai Zhao 0004, Nan Guan, Zhe Jiang 0004. 1-7 [doi]
• TransRoute: A Novel Hierarchical Transistor-Level Routing Framework Beyond Standard-Cell MethodologyChen-Hao Hsu, David Z. Pan, Laurent Perron, Frédéric Didier, Xiaoqing Xu, Hao Chen 0059. 1-7 [doi]
• ABC-FHE: A Resource-Efficient Accelerator Enabling Bootstrappable Parameters for Client-Side Fully Homomorphic EncryptionSungwoong Yune, Hyojeong Lee, Adiwena Putra, Hyunjun Cho, Cuong Duong Manh, JaeHo Jeon, Joo-Young Kim 0001. 1-7 [doi]
• 3D-Flow: Flow-based Standard Cell Legalization for 3D ICsYuxuan Zhao 0001, Peiyu Liao, Bei Yu 0001. 1-7 [doi]
• EdgeMM: Multi-Core CPU with Heterogeneous AI-Extension and Activation-aware Weight Pruning for Multimodal LLMs at EdgeKangbo Bai, Le Ye, Ru Huang 0001, Tianyu Jia. 1-7 [doi]
• INSTA: An Ultra-Fast, Differentiable, Statistical Static Timing Analysis Engine for Industrial Physical Design ApplicationsYi-Chen Lu, Zhizheng Guo, Kishor Kunal, Rongjian Liang, Haoxing Ren. 1-7 [doi]
• EDGE: DBMS-Empowered Boolean Decomposition for GIG SynthesisRuofei Tang, Xuliang Zhu, Xinyi Zhang, Lei Chen 0002, Xing Li, Mingxuan Yuan, Jianliang Xu. 1-7 [doi]
• Late Breaking Results: Opera: An Open and Efficient Platform for Data-driven Synthesis of Analog CircuitsShikai Wang, Yaolong Hu, Zhiqiang Yi, Taiyun Chi, Weidong Cao 0001. 1-2 [doi]
• SmaRTLy: RTL Optimization with Logic Inferencing and Structural RebuildingChengxi Li, Yang Sun, Lei Chen, Yiwen Wang, Mingxuan Yuan, Evangeline F. Y. Young. 1-7 [doi]
• STREAM: Spatiotemporal Similarity-based Efficient Approximate Median with Tunable GranularityFenfang Li, Huizhang Luo, Weichen Liu, Anthony Theodore Chronopoulos, Kenli Li 0001, Chubo Liu. 1-6 [doi]
• Move Less, Retrieve Fast: A Retrieval-in-Memory Architecture for Language ModelsJiaxian Chen, Yuxuan Qi, Jianan Yuan, Kaoyi Sun, Tianyu Wang 0009, Chenlin Ma, Yi Wang 0003. 1-7 [doi]
• Simulation-based Parallel Sweeping: A New Perspective on Combinational Equivalence CheckingTianji Liu, Evangeline F. Y. Young. 1-7 [doi]
• In-Memory Arithmetic: Enabling Division with Stochastic LogicFarzad Razi, Mehran Shoushtari Moghadam, M. Hassan Najafi, Sercan Aygun, Marc D. Riedel. 1-2 [doi]
• Age-of-Information Minimization for Data Aggregation in Energy-Harvesting IoTsBingkun Yao, Mun Choon Chan, Hong Gao, Zhe Jiang 0004, Nan Guan. 1-7 [doi]
• Tropical: Enhancing SLO Attainment in Disaggregated LLM Serving via SLO-Aware MultiplexingJinming Ma, Jiefei Chen, Xiuhong Li, Jiangfei Duan, Haojie Duanmu, Xingcheng Zhang, Chao Yang 0002, Dahua Lin. 1-7 [doi]
• PUFiM: A Robust and Efficient FeFET-Based Security Solution Merging Physical Unclonable Function with Compute-in-Memory for Edge AITaixin Li, Thomas Kämpfe, Jianfeng Wang, Kai Ni 0004, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li 0002. 1-7 [doi]
• InterConFuzz: A Fuzzing-based Comprehensive NoC Verification FrameworkSamit Shahnawaz Miftah, Hyunmin Kim, Kanad Basu. 1-7 [doi]
• MOSS: Multi-Modal Representation Learning on Sequential CircuitsMingjun Wang, Bin Sun, Jianan Mu, Feng Gu, Boyu Han, Tianmeng Yang, Xinyu Zhang, Silin Liu, Yihan Wen, Hui Wang 0152, Jun Gao, Zhiteng Chao, Husheng Han, Zizhen Liu, Shengwen Liang, Jing Ye 0001, Bei Yu 0001, Xiaowei Li 0001, Huawei Li 0001. 1-7 [doi]
• A Cutting-Edge Parallel Solver for Scalable Power Grid Analysis Using Nested Domain DecompositionJianfei Song, Xiaoyu Yang, Zhou Jin 0001, Cheng Zhuo. 1-7 [doi]
• Segmented Angular Pre-Processing for Accurate and Efficient In-Memory Vector Similarity SearchChi-Tse Huang, Jen-Chieh Wang, Hsiang-Yun Cheng, An-Yeu Andy Wu. 1-7 [doi]
• AARC: Automated Affinity-aware Resource Configuration for Serverless WorkflowsLingxiao Jin, Zinuo Cai, Zebin Chen, Hongyu Zhao, Ruhui Ma. 1-7 [doi]
• High Energy-efficiency and Low latency In-Memory Computing using Analog Accumulator and In-Memory ADC with shared ReferencesJunyi Yang, Shuai Dong, Zhengnan Fu, Hongyang Shang, Arindam Basu. 1-7 [doi]
• FLAG: An FPGA-Based System for Low-Latency GNN Inference Service Using Vector QuantizationYunki Han, Taehwan Kim, Jiwan Kim, Seohye Ha, Lee-Sup Kim. 1-7 [doi]
• NVR: Vector Runahead on NPUs for Sparse Memory AccessHui Wang, Zhengpeng Zhao, Jing Wang, Yushu Du, Yuan Cheng, Bing Guo, He Xiao, Chenhao Ma 0006, Xiaomeng Han, Dean You, Jiapeng Guan, Ran Wei, Dawei Yang, Zhe Jiang 0004. 1-7 [doi]
• All-in-Memory Stochastic Computing using ReRAMJoão Paulo C. de Lima, Mehran Shoushtari Moghadam, Sercan Aygun, Jerónimo Castrillón, M. Hassan Najafi, Asif Ali Khan. 1-7 [doi]
• Precon: A Precision-Convertible Architecture for Accelerating Quantized Deep Learning Models across Various Domains Including LLMsJongwoo Park, Hyeonseong Kim, Jiyun Han, Seungkyu Choi. 1-7 [doi]
• GPS: GNN-Based Two-Stage Pre-Scheduling Loop Mapping Method on CGRAsMingyang Kou, Weiqing Ji, Shouyi Yin, Hailong Yao. 1-7 [doi]
• VQT-CiM: Accelerating Vector Quantization Enhanced Transformer with Ferroelectric Compute-in-MemoryXuchu Huang, Haonan Du, Min Zhou, Zheyu Yan, Cheng Zhuo, Xunzhao Yin. 1-7 [doi]
• ReMaP: Macro Placement by Recursively Prototyping and Periphery-Guided RelocatingYunqi Shi, Xi Lin 0001, Siyuan Xu, Shixiong Kai, Ke Xue 0001, Mingxuan Yuan, Chao Qian 0001, Zhi-Hua Zhou. 1-7 [doi]
• Megabits Down to Kilobits: Memory-Efficient Time-Aware Shaping for TSNXuyan Jiang, Wenwen Fu, Xiangrui Yang, Yingwen Chen, Wenfei Wu, ZhiGang Sun. 1-7 [doi]
• Late Breaking Results: A Fast Nearest Neighbor Search Acceleration for 3D Point CloudJinao Li, Teng Wang, Qianyu Cheng, Zhendong Zheng, Lei Gong, Chao Wang 0003, Xi Li 0003, Xuehai Zhou. 1-2 [doi]
• ACIM-QMM: Efficient Analog Computing-in-Memory Accelerator for QC-MDPC McEliece CryptosystemPingdan Xiao, Zhengmiao Wei, Sichun Du, Wanli Chang, Qinghui Hong. 1-6 [doi]
• BS-PDN-Last: Towards Optimal Power Delivery Network Design With Multifunctional Backside Metal LayersMin-Gyu Park, Amaan Rahman, Sung Kyu Lim. 1-7 [doi]
• DeepPUFSCA: Deep learning for Physical Unclonable Function attack based on Side Channel Analysis supportNgoc Phu Doan, Tuan Dung Pham, Zichi Zhang, Viet Hung Tran, Jack Miskelly, Hans Vandierendonck, Anh Tuan Hoang, Máire O'Neill, Son T. Mai. 1-7 [doi]
• PIMPAL: Accelerating LLM Inference on Edge Devices via In-DRAM Arithmetic LookupYoonho Jang, Hyeongjun Cho, Yesin Ryu, Jungrae Kim, Seokin Hong. 1-7 [doi]
• Generalizable Lithographic Hotspot Detection Using Asynchronous Meta-Learning with Only One ShotCong Jiang, Yujia Wang, Dan Feng, Haoyu Yang, Kang Liu. 1-7 [doi]
• EPIC: Error PredIction and Correction for Power-Efficient Voltage Underscaling Multiply-Accumulate UnitTongjing Wu, Xiaolu Hu, Tong Li, Siting Liu 0001, Hui Wang 0023, Weifeng He, Zhigang Mao, Honglan Jiang. 1-7 [doi]
• PHOENIX: Pauli-Based High-Level Optimization Engine for Instruction Execution on NISQ DevicesZhaohui Yang, Dawei Ding, Chenghong Zhu, Jianxin Chen, Yuan Xie. 1-7 [doi]
• Parallel Dynamic Partitioning for Datapath Combinational Equivalence CheckingShuai Zhou, Weikang Zhang, Xindi Zhang, Zite Jiang, Haihang You, Shaowei Cai 0001. 1-7 [doi]