Abstract is missing.
- RADAR: a 3D-reRAM based DNA alignment accelerator architectureWenqin Huangfu, Shuangchen Li, Xing Hu, Yuan Xie 0001. [doi]
- LCP: a layer clusters paralleling mapping method for accelerating inception and residual networks on FPGAXinhan Lin, Shouyi Yin, Fengbin Tu, Leibo Liu, Xiangyu Li, Shaojun Wei. [doi]
- Locality aware memory assignment and tilingSamuel Rogers, Hamed Tabkhi. [doi]
- Design-for-testability for continuous-flow microfluidic biochipsChunfeng Liu, Bing Li, Tsung-Yi Ho, Krishnendu Chakrabarty, Ulf Schlichtmann. [doi]
- Minimizing write amplification to enhance lifetime of large-page flash-memory storage devicesWei-Lin Wang, Tseng-Yi Chen, Yuan-Hao Chang, Hsin-Wen Wei, Wei Kuan Shih. [doi]
- CMP-PIM: an energy-efficient comparator-based processing-in-memory neural network acceleratorShaahin Angizi, Zhezhi He, Adnan Siraj Rakin, Deliang Fan. [doi]
- Approximate on-the-fly coarse-grained reconfigurable acceleration for general-purpose applicationsMarcelo Brandalero, Luigi Carro, Antonio Carlos Schneider Beck, Muhammad Shafique. [doi]
- An efficient Bayesian yield estimation method for high dimensional and high sigma SRAM circuitsJinyuan Zhai, Changhao Yan, Sheng-Guo Wang, Dian Zhou. [doi]
- Runtime monitoring for safety of intelligent vehiclesKosuke Watanabe, Eunsuk Kang, Chung-Wei Lin, Shinichi Shiraishi. [doi]
- PEP: proactive checkpointing for efficient preemption on GPUsChen Li 0015, Andrew Zigerelli, Jun Yang, Yang Guo. [doi]
- Obstacle-avoiding open-net connector with precise shortest distance estimationGuan-Qi Fang, Yong Zhong, Yi-Hao Cheng, Shao-Yun Fang. [doi]
- Raise your game for split manufacturing: restoring the true functionality through BEOLSatwik Patnaik, Mohammed Ashraf, Johann Knechtel, Ozgur Sinanoglu. [doi]
- GAN-OPC: mask optimization with lithography-guided generative adversarial netsHaoyu Yang, Shuhe Li, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young. [doi]
- Extensive evaluation of programming models and ISAs impact on multicore soft error reliabilityFelipe da Rosa, Vitor V. Bandeira, Ricardo Reis, Luciano Ost. [doi]
- A novel 3D DRAM memory cube architecture for space applicationsAnthony Agnesina, Amanvir Sidana, James Yamaguchi, Christian Krutzik, John Carson, Jean Yang-Scharlotta, Sung Kyu Lim. [doi]
- X-value elimination by scan slice correlation analysisHyunsu Chae, Joon-Sung Yang. [doi]
- A collaborative defense against wear out attacks in non-volatile processorsPatrick Cronin, Chengmo Yang, Yongpan Liu. [doi]
- FMMU: a hardware-accelerated flash map management unit for scalable performance of flash-based SSDsYeong-Jae Woo, Sheayun Lee, Sang Lyul Min. [doi]
- Protecting the supply chain for automotives and IoTsSandip Ray, Wen Chen 0016, Rosario Cammarota. [doi]
- Cache side-channel attacks and time-predictability in high-performance critical real-time systemsDavid Trilla, Carles Hernández, Jaume Abella, Francisco J. Cazorla. [doi]
- Architecture decomposition in system synthesis of heterogeneous many-core systemsValentina Richthammer, Tobias Schwarzer, Stefan Wildermann, Jürgen Teich, Michael Glaß. [doi]
- Exploring the programmability for deep learning processors: from architecture to tensorizationChixiao Chen, Huwan Peng, Xindi Liu, Hongwei Ding, C.-J. Richard Shi. [doi]
- OPERON: optical-electrical power-efficient route synthesis for on-chip signalsDerong Liu, Zheng Zhao, Zheng Wang, Zhoufeng Ying, Ray T. Chen, David Z. Pan. [doi]
- PIMA-logic: a novel processing-in-memory architecture for highly flexible and energy-efficient logic computationShaahin Angizi, Zhezhi He, Deliang Fan. [doi]
- Efficient multi-layer obstacle-avoiding region-to-region rectilinear steiner tree constructionRun-Yi Wang, Chia-Cheng Pai, Jun-Jie Wang, Hsiang-Ting Wen, Yu-Cheng Pai, Yao-Wen Chang, James Chien-Mo Li, Jie-Hong Roland Jiang. [doi]
- COSAT: congestion, obstacle, and slew aware tree construction for multiple power domain designChien Pang Lu, Iris Hui-Ru Jiang. [doi]
- Similarity-aware spectral sparsification by edge filteringZhuo Feng. [doi]
- Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classificationHossein Sayadi, Nisarg Patel, Sai Manoj P. D, Avesta Sasan, Setareh Rafatirad, Houman Homayoun. [doi]
- Enabling union page cache to boost file access performance of NVRAM-based storage deviceShuo-Han Chen, Tseng-Yi Chen, Yuan-Hao Chang, Hsin-Wen Wei, Wei Kuan Shih. [doi]
- DPS: dynamic precision scaling for stochastic computing-based deep neural networksHyeon Uk Sim, Saken Kenzhegulov, Jongeun Lee. [doi]
- Measurement-based cache representativeness on multipath programsSuzana Milutinovic, Jaume Abella, Enrico Mezzetti, Francisco J. Cazorla. [doi]
- Dyhard-DNN: even more DNN acceleration with dynamic hardware reconfigurationMateja Putic, Swagath Venkataramani, Schuyler Eldridge, Alper Buyuktosunoglu, Pradip Bose, Mircea Stan. [doi]
- SARA: self-aware resource allocation for heterogeneous MPSoCsYang Song, Olivier Alavoine, Bill Lin. [doi]
- Developing synthesis flows without human knowledgeCunxi Yu, Houping Xiao, Giovanni De Micheli. [doi]
- WB-trees: a meshed tree representation for FinFET analog layout designsYu-Sheng Lu, Yu-Hsuan Chang, Yao-Wen Chang. [doi]
- Virtualsync: timing optimization by synchronizing logic waves with sequential and combinational components as delay unitsGrace Li Zhang, Bing Li 0005, Masanori Hashimoto, Ulf Schlichtmann. [doi]
- MAXelerator: FPGA accelerator for privacy preserving multiply-accumulate (MAC) on cloud serversSiam U. Hussain, Bita Darvish Rouhani, Mohammad GhasemZadeh, Farinaz Koushanfar. [doi]
- Thundervolt: enabling aggressive voltage underscaling and timing error resilience for energy efficient deep learning acceleratorsJeff Zhang, Kartheek Rangineni, Zahra Ghodsi, Siddharth Garg. [doi]
- Specification-driven automated conformance checking for virtual prototype and post-silicon designsHaifeng Gu, Mingsong Chen, Tongquan Wei, Li Lei, Fei Xie. [doi]
- SNrram: an efficient sparse neural network computation architecture based on resistive random-access memoryPeiqi Wang, Yu Ji, Chi Hong, Yongqiang Lyu, Dongsheng Wang, Yuan Xie. [doi]
- Wear leveling for crossbar resistive memoryWen Wen, Youtao Zhang, Jun Yang. [doi]
- Response-time analysis of DAG tasks supporting heterogeneous computingMaria A. Serrano, Eduardo Quiñones. [doi]
- DSA-friendly detailed routing considering double patterning and DSA template assignmentsHai-Juan Yu, Yao-Wen Chang. [doi]
- Dynamic management of key states for reinforcement learning-assisted garbage collection to reduce long tail latency in SSDWon-Kyung Kang, Sungjoo Yoo. [doi]
- SMApproxlib: library of FPGA-based approximate multipliersSalim Ullah, Sanjeev Sripadraj Murthy, Akash Kumar 0001. [doi]
- A measurement system for capacitive PUF-based security enclosuresJohannes Obermaier, Vincent Immler, Matthias Hiller, Georg Sigl. [doi]
- CASTLE: compression architecture for secure low latency, low energy, high endurance NVMsPoovaiah M. Palangappa, Kartik Mohanram. [doi]
- Area-optimized low-latency approximate multipliers for FPGA-based hardware acceleratorsSalim Ullah, Semeen Rehman, Bharath Srinivas Prabakaran, Florian Kriebel, Muhammad Abdullah Hanif, Muhammad Shafique 0001, Akash Kumar 0001. [doi]
- An efficient timestamp-based monitoring approach to test timing constraints of cyber-physical systemsMohammadreza Mehrabian, Mohammad Khayatian, Ahmed Mousa, Aviral Shrivastava, Ya-Shian Li-Baboud, Patricia Derler, Edward Griffor, Hugo A. Andrade, Marc Weiss, John C. Eidson, Dhananjay M. Anand. [doi]
- SRAM based opportunistic energy efficiency improvement in dual-supply near-threshold processorsYunfei Gu, Dengxue Yan, Vaibhav Verma, Mircea R. Stan, Xuan Zhang. [doi]
- Parallelizing SRAM arrays with customized bit-cell for binary neural networksRui Liu, Xiaochen Peng, Xiaoyu Sun, Win-San Khwa, Xin Si, Jia-Jing Chen, Jia-Fang Li, Meng-Fan Chang, Shimeng Yu. [doi]
- A machine learning framework to identify detailed routing short violations from a placed netlistAysa Fakheri Tabrizi, Nima Karimpour Darav, Shuchang Xu, Logan Rakai, Ismail Bustany, Andrew A. Kennings, Laleh Behjat. [doi]
- Brook auto: high-level certification-friendly programming for GPU-powered automotive systemsMatina Maria Trompouki, Leonidas Kosmidis. [doi]
- Semi-automatic safety analysis and optimizationPeter Munk, Andreas Abele, Eike Thaden, Arne Nordmann, Rakshith Amarnath, Markus Schweizer, Simon Burton. [doi]
- Noise-aware DVFS transition sequence optimization for battery-powered IoT devicesShaoheng Luo, Cheng Zhuo, Houle Gan. [doi]
- Analysis of security of split manufacturing using machine learningBoyu Zhang, Jonathon Crandall Magaña, Azadeh Davoodi. [doi]
- STAFF: online learning with stabilized adaptive forgetting factor and feature selection algorithmUjjwal Gupta, Manoj Babu, Raid Ayoub, Michael Kishinevsky, Francesco Paterna, Ümit Y. Ogras. [doi]
- DrAcc: a DRAM based accelerator for accurate CNN inferenceQuan Deng, Lei Jiang, Youtao Zhang, Minxuan Zhang, Jun Yang. [doi]
- Runtime adjustment of IoT system-on-chips for minimum energy operationMohammad Saber Golanbari, Mehdi Baradaran Tahoori. [doi]
- A security vulnerability analysis of SoCFPGA architecturesSumanta Chaudhuri. [doi]
- Coding approach for low-power 3D interconnectsLennart Bamberg, Robert Schmidt, Alberto García Ortiz. [doi]
- Automated accelerator generation and optimization with composable, parallel and pipeline architectureJason Cong, Peng Wei, Cody Hao Yu, Peng Zhang. [doi]
- FastGC: accelerate garbage collection via an efficient copyback-based data migration in SSDsFei Wu 0005, Jiaona Zhou, Shunzhuo Wang, Yajuan Du, Chengmo Yang, Changsheng Xie. [doi]
- It's hammer time: how to attack (rowhammer-based) DRAM-PUFsShaza Zeitouni, David Gens, Ahmad-Reza Sadeghi. [doi]
- Proactive channel adjustment to improve polar code capability for flash storage devicesKun-Cheng Hsu, Che-Wei Tsao, Yuan-Hao Chang, Tei-Wei Kuo, Yu-Ming Huang. [doi]
- FLOSS: FLOw sensitive scheduling on mobile platformsHaibo Zhang, Prasanna Venkatesh Rengasamy, Nachiappan Chidambaram Nachiappan, Shulin Zhao, Anand Sivasubramaniam, Mahmut T. Kandemir, Chita R. Das. [doi]
- Optimized selection of wireless network topologies and components via efficient pruning of feasible pathsDmitrii Kirov, Pierluigi Nuzzo, Roberto Passerone, Alberto L. Sangiovanni-Vincentelli. [doi]
- A fast and robust failure analysis of memory circuits using adaptive importance sampling methodXiao Shi, Fengyuan Liu, Jun Yang, Lei He. [doi]
- Power-based side-channel instruction-level disassemblerJungmin Park, Xiaolin Xu, Yier Jin, Domenic Forte, Mark Tehranipoor. [doi]
- SpWA: an efficient sparse winograd convolutional neural networks accelerator on FPGAsLiqiang Lu, Yun Liang 0001. [doi]
- Revisiting context-based authentication in IoTMarkus Miettinen, Thien Duc Nguyen, Ahmad-Reza Sadeghi, N. Asokan. [doi]
- Electro-magnetic analysis of GPU-based AES implementationYiwen Gao, Hailong Zhang 0001, Wei Cheng, Yongbin Zhou, Yuchen Cao. [doi]
- Efficient reinforcement learning for automating human decision-making in SoC designShankar Sadasivam, Zhuo Chen, Jinwon Lee, Rajeev Jain. [doi]
- Deepsecure: scalable provably-secure deep learningBita Darvish Rouhani, M. Sadegh Riazi, Farinaz Koushanfar. [doi]
- Sign-magnitude SC: getting 10X accuracy for free in stochastic computing for deep neural networksAidyn Zhakatayev, Sugil Lee, Hyeon Uk Sim, Jongeun Lee. [doi]
- Packet pump: overcoming network bottleneck in on-chip interconnects for GPGPUsXianwei Cheng, Yang Zhao, Hui Zhao, Yuan Xie. [doi]
- Basejump STL: systemverilog needs a standard template library for hardware designMichael Bedford Taylor. [doi]
- Hypernel: a hardware-assisted framework for kernel protection without nested pagingDonghyun Kwon, Kuenwhee Oh, JunMo Park, Seungyong Yang, Yeongpil Cho, Brent ByungHoon Kang, Yunheung Paek. [doi]
- A modular digital VLSI flow for high-productivity SoC designBrucek Khailany, Evgeni Khmer, Rangharajan Venkatesan, Jason Clemons, Joel S. Emer, Matthew Fojtik, Alicia Klinefelter, Michael Pellauer, Nathaniel Ross Pinckney, Yakun Sophia Shao, Shreesha Srinath, Christopher Torng, Sam Likun Xi, Yanqing Zhang, Brian Zimmer. [doi]
- Reducing time and effort in IC implementation: a roadmap of challenges and solutionsAndrew B. Kahng. [doi]
- Data prediction for response flows in packet processing cacheHayato Yamaki, Hiroaki Nishi, Shinobu Miwa, Hiroki Honda. [doi]
- LEMAX: learning-based energy consumption minimization in approximate computing with quality guaranteeVahideh Akhlaghi, Sicun Gao, Rajesh K. Gupta 0001. [doi]
- Cross-layer dependency analysis with timing dependence graphsMischa Möstl, Rolf Ernst. [doi]
- Reducing the overhead of authenticated memory encryption using delta encoding and ECC memorySalessawi Ferede Yitbarek, Todd M. Austin. [doi]
- A general graph based pessimism reduction framework for design optimization of timing closureFulin Peng, Changhao Yan, Chunyang Feng, Jianquan Zheng, Sheng-Guo Wang, Dian Zhou, Xuan Zeng 0001. [doi]
- Columba S: a scalable co-layout design automation tool for microfluidic large-scale integrationTsun-Ming Tseng, Mengchu Li, Daniel Nestor Freitas, Amy Mongersun, Ismail Emre Araci, Tsung-Yi Ho, Ulf Schlichtmann. [doi]
- A machine learning based hard fault recuperation model for approximate hardware acceleratorsFarah Naz Taher, Joseph Callenes-Sloan, Benjamin Carrión Schäfer. [doi]
- Atomlayer: a universal reRAM-based CNN accelerator with atomic layer computationXiming Qiao, Xiong Cao, Huanrui Yang, Linghao Song, Hai Li. [doi]
- PlanarONoC: concurrent placement and routing considering crossing minimization for optical networks-on-chipYu-Kai Chuang, Kuan-Jung Chen, Kun-Lin Lin, Shao-Yun Fang, Bing Li, Ulf Schlichtmann. [doi]
- Loom: exploiting weight and activation precisions to accelerate convolutional neural networksSayeh Sharify, Alberto Delmas Lascorz, Kevin Siu, Patrick Judd, Andreas Moshovos. [doi]
- Compensated-DNN: energy efficient low-precision deep neural networks by compensating quantization errorsShubham Jain, Swagath Venkataramani, Vijayalakshmi Srinivasan, Jungwook Choi, Pierce Chuang, Leland Chang. [doi]
- S2FA: an accelerator automation framework for heterogeneous computing in datacentersCody Hao Yu, Peng Wei, Max Grossman, Peng Zhang, Vivek Sarkar, Jason Cong. [doi]
- Efficient computation of ECO patch functionsAi Quoc Dao, Nian-Ze Lee, Li Cheng Chen, Mark Po-Hung Lin, Jie-Hong R. Jiang, Alan Mishchenko, Robert K. Brayton. [doi]
- HFMV: hybridizing formal methods and machine learning for verification of analog and mixed-signal circuitsHanbin Hu, Qingran Zheng, Ya Wang, Peng Li. [doi]
- Exact algorithms for delay-bounded steiner arborescencesStephan Held, Benjamin Rockel. [doi]
- TM TC27xEnrique Díaz, Enrico Mezzetti, Leonidas Kosmidis, Jaume Abella, Francisco J. Cazorla. [doi]
- Thermal-aware optimizations of reRAM-based neuromorphic computing systemsMajed Valad Beigi, Gokhan Memik. [doi]
- Formal micro-architectural analysis of on-chip ring networksPerry van Wesel, Julien Schmaltz. [doi]
- Reverse engineering convolutional neural networks through side-channel information leaksWeizhe Hua, Zhiru Zhang, G. Edward Suh. [doi]
- SAT based exact synthesis using DAG topology familiesWinston Haaswijk, Alan Mishchenko, Mathias Soeken, Giovanni De Micheli. [doi]
- Subutai: distributed synchronization primitives in NoC interfaces for legacy parallel-applicationsRodrigo Cataldo, Ramon Fernandes, Kevin J. M. Martin, Johanna Sepúlveda, Altamiro Amadeu Susin, César A. M. Marcon, Jean-Philippe Diguet. [doi]
- Automated interpretation and reduction of in-vehicle network traces at a large scaleArtur Mrowca, Thomas Pramsohler, Sebastian Steinhorst, Uwe Baumgarten. [doi]
- Compiler-guided instruction-level clock scheduling for timing speculative processorsYuanbo Fan, Tianyu Jia, Jie Gu, Simone Campanoni, Russ Joseph. [doi]
- Duet: an OLED & GPU co-management scheme for dynamic resolution adaptationHan-Yi Lin, Chia-Chun Hung, Pi-Cheng Hsiu, Tei-Wei Kuo. [doi]
- NNsim: fast performance estimation based on sampled simulation of GPGPU kernels for neural networksJintaek Kang, Kwanghyun Chung, Youngmin Yi, Soonhoi Ha. [doi]
- Achieving defect-free multilevel 3D flash memories with one-shot program designChien-Chung Ho, Yung-Chun Li, Yuan-Hao Chang, Yu-Ming Chang. [doi]
- Multi-objective bayesian optimization for analog/RF circuit synthesisWenlong Lyu, Fan Yang 0001, Changhao Yan, Dian Zhou, Xuan Zeng 0001. [doi]
- Improving runtime performance of deduplication system with host-managed SMR storage drivesChun-Feng Wu, Ming-Chang Yang, Yuan-Hao Chang. [doi]
- RAIN: a tool for reliability assessment of interconnect networks - physics to softwareAli Abbasinasab, Malgorzata Marek-Sadowska. [doi]
- TRIG: hardware accelerator for inference-based applications and experimental demonstration using carbon nanotube FETsGage Hills, Daniel Bankman, Bert Moons, Lita Yang, Jake Hillard, Alex Kahng, Rebecca Park, Marian Verhelst, Boris Murmann, Max M. Shulaker, H.-S. Philip Wong, Subhasish Mitra. [doi]
- Formal security verification of concurrent firmware in SoCs using instruction-level abstraction for hardwareBo-Yuan Huang, Sayak Ray, Aarti Gupta, Jason M. Fung, Sharad Malik. [doi]
- Reasoning about safety of learning-enabled components in autonomous cyber-physical systemsCumhur Erkan Tuncali, James Kapinski, Hisahiro Ito, Jyotirmoy V. Deshmukh. [doi]
- RAMP: resource-aware mapping for CGRAsShail Dave, Mahesh Balasubramanian, Aviral Shrivastava. [doi]
- Long live TIME: improving lifetime for training-in-memory engines by structured gradient sparsificationYi Cai, Yujun Lin, Lixue Xia, Xiaoming Chen, Song Han, Yu Wang 0002, Huazhong Yang. [doi]
- ACME: advanced counter mode encryption for secure non-volatile memoriesShivam Swami, Kartik Mohanram. [doi]
- An architecture-agnostic integer linear programming approach to CGRA mappingS. Alexander Chin, Jason Helge Anderson. [doi]
- An efficient kernel transformation architecture for binary- and ternary-weight neural network inferenceShixuan Zheng, Yonggang Liu, Shouyi Yin, Leibo Liu, Shaojun Wei. [doi]
- Dadu-P: a scalable accelerator for robot motion planning in a dynamic environmentShiqi Lian, Yinhe Han, Xiaoming Chen, Ying Wang, Hang Xiao. [doi]
- Dnestmap: mapping deeply-nested loops on ultra-low power CGRAsManupa Karunaratne, Cheng Tan, Aditi Kulkarni Mohite, Tulika Mitra, Li-Shiuan Peh. [doi]
- BLASYS: approximate logic synthesis using boolean matrix factorizationSoheil Hashemi, Hokchhay Tann, Sherief Reda. [doi]
- Closed yet open DRAM: achieving low latency and high performance in DRAM memory systemsLavanya Subramanian, Kaushik Vaidyanathan, Anant Nori, Sreenivas Subramoney, Tanay Karnik, Hong Wang. [doi]
- Ultralow power acoustic feature-scoring using gaussian I-V transistorsAmit Ranjan Trivedi, Ahish Shylendra. [doi]
- Edge-cloud collaborative processing for intelligent internet of things: a case study on smart surveillanceBurhan Ahmad Mudassar, Jong Hwan Ko, Saibal Mukhopadhyay. [doi]
- QoS-aware stochastic power management for many-coresAnuj Pathania, Heba Khdr, Muhammad Shafique 0001, Tulika Mitra, Jörg Henkel. [doi]
- Efficient batch statistical error estimation for iterative multi-level approximate logic synthesisSanbao Su, Yi Wu, Weikang Qian. [doi]
- Cost-aware patch generation for multi-target function rectification of engineering change ordersHe-Teng Zhang, Jie-Hong R. Jiang. [doi]
- Analog placement with current flow and symmetry constraints using PCP-SPAbhishek Patyal, Po-Cheng Pan, Asha K. A, Hung-Ming Chen, Hao-Yu Chi, Chien-Nan Liu. [doi]
- Content addressable memory based binarized neural network accelerator using time-domain signal processingWoong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park 0001. [doi]
- Cross-layer fault-space pruning for hardware-assisted fault injectionChristian Dietrich 0001, Achim Schmider, Oskar Pusz, Guillermo Payá Vayá, Daniel Lohmann. [doi]
- Canonical computation without canonical representationAlan Mishchenko, Robert K. Brayton, Ana Petkovska, Mathias Soeken, Luca Amarù, Antun Domic. [doi]
- Dynamic vehicle software with AUTOCONTChristine Jakobs, Peter Tröger, Matthias Werner 0001, Philipp Mundhenk, Karsten Schmidt. [doi]
- Active forwarding: eliminate IOMMU address translation for accelerator-rich architecturesHsueh-Chun Fu, Po-Han Wang, Chia-Lin Yang. [doi]
- Mamba: closing the performance gap in productive hardware development frameworksShunning Jiang, Berkin Ilbeyi, Christopher Batten. [doi]
- An ultra-low energy internally analog, externally digital vector-matrix multiplier based on NOR flash memory technologyMohammad Reza Mahmoodi, Dmitri B. Strukov. [doi]
- Bandwidth-efficient deep learningSong Han, William J. Dally. [doi]
- Calibrating process variation at system level with in-situ low-precision transfer learning for analog neural network processorsKaige Jia, Zheyu Liu, Qi Wei, Fei Qiao, Xinjun Liu, Yi Yang, Hua Fan, Huazhong Yang. [doi]
- SOTERIA: exploiting process variations to enhance hardware security with photonic NoC architecturesSai Vineel Reddy Chittamuru, Ishan G. Thakkar, Varun Bhat, Sudeep Pasricha. [doi]
- Towards accurate and high-speed spiking neuromorphic systems with data quantization-aware deep networksFuqiang Liu, Chenchen Liu. [doi]
- Generalized augmented lagrangian and its applications to VLSI global placementZiran Zhu, Jianli Chen, Zheng Peng 0002, Wenxing Zhu, Yao-Wen Chang. [doi]
- Efficient winograd-based convolution kernel implementation on edge devicesAthanasios Xygkis, Lazaros Papadopoulos, David Moloney, Dimitrios Soudris, Sofiane Yous. [doi]
- Extracting data parallelism in non-stencil kernel computing by optimally coloring folded memory conflict graphJuan Escobedo, Mingjie Lin. [doi]
- OFTL: ordering-aware FTL for maximizing performance of the journaling file systemDaekyu Park, Donghyun Kang, Young Ik Eom. [doi]
- Context-aware dataflow adaptation technique for low-power multi-core embedded systemsHyeonseok Jung, Hoeseok Yang. [doi]
- Reconciling remote attestation and safety-critical operation on simple IoT devicesXavier Carpent, Karim Eldefrawy, Norrathep Rattanavipanon, Ahmad-Reza Sadeghi, Gene Tsudik. [doi]
- Employing classification-based algorithms for general-purpose approximate computingGeraldo F. Oliveira, Larissa Rozales Gonçalves, Marcelo Brandalero, Antonio Carlos Schneider Beck, Luigi Carro. [doi]
- TAO: techniques for algorithm-level obfuscation during high-level synthesisChristian Pilato, Francesco Regazzoni, Ramesh Karri, Siddharth Garg. [doi]
- Application level hardware tracing for scaling post-silicon debugDebjit Pal, Abhishek Sharma, Sandip Ray, Flavio M. de Paula, Shobha Vasudevan. [doi]
- STASH: security architecture for smart hybrid memoriesShivam Swami, Joydeep Rakshit, Kartik Mohanram. [doi]
- Soft-FET: phase transition material assisted soft switching field effect transistor for supply voltage droop mitigationSubrahmanya Teja, Jaydeep P. Kulkarni. [doi]
- Ares: a framework for quantifying the resilience of deep neural networksBrandon Reagen, Udit Gupta, Lillian Pentecost, Paul N. Whatmough, Sae Kyu Lee, Niamh Mulholland, David M. Brooks, Gu-Yeon Wei. [doi]
- LAWN: boosting the performance of NVMM file system through reducing write amplificationChundong Wang, Sudipta Chattopadhyay. [doi]
- Aging-constrained performance optimization for multi coresHeba Khdr, Hussam Amrouch, Jörg Henkel. [doi]
- Approximation-aware coordinated power/performance management for heterogeneous multi-coresAnil Kanduri, Antonio Miele, Amir M. Rahmani, Pasi Liljeberg, Cristiana Bolchini, Nikil D. Dutt. [doi]
- Enhancing workload-dependent voltage scaling for energy-efficient ultra-low-power embedded systemsVeni Mohan, Akhilesh Iyer, John Sartori. [doi]
- VRL-DRAM: improving DRAM performance via variable refresh latencyAnup Das, Hasan Hassan, Onur Mutlu. [doi]
- Using imprecise computing for improved non-preemptive real-time schedulingLin Huang, Youmeng Li, Sachin S. Sapatnekar, Jiang Hu. [doi]
- Enabling a new era of brain-inspired computing: energy-efficient spiking neural network with ring topologyKangjun Bai, Jialing Li, Kian Hamedani, Yang Yi 0002. [doi]
- DeepN-JPEG: a deep neural network favorable JPEG-based image compression frameworkZihao Liu, Tao Liu, Wujie Wen, Lei Jiang, Jie Xu, Yanzhi Wang, Gang Quan. [doi]
- Resource-aware partitioned scheduling for heterogeneous multicore real-time systemsJian-Jun Han, Wen Cai, Dakai Zhu 0001. [doi]
- Inducing local timing fault through EM injectionMarjan Ghodrati, Bilgiday Yuce, Surabhi Gujar, Chinmay Deshpande, Leyla Nazhandali, Patrick Schaumont. [doi]
- Accurate processor-level wirelength distribution model for technology pathfinding using a modernized interpretation of rent's ruleDivya Prasad, Saurabh Sinha, Brian Cline, Steve Moore, Azad Naeemi. [doi]
- LEAD: learning-enabled energy-aware dynamic voltage/frequency scaling in NoCsMark Clark, Avinash Kodi, Razvan C. Bunescu, Ahmed Louri. [doi]
- On-chip deep neural network storage with multi-level eNVMMarco Donato, Brandon Reagen, Lillian Pentecost, Udit Gupta, David Brooks, Gu-Yeon Wei. [doi]
- Tamper-resistant pin-constrained digital microfluidic biochipsJack Tang, Mohamed Ibrahim, Krishnendu Chakrabarty, Ramesh Karri. [doi]
- DWE: decrypting learning with errors with errorsSong Bian, Masayuki Hiromoto, Takashi Sato. [doi]
- Routability-driven and fence-aware legalization for mixed-cell-height circuitsHaocheng Li, Wing-Kai Chow, Gengjie Chen, Evangeline F. Y. Young, Bei Yu. [doi]
- Co-design of deep neural nets and neural net accelerators for embedded vision applicationsKiseok Kwon, Alon Amid, Amir Gholami, Bichen Wu, Krste Asanovic, Kurt Keutzer. [doi]
- Side-channel security of superscalar CPUs: evaluating the impact of micro-architectural featuresAlessandro Barenghi, Gerardo Pelosi. [doi]
- PARM: power supply noise aware resource management for NoC based multicore systems in the dark silicon eraVenkata Yaswanth Raparti, Sudeep Pasricha. [doi]
- Hierarchical hyperdimensional computing for energy efficient classificationMohsen Imani, Chenyu Huang, Deqian Kong, Tajana Rosing. [doi]
- CamPUF: physically unclonable function based on CMOS image sensor fixed pattern noiseYounghyun Kim, Yongwoo Lee. [doi]
- GPU obfuscation: attack and defense strategiesAbhishek Chakraborty, Yang Xie, Ankur Srivastava. [doi]
- PULP-HD: accelerating brain-inspired high-dimensional computing on a parallel ultra-low power platformFabio Montagna, Abbas Rahimi, Simone Benatti, Davide Rossi, Luca Benini. [doi]
- IAfinder: identifying potential implicit assumptions to facilitate validation in medical cyber-physical systemZhicheng Fu, Zhao Wang, Chunhui Guo, Zhenyu Zhang, Shangping Ren, Lui Sha. [doi]
- A neuromorphic design using chaotic mott memristor with relaxation oscillationBonan Yan, Xiong Cao, Hai (Helen) Li. [doi]
- ACED: a hardware library for generating DSP systemsAngie Wang, Paul Rigge, Adam M. Izraelevitz, Chick Markley, Jonathan Bachrach, Borivoje Nikolic. [doi]
- Efficient and reliable power delivery in voltage-stacked manycore system with hybrid charge-recycling regulatorsAn Zou, Jingwen Leng, Xin He, Yazhou Zu, Vijay Janapa Reddi, Xuan Zhang. [doi]
- Optimized I/O determinism for emerging NVM-based NVMe SSD in an enterprise systemSeonbong Kim, Joon-Sung Yang. [doi]
- Design and architectural co-optimization of monolithic 3D liquid state machine-based neuromorphic processorBon Woong Ku, Yu Liu, Yingyezhe Jin, Sandeep Kumar Samal, Peng Li, Sung Kyu Lim. [doi]