Kyeongho Lee - researchr alias

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Viewing Publication 1 - 27 from 27

2025

A Design Framework of Heterogeneous Approximate DCIM-Based Accelerator for Energy-Efficient NN ProcessingKyeongho Lee, Hyeyeong Lee, Jongsun Park 0001. tcasI, 72(8):3997-4006, August 2025. [doi]

2024

A 28-nm 50.1-TOPS/W P-8T SRAM Compute-In-Memory Macro Design With BL Charge-Sharing-Based In-SRAM DAC/ADC OperationsKyeongho Lee, Joonhyung Kim, Jongsun Park 0001. jssc, 59(6):1926-1937, June 2024. [doi]

TP-DCIM: Transposable Digital SRAM CIM Architecture for Energy-Efficient and High Throughput Transformer AccelerationJunwoo Park, Kyeongho Lee, Jongsun Park 0001. iccad 2024: [doi]

2023

A 2941-TOPS/W Charge-Domain 10T SRAM Compute-in-Memory for Ternary Neural NetworkSungsoo Cheon, Kyeongho Lee, Jongsun Park 0001. tcasI, 70(5):2085-2097, May 2023. [doi]

Low Area and Low Power Threshold Implementation Design Technique for AES S-BoxJunhyun Song, Kyeongho Lee, Jongsun Park 0001. tcasII, 70(3):1169-1173, March 2023. [doi]

2022

A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input ProcessingJoonhyung Kim, Kyeongho Lee, Jongsun Park 0001. islped 2022: [doi]

Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital ConversionKyeongho Lee, Joonhyung Kim, Jongsun Park 0001. iccad 2022: 143 [doi]

A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain ConversionHyunchul Park, Kyeongho Lee, Jongsun Park. aicas 2022: 455-458 [doi]

2021

A 65-nm 0.6-fJ/Bit/Search Ternary Content Addressable Memory Using an Adaptive Match-Line DischargeKyeongho Lee, Woong Choi, Jongsun Park 0001. jssc, 56(8):2574-2584, 2021. [doi]

A Charge-Sharing based 8T SRAM In-Memory Computing for Edge DNN AccelerationKyeongho Lee, Sungsoo Cheon, Joongho Jo, Woong Choi, Jongsun Park 0001. dac 2021: 739-744 [doi]

2020

Bit Parallel 6T SRAM In-memory Computing with Reconfigurable Bit-PrecisionKyeongho Lee, Jinho Jeong, Sungsoo Cheon, Woong Choi, Jongsun Park 0001. dac 2020: 1-6 [doi]

2019

Low Cost Ternary Content Addressable Memory Based on Early Termination Precharge SchemeKyeongho Lee, Geon Ko, Jongsun Park 0001. iscas 2019: 1-4 [doi]

2018

Low Cost Ternary Content Addressable Memory Using Adaptive Matchline Discharging SchemeWoong Choi, Kyeongho Lee, Jongsun Park 0001. iscas 2018: 1-4 [doi]

Content addressable memory based binarized neural network accelerator using time-domain signal processingWoong Choi, Kwanghyo Jeong, Kyungrak Choi, Kyeongho Lee, Jongsun Park 0001. dac 2018: [doi]

2015

A Preliminary Study on Human Trust Measurements by EEG for Human-Machine InteractionsSuh-Yeon Dong, Bo-kyeong Kim, Kyeongho Lee, Soo-Young Lee. hai 2015: 265-268 [doi]

Implicit Shopping Intention Recognition with Eye Tracking Data and Response TimeDong Gun Lee, Kyeongho Lee, Soo-Young Lee. hai 2015: 295-298 [doi]

2008

Wire-speed application flow generation in hardware platform for multi-gigabit traffic monitoringTaesang Choi, Sangsik Yoon, Dongwon Kang, Sangwan Kim, Joonkyung Lee, Kyeongho Lee. apnoms 2008: 184-191 [doi]

2006

Novel Traffic Measurement Methodology for High Precision Applications Awareness in Multi-gigabit NetworksTaesang Choi, Sangsik Yoon, Dongwon Kang, Sangwan Kim, Joonkyung Lee, Kyeongho Lee. apnoms 2006: 63-72 [doi]

2005

Comparison frequency doubling and charge pump matching techniques for dual-band /spl Delta//spl Sigma/ fractional-N frequency synthesizerHyungki Huh, Yido Koo, Kang-Yoon Lee, Yeonkyeong Ok, Sungho Lee, Daehyun Kwon, JeongWoo Lee, Joonbae Park, Kyeongho Lee, Deog Kyoon Jeong, Wonchan Kim. jssc, 40(11):2228-2236, 2005. [doi]

2003

Full-CMOS 2-GHz WCDMA direct conversion transmitter and receiverKang-Yoon Lee, Seung Wook Lee, Yido Koo, Hyoung-Ki Huh, Hee-Young Nam, Jeong-Woo Lee, Joonbae Park, Kyeongho Lee, Deog Kyoon Jeong, Wonchan Kim. jssc, 38(1):43-53, 2003. [doi]

2002

A fully integrated CMOS frequency synthesizer with charge-averaging charge pump and dual-path loop filter for PCS- and cellular-CDMA wireless systemsYido Koo, Hyungki Huh, Yongsik Cho, JeongWoo Lee, Joonbae Park, Kyeongho Lee, Deog Kyoon Jeong, Wonchan Kim. jssc, 37(5):536-542, 2002. [doi]

2001

A single-chip 2.4-GHz direct-conversion CMOS receiver for wireless local loop using multiphase reduced frequency conversion techniqueKyeongho Lee, Joonbae Park, Jeong-Woo Lee, Seung Wook Lee, Hyungki Huh, Deog Kyoon Jeong, Wonchan Kim. jssc, 36(5):800-809, 2001. [doi]

2000

An all-analog multiphase delay-locked loop using a replica delay line for wide-range operation and low-jitter performanceYongsam Moon, Jongsang Choi, Kyeongho Lee, Deog Kyoon Jeong, Min-Kyu Kim. jssc, 35(3):377-384, 2000. [doi]

1999

A 62.5-250 MHz multi-phase delay-locked loop using a replica delay line with triply controlled delay cellsYongsam Moon, Jongsang Choi, Kyeongho Lee, Deog Kyoon Jeong, Min-Kyu Kim. cicc 1999: 299-302 [doi]

1998

1.04 GBd low EMI digital video interface system using small swing serial link techniqueKyeongho Lee, Yeshik Shin, Sungjoon Kim, Deog Kyoon Jeong, Gyudong Kim, Bruce Kim, Victor Da Costa. jssc, 33(5):816-823, 1998. [doi]

1997

A 960-Mb/s/pin interface for skew-tolerant bus using low jitter PLLSungjoon Kim, Kyeongho Lee, Yongsam Moon, Deog Kyoon Jeong, Yunho Choi, Hyung Kyu Lim. jssc, 32(5):691-700, 1997. [doi]

1995

A CMOS serial link for fully duplexed data communicationKyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog Kyoon Jeong. jssc, 30(4):353-364, April 1995. [doi]

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