Gijung Ahn - researchr alias

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Viewing Publication 1 - 7 from 7

2006

A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time ControlYongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim. isscc 2006: 233-242 [doi]

2004

A quad 0.6-3.2 Gb/s/channel interference-free CMOS transceiver for backplane serial linkYongsam Moon, Young Soo Park, Namhoon Kim, Gijung Ahn, Hyun J. Shin, Deog Kyoon Jeong. jssc, 39(5):795-803, 2004. [doi]

2002

A 5-Gb/s 0.25-/spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuitSang Hyun Lee, Moon Sang Hwang, Youngdon Choi, Sungjoon Kim, Yongsam Moon, Bong-Joon Lee, Deog Kyoon Jeong, Wonchan Kim, Young-June Park, Gijung Ahn. jssc, 37(12):1822-1830, 2002. [doi]

2001

A 0.6-2.5-GBaud CMOS tracked 3 /spl times/ oversampling transceiver with dead-zone phase detection for robust clock/data recoveryYongsam Moon, Deog Kyoon Jeong, Gijung Ahn. jssc, 36(12):1974-1983, 2001. [doi]

2000

A 2-Gbaud 0.7-V swing voltage-mode driver and on-chip terminator for high-speed NRZ data transmissionGijung Ahn, Deog Kyoon Jeong, Gyudong Kim. jssc, 35(6):915-918, 2000. [doi]

1995

A CMOS serial link for fully duplexed data communicationKyeongho Lee, Sungjoon Kim, Gijung Ahn, Deog Kyoon Jeong. jssc, 30(4):353-364, April 1995. [doi]

1994

An experimental high-density DRAM cell with a built-in gain stageWonchan Kim, Joongsik Kih, Gyudong Kim, Sanghun Jung, Gijung Ahn. jssc, 29(8):978-981, August 1994. [doi]

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