Table of Contents

• Where CMOS is going: trendy hype vs. real technologyTze-Chiang Chen. 1-18 [doi]
• ICs for mobile multimedia communicationsHermann Eul. 21-39 [doi]
• Toward Future Computer Entertainment SystemsKen Kutaragi. 40-56 [doi]
• A 24x16 CMOS-Based Chronocoulometric DNA MicroarrayMarcin K. Augustyniak, Christian Paulus, Ralf Brederlow, N. Persike, Gerhard Hartwich, Doris Schmitt-Landsiedel, Roland Thewes. 59-68 [doi]
• Fully Electronic CMOS DNA Detection Array Based on Capacitance Measurement with On-Chip Analog-to-Digital ConversionClaudio Stagni, D. Esposti, Carlotta Guiducci, Christian Paulus, Meinrad Schienle, Marcin K. Augustyniak, Giampaolo Zuccheri, Bruno Samorì, Luca Benini, Bruno Riccò, Roland Thewes. 69-78 [doi]
• A 32-Site 4-Channel Cochlear Electrode ArrayP. T. Bhatti, Sangwoo Lee, K. D. Wise. 79-88 [doi]
• 2, Digitally Programmable Nerve Stimulation Pad Cell with High-Voltage Capability for a Retinal ImplantMaurits Ortmanns, N. Unger, André Rocke, Marcus Gehrke, H. J. Tietdke. 89-98 [doi]
• Minimally Invasive Retinal ProsthesisLuke Theogarajan, J. Wyatt, J. Rizzo, B. Drohan, M. Markova, Shawn K. Kelly, G. Swider, M. Raj, Douglas B. Shire, Marcus D. Gingerich, J. Lowenstein, B. Yomtov. 99-108 [doi]
• A 60µW 60 nV/Hz Readout Front-End for Portable Biopotential Acquisition SystemsRefet Firat Yazicioglu, Patrick Merken, Robert Puers, Chris Van Hoof. 109-118 [doi]
• A 1V 2.3µW Biomedical Signal Acquisition ICHonglei Wu, Yong Ping Xu. 119-128 [doi]
• A 14b 20mW 640MHz CMOS CT ΔΣ ADC with 20MHz Signal Bandwidth and 12b ENOBGerhard Mitteregger, Christian Ebner, S. Mechnig, Thomas Blon, Christophe Holuigue, E. Romani, A. Melodia, V. Melini. 131-140 [doi]
• A 375mW Quadrature Bandpass ΔΣ ADC with 90dB DR and 8.5MHz BW at 44MHzRichard Schreier, Nazmy Abaskharoun, Hajime Shibata, I. Mehr, S. Rose, Donald Paterson. 141-150 [doi]
• An 118dB DR CT IF-to-Baseband ΣΔ Modulator for AM/FM/IBOC Radio ReceiversPaulo G. R. Silva, Lucien J. Breems, Kofi A. A. Makinwa, Raf Roovers, Johan H. Huijsing. 151-160 [doi]
• A 14mW Multi-bit ΔΣ Modulator with 82dB SNR and 86dB DR for ADSL2+Sunwoo Kwon, Franco Maloberti. 161-170 [doi]
• A 5.4mW 2-Channel Time-Interleaved Multi-bit ΔΣ Modulator with 80dB SNR and 85dB DR for ADSLKye-Shin Lee, Sunwoo Kwon, Franco Maloberti. 171-180 [doi]
• A 0.5V 74dB SNDR 25kHz CT ΔΣ Modulator with Return-to-Open DACKong-Pang Pun, S. Chatterjee, P. Kinget. 181-190 [doi]
• A 0.9V ΔΣ Modulator with 80dB SNDR and 83dB DR Using a Single-Phase TechniqueJoão Goes, Bruno Vaz, Rui Monteiro, Nuno Paulino 0002. 191-200 [doi]
• An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for Digital TV ReceiversY. Fujimoto, Yusuke Kanazawa, P. Lore, Michael M. Miyamoto. 201-210 [doi]
• A 10Gb/s 5-Tap-DFE/4-Tap-FFE Transceiver in 90nm CMOSMounir Meghelli, Sergey V. Rylov, John F. Bulzacchelli, W. Rhee, Alexander V. Rylyakov, Herschel A. Ainspan, Benjamin D. Parker, Michael P. Beakes, A. Chung, Troy J. Beukema, Petar K. Pepeljugoski, L. Shan, Young Hoon Kwark, Sudhir M. Gowda, Daniel J. Friedman. 213-222 [doi]
• A Serial-Link Transceiver with Transition EqualizationK.-L. J. Wong, Chih-Kong Ken Yang. 223-232 [doi]
• A Quad 6Gb/s Multi-rate CMOS Transceiver with TX Rise/Fall-Time ControlYongsam Moon, Gijung Ahn, Hoon Choi, Namhoon Kim, Daeyun Shim. 233-242 [doi]
• A 12.5Gb/s Single-Chip Transceiver for UTP Cables in 0.13µm CMOSM. Callicotte, J. Little, H. Takatori, K. Dyer, Chien-Hsin Lee. 243-252 [doi]
• A 100mW 9.6Gb/s Transceiver in 90nm CMOS for Next-Generation Memory InterfacesE. Prete, D. Scheideler, A. Sanders. 253-262 [doi]
• A 20Gb/s Forwarded Clock Transceiver in 90nm CMOS BBryan Casper, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, K. Canagasaby, Joseph T. Kennedy, E. Yeung, Randy Mooney. 263-272 [doi]
• A 20Gb/s Adaptive Equalizer in 0.13µm CMOS TechnologyJ. Lee. 273-282 [doi]
• 00 swingJintae Kim, Hamid Hatamkhani, Chih-Kong Ken Yang. 283-292 [doi]
• A Power-Efficient High-Throughput 32-Thread SPARC ProcessorAna Sonia Leon, Jinuk Luke Shin, K. W. Tam, W. Bryg, Francis Schumacher, P. Kongetira, David Weisner, Allan Strong. 295-304 [doi]
• A 16-Core RISC Microprocessor with Network ExtensionsVishnu Yalala, Derek Brasili, David Carlson, Adam Hughes, Anil Jain, Tim Kiszely, K. Kodandapani, Anand Varadharajan, Thucydides Xanthopoulos. 305-314 [doi]
• A Dual-Core Multi-Threaded Xeon Processor with 16MB L3 CacheStefan Rusu, Simon M. Tam, Harry Muljono, David Ayers, Jonathan Chang. 315-324 [doi]
• A 2.6GHz Dual-Core 64bx86 Microprocessor with DDR2 Memory SupportMichael Golden, Srikanth Arekapudi, G. Dabney, M. Haertel, S. Hale, L. Herlinger, Y. Kim, K. Mcgrath, V. Palisetti, M. Singh. 325-332 [doi]
• A 64B CPU Pair: Dual- and Single-Processor ChipsE. B. Cohen, N. J. Rohrer, P. Sandon, M. Canada, Cédric Lichtenau, M. Ringler, Paul Kartschoke, R. Floyd, J. Heaslip, M. Ross, Thomas Pflueger, R. Hilgendorf, P. McCormick, G. Salem, J. Connor, Stephen F. Geissler, D. Thygesen. 333-342 [doi]
• High-Speed Interconnect for a Multiprocessor Server Using Over 1Tb/s CrossbarJ. Yamada, H. Adachi, Y. Mori, A. Harada, S. Okada, H. Ando. 343-352 [doi]
• A 9GHz 65nm Intel Pentium 4 Processor Integer Execution CoreSapumal B. Wijeratne, Nanda Siddaiah, Sanu Mathew, Mark Anders, Ram Krishnamurthy, Jeremy Anderson, S. Hwang, Matthew Ernest, Mark D. Nardin. 353-365 [doi]
• A 16mA UWB 3-to-5GHz 20Mpulses/s Quadrature Analog Correlation Receiver in 0.18µm CMOSJulien Ryckaert, Mustafa Badaroglu, Vincent De Heyn, Geert Van der Plas, Pierluigi Nuzzo, Andrea Baschirotto, Stefano D'Amico, Claude Desset, H. Suys, Michael Libois, Bart van Poucke, Piet Wambacq, Bert Gyselinckx. 368-377 [doi]
• A CMOS Carrier-less UWB Transceiver for WPAN ApplicationsYuanjin Zheng, Yan Tong, Chyuen-Wei Ang, Yong Ping Xu, Wooi Gan Yeoh, Fujiang Lin, Rajinder Singh. 378-387 [doi]
• Dual-antenna phased-array UWB transceiver in 0.18µm CMOSSteve Lo, Isaac Sever, Ssu-Pin Ma, Peter Jang, Albert Zou, Chris Arnott, Kalyan Ghatak, Adam Schwartz, Lam Huynh, Thai Nguyen. 388-397 [doi]
• A 1.1V 3.1-to-9.5GHz MB-OFDM UWB transceiver in 90nm CMOSA. Tanaka, H. Okada, H. Kodama, H. Ishikawa. 398-407 [doi]
• A WiMedia/MBOA-Compliant CMOS RF Transceiver for UWBChristoph Sandner, S. Derksen, Dieter Draxelmayr, S. Ek, V. Filimon, G. Leach, Stefano Marsili, D. Matveev, Koen L. R. Mertens, F. Michl, H. Paule, Manfred Punzenberger, C. Reindl, Raffaele Salerno, Marc Tiebout, A. Wiesbauer, I. Winter, Z. Zhang. 408-417 [doi]
• A Fully Integrated UWB PHY in 0.13µm CMOSTurgut Aytur, Han-Chang Kang, Ravishankar H. Mahadevappa, M. Altintas, S. Brink, T. Diep, Cheng-Chung Hsu, Feng Shi, Feiran Yang, Chao-Cheng Lee, Ran-Hong Yan, Behzad Razavi. 418-427 [doi]
• A 14-band Frequency Synthesizer for MB-OFDM UWB ApplicationChe-Fu Liang, Shen-Iuan Liu, Yen-horng Chen, Tzu-Yi Yang, Gin-Kou Ma. 428-437 [doi]
• A Sub-1mm2 Dynamically Tuned CMOS MB-OFDM 3-to-8GHz UWB Receiver Front-EndM. Ranjan, L. Larson. 438-445 [doi]
• A 4b/cell NROM 1Gb Data-Storage MemoryY. Polansky, Avi Lavan, Ran Sahar, O. Dadashev, Yoram Betser, G. Cohen, Eduardo Maayan, Boaz Eitan, Ful-Long Ni, Yen-Hui Joseph Ku, Chih-Yuan Lu, Tim Chang-Ting Chen, Chun-Yu Liao, Chin-Hung Chang, Chung Kuang Chen, Wen-Chiao Ho, Yite Shih, Wenchi Ting, Wenpin Lu. 448-458 [doi]
• A 64Mb Chain FeRAM with Quad-BL Architecture and 200MB/s Burst ModeKatsuhiko Hoya, Daisaburo Takashima, Shinichiro Shiratake, Ryu Ogiwara, Tadashi Miyakawa, Hidehiro Shiga, S. M. Doumae, S. Ohtsuki, Yoshinori Kumura, Susumu Shuto, Tohru Ozaki, Koji Yamakawa, Iwao Kunishima, Akihiro Nitayama, Shuso Fujii. 459-466 [doi]
• Signal-Margin-Screening for Multi-Mb MRAMHeinz Hoenigschmid, P. Beer, A. Bette, R. Dittrich, R. Gardic, Dietmar Gogl, S. Lammers, J. Schmid, Laith Altimime, Serge Bournat, Gerhard Müller. 467-476 [doi]
• A 16Mb MRAM with FORK Wiring Scheme and Burst ModesYoshihisa Iwata, Kenji Tsuchida, Tsuneo Inaba, Yui Shimizu, R. Takizawa, Yoshihiro Ueda, Tadahiko Sugibayashi, Yoshiaki Asao, Takeshi Kajiyama, Keiji Hosotani, Sumio Ikegawa, Tadashi Kai, M. Nakayama, Shuichi Tahara, Hiroaki Yoda. 477-486 [doi]
• A 0.1µm 1.8V 256Mb 66MHz Synchronous Burst PRAMSangbeom Kang, Woo-Yeong Cho, Beak-Hyung Cho, KwangJin Lee, Changsoo Lee, Hyung-Rok Oh, Byung Gil Choi, Qi Wang, Hye-Jin Kim, Mu-Hui Park, Yu-Hwan Ro, Suyeon Kim, Du-Eung Kim, Kang-Sik Cho, Choong-Duk Ha, Young-Ran Kim, Ki-Sung Kim, Choong-Ryeol Hwang, Choong-Keun Kwak, Hyun-Geun Byun, YunSueng Shin. 487-496 [doi]
• A 4Gb 2b/cell NAND Flash Memory with Embedded 5b BCH ECC for 36MB/s System Read ThroughputRino Micheloni, R. Ravasio, Alessia Marelli, E. Alice, V. Altieri, A. Bovino, Luca Crippa, E. Di Martino, L. D'Onofrio, A. Gambardella, E. Grillea, G. Guerra, D. Kim, C. Missiroli, I. Motta, A. Prisco, G. Ragone, M. Romano, M. Sangalli, P. Sauro, M. Scotti, S. Won. 497-506 [doi]
• A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program ThroughputKen Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Y. Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima. 507-516 [doi]
• An 8Gb/s/pin 9.6ns Row-Cycle 288Mb Deca-Data Rate SDRAM with an I/O Error-Detection SchemeKyu-hyoun Kim, Uksong Kang, Hoeju Chung, Dukha Park, Woo-Seop Kim, Young-Chan Jang, Moon-Sook Park, Hoon Lee, Jinyoung Kim, Jung Sunwoo, Hwan-Wook Park, Hyun-Kyung Kim, Su-Jin Chung, Jaekwan Kim, Hyung-Seuk Kim, Kee-Won Kwon, Young-Taek Lee, Joo-Sun Choi, Changhyun Kim. 527-536 [doi]
• A 2Gb/s/pin 512Mb Graphics DRAM with NoiseReduction TechniquesMartin Brox, H. Fibranz, Maksim Kuzmenka, F. Lu, S. Mann, M. Markert, U. Mbller, Manfred Plan, Kai Schiller, P. Schmblz, P. Schrbgmeier, A. Tauber, Bradley Weber, P. Mayer, Wolfgang Spirkl, Holger Steffens, Jörg Weller. 537-546 [doi]
• A 2.5Gb/s/pin 256Mb GDDR3 SDRAM with Series Pipelined CAS Latency Control and Dual-Loop Digital DLLDong Uk Lee, Hyun-Woo Lee, Ki Chang Kwean, Young-Kyoung Choi, Hyong Uk Moon, Seung-Wook Kwack, Shin-Deok Kang, Kwan-Weon Kim, Yong-Ju Kim, Young-Jung Choi, Patrick B. Moran, Jin-Hong Ahn, Joong Sik Kih. 547-556 [doi]
• An 8.4ns Column-Access 1.3Gb/s/pin DDR3 SDRAM with an 8: 4 Multiplexed Data-Transfer SchemeHiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura. 557-566 [doi]
• A 65nm low-power embedded DRAM with extended data-retention sleep modeTakeshi Nagai, Masaharu Wada, Hitoshi Iwai, Mariko Kaku, Atsushi Suzuki, Tomohisa Takai, Naoko Itoga, Takayuki Miyazaki, Hiroyuki Takenaka, Takehiko Hojo, Shinji Miyano. 567-576 [doi]
• TCAM for IP-Address Lookup Using Tree-style AND-type Match Lines and Segmented Search LinesJinn-Shyan Wang, Chao-Ching Wang, Chingwei Yeh. 577-586 [doi]
• A Storage- and Power-Efficient Range-Matching TCAM for Packet ClassificationYoung-Deok Kim, Hyun-Seok Ahn, Joon Young Park, Suhwan Kim, Deog Kyoon Jeong. 587-596 [doi]
• A 250µW 0.042mm2 2MS/s 9b DAC for Liquid Crystal Display DriversImre Knausz, Robert J. Bowman. 599-608 [doi]
• A Current Driver IC using a S/H for QVGA FullColor Active-Matrix Organic LED Mobile DisplaysJong-Hak Baek, Jaehoon Lee, Han Su Pae, Chang-ju Lee, JongSeon Kim, Myunghee Lee, Jintae Kim, Changsik Choi, Hong Kwon Kim, Tae-Jin Kim, Ho Kyoon Chung. 609-618 [doi]
• Panel-Sized TFT-LCD Column DriverO. Ishibashi, M. Iriguchi, K. Kimura, J. Ishii, D. Sasaki, H. Imai, H. Tsuchi, H. Hayama. 619-626 [doi]
• A 77GHz 4-Element Phased Array Receiver with On-Chip Dipole Antennas in SiliconAydin Babakhani, Xiang Guan, Abbas Komijani, Arun Natarajan, Ali Hajimiri. 629-638 [doi]
• A 77GHz Phased-Array Transmitter with Local LO-Path Phase-Shifting in SiliconArun Natarajan, Abbas Komijani, Xiang Guan, Aydin Babakhani, Y. Wang, Ali Hajimiri. 639-648 [doi]
• A silicon 60GHz receiver and transmitter chipset for broadband communicationsBrian A. Floyd, Scott K. Reynolds, Ullrich R. Pfeiffer, Troy J. Beukema, Janus Grzyb, Chuck Haymes. 649-658 [doi]
• A 60GHz transmitter with integrated antenna in 0.18µm SiGe BiCMOS technologyChi-Hsueh Wang, Yi-Hsien Cho, Chin-Shen Lin, Huei Wang, Chun-Hsiung Chen, Dow-Chih Niu, J. Yeh, Chwan-Ying Lee, J. Chern. 659-668 [doi]
• A 10b 10GHz digitlly controlled LC oscillator in 65nm CMOSN. Da Dalt, Claus Kropf, M. Burian, Thomas Hartig, H. Eul. 669-678 [doi]
• An 18mW 90 to 770MHz synthesizer with agile auto-tuning for digital TV-tunersM. Marutani, H. Anbutsu, M. Kondo, N. Shirai, H. Yamazaki, Y. Watanabe. 681-690 [doi]
• A 2.3GHz LC-tank CMOS VCO with optimal phase noise performanceP. Andreani, A. Fard. 691-700 [doi]
• A phase-noise reduction technique for quadrature LC-VCO with phase-to-amplitude noise conversionChih-Wei Yao, Alan N. Willson Jr.. 701-710 [doi]
• A 1V 17GHz 5mW Quandrature CMOS VCO based on transformer couplingAlan W. L. Ng, Howard Cam Luong. 711-720 [doi]
• A 5GHz resistive-feedback CMOS LNA for low-cost multi-standard applicationsJ.-H. C. Zhan, S. S. Taylor. 721-730 [doi]
• A 3 to 5GHz CMOS UWB LNA with input matching using miller effectH. J. Lee, D. S. Ha, S. S. Choi. 731-740 [doi]
• A fast-settling PLL frequency synthesizer with direct frequency presettingXiaofei Kuang, Nanjian Wu. 741-750 [doi]
• Electrical funnel: A broadband signal combining methodEhsan Afshari, Harish S. Bhat, Xiaofeng Li, Ali Hajimiri. 751-760 [doi]
• A single-chip linear CMOS power amplifier for 2.4 GHz WLANJongchan Kang, Ali Hajimiri, Bumman Kim. 761-769 [doi]
• A UMTS-complaint fully digitally controlled oscillator with 100Mhz fine-tuning range in 0.13µm CMOST. Pittorino, Y. Chen, V. Neubauer, Thomas Mayer, Linus Maurer. 770-779 [doi]
• A 90nm CMOS 1.2V 10b power and speed programmable pipelined ADC with 0.5pJ/conversion-stepGovert Geelen, Edward J. F. Paulus, D. Simanjuntak, H. Pastoor, R. Verlinden. 782-791 [doi]
• A 10b 50MS/s pipelined ADC with opamp current reuseSeung-Tak Ryu, Bang-Sup Song, Kantilal Bacrania. 792-801 [doi]
• A 30mW 12b 40MS/s subranging ADC with a high-gain offset-canceling positive-feedback amplifier in 90nm digital CMOSYasuhide Shimizu, Shigemitsu Murayama, Kohei Kudoh, Hiroaki Yatsuda, A. Ogawa. 802-811 [doi]
• Comparator-based switched-capacitor circuits for scaled CMOS technologiesTodd Sepke, J. K. Fiorenza, Charles G. Sodini, Peter Holloway, Hae-Seung Lee. 812-821 [doi]
• A 25µW 100kS/s 12b ADC for wireless micro-sensor applicationsN. Verma, A. P. Chandrakasan. 822-831 [doi]
• A 14b 100MS/s digitally self-calibrated pipelined ADC in 0.13µm CMOSPeter Bogner, Franz Kuttner, Claus Kropf, Thomas Hartig, M. Burian, H. Eul. 832-841 [doi]
• 2 50MS/s ADC with wide input rangeHee-Cheol Choi, Ju-Wha Kim, Sang-Min Yoo, Kang-Jin Lee, Tae-Hwan Oh, Mi-Jung Seo, Jae-Whui Kim. 842-851 [doi]
• A 13b linear 40MS/s pipelined ADC with self-configured capacitor matchingSourja Ray, Bang-Sup Song. 852-861 [doi]
• A 9.95 to 11.1Gb/s XFP transceiver in 0.13µm CMOSJack Kenney, Declan Dalton, M. Eskiyerli, E. Evans, B. Hilton, D. Hitchcox, T. Kwok, D. Mulcahy, C. McQuilkin, V. Reddy, S. Selvanayagam, P. Shepherd, Ward S. Titus, Larry DeVito. 864-873 [doi]
• An MLSE receiver for electronic-dispersion compensation of OC-192 fiber linksHyeon-Min Bae, Jonathan B. Ashbrook, J. Park, Naresh R. Shanbhag, Andrew C. Singer, S. Chopra. 874-883 [doi]
• A monolithic low-bandwidth jitter-cleaning PLL with hitless switching for SONET/SDH clock generationD. C. Wei, Y. Huang, B. W. Garlepp, J. Hein. 884-893 [doi]
• A 24mW 1.25Gb/s 13kΧ transimpedance amplifier using active compensationChia-Ming Tsai, Li-Ren Huang. 894-903 [doi]
• 11Gb/s monolithically integrated silicon optical receiver for 850nm wavelengthR. Swoboda, H. Zimmermann. 904-911 [doi]
• A 10Gb/s burst-mode/continuous-mode laser driver with current-mode extinction-ratio compensation circuitDay-Uei Li, Chia-Ming Tsai. 912-921 [doi]
• A 10Gb/s photonic modulator and WDM MUX/DEMUX integrated with electronics in 0.13µm SOI CMOSA. Huang, Cary Gunn, Guo-liang Li, Yi Liang, Sina Mirsaidi, Adithyaram Narasimha, Thierry Pinguet. 922-929 [doi]
• An integrated VCSEL driver for 10Gb ethernet in 0.13µm CMOSS. Rabii, N. Acharya, P. Chau, J. Dao, A. Feldman, H.-J. Liaw, D. Liu, M. Loinaz, M. Luschas, A. Salleh, S. Sheth, S. Sidiropoulos, D. Stark, S. Verma. 930-939 [doi]
• A 10Gb/s burst-mode adaptive gain select limiting amplifier in 0.13µm CMOSMasafumi Nogawa, Yusuke Ohtomo, Shunji Kimura, Kazuyoshi Nishimura, Tomoaki Kawamura, Minoru Togashi. 940-949 [doi]
• A 90nm CMOS low-power GSM/EDGE multimedia-enhanced baseband processor with 380MHz ARM9 and mixed-signal extensionsThomas Lüftner, Jörg Berthold, Christian Pacha, Georg Georgakos, Guillaume Sauzon, Olaf Hoemke, Jurij Beshenar, Peter Mahrla, Knut M. Just, Peter Hober, Stephan Henzler, Doris Schmitt-Landsiedel, Andre Yakovleff, Axel Klein, Richard J. Knight, Pramod Acharya, H. Mabrouki, G. Juhoor, M. Sauer. 952-961 [doi]
• All digital spread spectrum clock generator for EMI reductionSimon Damphousse, Khalid Ouici, Ahmed Rizki, Martin Mallinson. 962-971 [doi]
• A 630MHz direct digital frequency synthesizer with 90dBc SFDR in 0.25µm CMOSD. De Cam, Nicola Petra, Antonio G. M. Strollo. 972-981 [doi]
• A 380MHz, 150mW direct digital synthesizer/mixer in 0.25µm CMOSD. De Cam, Nicola Petra, Antonio G. M. Strollo. 982-991 [doi]
• A DSSS UWB digital PHY/MAC transceiver for wireless ad hoc mesh networks with distributed controlA. Koyama, H. Iwami, Y. Mizoguchi, S. Tashiro, F. Nishiyama, T. Yamagata, Y. Hashimoto, M. Takada, K. Watanabe, J. Iwasaki, M. Suzuki. 992-1001 [doi]
• A 1.8V 250mW COFDM baseband receiver for DVB-T/H applicationsLei-Fone Chen, Yuan Chen, Lu-Chung Chien, Ying-Hao Ma, Chia-Hao Lee, Yu-Wei Lin, Chien-Ching Lin, Hsuan-Yu Liu, Terng-Yin Hsu, Chen-Yi Lee. 1002-1011 [doi]
• A 0.13µm CMOS SoC for all format blue and red laser DVD front-end digital signal processorM. Bathaee, H. Ghezelayagh, Wang Qin Heng, D. Nicolae, O. Fratu, R. Pop, G. Dilimot, V. Feies, P. Agache, R. Ruscu, M. lorgulescu, Jing-gang, Wei Mao Lin, Ma Lei, Dong Zhao Hui, Wang Tao. 1012-1021 [doi]
• Fully Integrated CMOS SoC for 56/18/16 CD/DVD-dual/RAM Applications with On-Chip 4-LVDS Channel WSG and 1.5Gb/s SATA PHYJyh-Shin Pan, Tse-Hsiang Hsu, Hao-Cheng Chen, Jong-Woei Chen, Bing-Yu Hsieh, Hong-Ching Chen, Wei-Hsuan Tu, Chi-Ming Chang, Roger Lee, Ching-Ho Chu, Yuan-Chin Liu, Chuan-Cheng Hsiao, Chuan Liu, Lily Huang, Chia-Hua Chou, Chang-Long Wu, Meng-Hsueh Lin, Shang-Ping Chen, B. Liu, Heng-Shou Hsu, Chun-Yiu Lin, Shang-Nien Tsai, Jenn-Ning Yang, S. Chien, Kuan-Hua Chao, Chang-Po Ma, Yung Cheng, Shu-Hung Chou, Yih-Shin Weng, Ming-Shiam Tsai, Kun-Hung Hsieh, Kuang-Jung Chang, Jin-Chuan Hsu, Hsiu-Chen Peng, Alex Ho. 1022-1031 [doi]
• Printable electronics for polymer RFID applicationsM. Bohm, A. Ullmann, D. Zipperer, A. Knobloch, W. H. Glauert, W. Fix. 1034-1041 [doi]
• A 13.56MHz RFID System based on Organic TranspondersEugenio Cantatore, Thomas C. T. Geuns, Arnold F. A. Gruijthuijsen, Gerwin H. Gelinck, Steffen Drews, Dago M. De Leeuw. 1042-1051 [doi]
• Printed Electronic Nose Vapor Sensors for Consumer Product MonitoringV. Subramanian, J. B. Lee, V. H. Liu, S. Molesa. 1052-1059 [doi]
• An Organic FET SRAM for Braille Sheet Display with Back Gate to Increase Static Noise MarginMakoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Teruki Someya, Takayasu Sakurai. 1060-1069 [doi]
• Analog Signal Processing with Organic FETsN. Gay, W. J. Fischer, M. Halik, Hagen Klauk, Ute Zschieschang, G. Schmid. 1070-1079 [doi]
• A 2V Organic Complementary InverterStijn De Vusser, Soeren Steudel, Kris Myny, Jan Genoe, Paul Heremans. 1082-1091 [doi]
• CMOS-on-Plastic Technology using Sequential Laterally Solidified Silicon Thin-Film TransistorsM. G. Kane, L. Goodman, A. H. Firester, P. C. van der Wilt, A. V. Limanov, J. S. Im. 1092-1098 [doi]
• A 4.5mW Closed-Loop ΔΣ Micro-Gravity CMOS-SOI AccelerometerBabak Vakili-Amini, Reza Abdolvand, Farrokh Ayazi. 1101-1110 [doi]
• A Programmable MEMS FSK TransmitterWan-Thai Hsu, A. R. Brown, K. R. Cioffi. 1111-1120 [doi]
• A Self-Resonant MEMS-based Electrostatic Field Sensor with 4V/m/Hz SensitivityT. Denison, Jinbo Kuang, J. Shafran, M. Judy, K. Lundberg. 1121-1130 [doi]
• A CMOS Interface for a Gas-Sensor Array with a 0.5%-Linearity over 500kΧ-to-1GΧ Range and 2.5°C Temperature Control AccuracyMattia Malfatti, David Stoppa, Andrea Simoni, Leandro Lorenzelli, A. Adami, Andrea Baschirotto. 1131-1140 [doi]
• A CMOS Temperature-to-Frequency Converter with an Inaccuracy of 0.5°C (3 σ) from -40 to 105°CKofi A. A. Makinwa, Martijn F. Snoeij. 1141-1150 [doi]
• An Integrated Magnetic Sensor with Two Continuous-Time ΔΣ-Converters and Stress Compensation CapabilityM. Motz, Udo Ausserlechner, W. Scherr, B. Schaffer. 1151-1160 [doi]
• A 200dB Dynamic Range Iris-less CMOS Image Sensor with Lateral Overflow Integration Capacitor using Hybrid Voltage and Current Readout OperationNana Akahane, R. Ryuzaki, Satoru Adachi, Koichi Mizobuchi, Shigetoshi Sugawa. 1161-1170 [doi]
• A Back-Illuminated High-Sensitivity Small-Pixel Color CMOS Image Sensor with Flexible Layout of Metal WiringS. Iwabuchi, Y. Maruyama, Y. Ohgishi, M. Muramatsu, N. Karasawa, T. Hirayama. 1171-1178 [doi]
• Laser Radar Imager Based on 3D Integration of Geiger-Mode Avalanche Photodiodes with Two SOI Timing Circuit LayersB. Aull, J. Burns, Chenson Chen, B. Felton, H. Hanson, Craig L. Keast, Jeffrey M. Knecht, A. Loomis, M. Renzi, Antonio M. Soares, Vyshnavi Suntharalingam, Keith Warner, D. Wolfson, D.-R. Yost, Douglas Young. 1179-1188 [doi]
• An SOI-Based 7.5µm-Thick 0.15x0.15mm2 RFID ChipMitsuo Usami, Akira Sato, Hisao Tanabe, Toshiaki Iwamatsu, S. Maegawa, Y. Ohji. 1191-1200 [doi]
• A Passive UHF RFID Tag LSI with 36.6% Efficiency CMOS-Only Rectifier and Current-Mode Demodulator in 0.35µm FeRAM TechnologyHiroyuki Nakamoto, Daisuke Yamazaki, Takuji Yamamoto, Hajime Kurata, Satoshi Yamada, Kenji Mukaida, Tsuzumi Ninomiya, Takashi Ohkawa, Shoichi Masui, Kunihiko Gotoh. 1201-1210 [doi]
• A 3.4Mb/s RFID Front-end for Proximity Applications Based on a Delta-modulatorB. Gomez, Gilles Masson, P. Villard, G. Robert, François Dehmas, Jacques Reverdy. 1211-1217 [doi]
• A 60GHz CMOS VCO Using On-Chip Resonator with Embedded Artificial Dielectric for Size, Loss and Noise ReductionDaquan Huang, William Hant, Ning-Yi Wang, T. W. Ku, Qun Gu, R. Wong, Mau-Chung Frank Chang. 1218-1227 [doi]
• A 5.4GHz 0.35µm BiCMOS FBAR Resonator Oscillator in Above-IC TechnologyM. Aissi, E. Tournier, M.-A. Dubois, G. Parat, R. Plana. 1228-1235 [doi]
• Dielectrically Transduced Single-Ended to Differential MEMS FilterD. Weinstein, H. Chandrahalim, Lih Feng Cheow, S. A. Bhave. 1236-1243 [doi]
• A Low-Power 2.4GHz CMOS Receiver Front-End Using BAW ResonatorsJérémie Chabloz, Claude Muller, Franz Pengg, A. Pezous, Christian Enz, M.-A. Dubois. 1244-1253 [doi]
• A Miniature V-band 3-Stage Cascode LNA in 0.13µm CMOSChieh-Min Lo, Chin-Shen Lin, Huei Wang. 1254-1263 [doi]
• A 25Gb/s CDR in 90nm CMOS for High-Density InterconnectsChristian Kromer, G. Sialm, Christian Menolfi, Martin L. Schmatz, Frank Ellinger, Heinz Jäckel. 1266-1275 [doi]
• A 2.5Gb/s Multi-Rate 0.25µm CMOS CDR Utilizing a Hybrid Analog/Digital Loop FilterMichael H. Perrott, Yunteng Huang, R. T. Baird, Bruno W. Garlepp, Ligang Zhang, J. P. Hein. 1276-1285 [doi]
• 2 9mW Wide-Range Duty-Cycle Correcting False-Lock-Free DLL with Fully Balanced Charge-Pump for DDR InterfaceYusuke Tokunaga, Shiro Sakiyama, Shiro Dosho, Y. Doi, M. Hattori. 1286-1295 [doi]
• Improving CDR Performance via EstimationHaechang Lee, Akash Bansal, Yohan Frans, Jared Zerbe, S. Sidiropoulos, M. Horowitz. 1296-1303 [doi]
• A 3.2Gb/s Semi-Blind-Oversampling CDRMarcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker. 1304-1313 [doi]
• Data Recovery and Retiming for the Fully Buffered DIMM 4.8Gb/s Serial LinksHamid Partovi, W. Walthes, Luca Ravezzi, P. Lindt, S. Chokkalingam, Karthik Gopalakrishnan, A. Blum, Otto Schumacher, C. Andreotti, M. Bruennert, B. Celli-Urbani, D. Friebe, I. Koren, M. Verbeck, U. Lange. 1314-1323 [doi]
• A 10Gb/s CMOS CDR and DEMUX IC with a Quarter-Rate Linear Phase DetectorSangjin Byun, Jyung Chan Lee, Jae Hoon Shim, Kwangjoon Kim, Hyun-Kyu Yu. 1324-1333 [doi]
• A 20Gb/s Embedded Clock Transceiver in 90nm CMOSBryan Casper, James E. Jaussi, Frank O'Mahony, Mozhgan Mansuri, K. Canagasaby, Joe Kennedy, E. Yeung, Randy Mooney. 1334-1343 [doi]
• A 240W Monolithic Class-D Audio Amplifier Output StageF. Nyboe, C. Kaya, L. Risbo, P. Andreani. 1346-1355 [doi]
• Frequency Compensation of an SOI Bipolar-CMOSDMOS Car Audio PAR. van derZee, R. van Heeswijk. 1356-1365 [doi]
• A Digital Input Controller for Audio Class-D Amplifiers with 100W 0.004% THD+N and 113dB DRT. Ido, S. Ishizuka, L. Risbo, F. Aoyagi, T. Hamasaki. 1366-1375 [doi]
• A 4.1mW 79dB-DR 4th-order Source-FollowerBased Continuous-Time Filter for WLAN ReceiversS. D'Amico, Matteo Conta, Andrea Baschirotto. 1378-1387 [doi]
• A Micropower Chopper-Stabilized Operational Amplifier using a SC Notch Filter with Synchronous Integration inside the ContinuousTime Signal PathR. Burt, J. Zhang. 1388-1397 [doi]
• A Multi-Stage Interleaved Synchronous Buck Converter with Integrated Output Filter in a 0.18µ SiGe processSiamak Abedinpour, Bertan Bakkaloglu, Sayfe Kiaei. 1398-1407 [doi]
• A CMOS-Control Rectifier for DiscontinuousConduction Mode Switching DC-DC ConvertersTsz Yin Man, Philip K. T. Mok, Mansun Chan. 1408-1417 [doi]
• A 5GHz 108Mb/s 2x2 MIMO Transceiver with Fully Integrated +16dBm PAs in 90nm CMOSYorgos Palaskas, Ashoke Ravi, Stefano Pellerano, Brent R. Carlton, M. A. Elmala, Ralph E. Bishop, Gaurab Banerjee, R. B. Nicholls, S. Ling, Stewart S. Taylor, K. Soumyanath. 1420-1429 [doi]
• An IEEE 802.11a/b/g SoC for Embedded WLAN ApplicationsLalitkumar Nathawad, David Weber, Shahram Abdollahi-Alibeik, Phoebe Chen, Syed Enam, Brian Kaczynski, Alireza Kheirkhahi, MeeLan Lee, Sotirios Limotyrakis, Keith Onodera, Katelijn Vleugels, Masoud Zargari, Bruce A. Wooley. 1430-1439 [doi]
• A Wireless Transceiver with Integrated Data Converters for 802.11a/b/g Access PointsTony Montalvo, C. Angell, David J. McLaurin, Corey Petersen, E. Fogleman, Janet Brunsilius, Phil Brown, Ege Yetis, Jeff Bray, M. Kessler, Bernard Tenbroek. 1440-1449 [doi]
• A Highly Linear Direct-Conversion Transmit Mixer Transconductance Stage with Local Oscillation Feedthrough and I/Q Imbalance Cancellation SchemeC. Paul Lee, Arya Behzad, Dayo Ojo, Michael S. Kappes, Stephen Au, Meng-An Pan, Keith A. Carter, S. Tian. 1450-1459 [doi]
• An Ultra-Low Power 2.4GHz RF Transceiver for Wireless Sensor Networks in 0.13µm CMOS with 400mV Supply and an Integrated Passive RX Front-EndBen W. Cook, A. D. Berny, Alyosha C. Molnar, Steven Lanzisera, Kristofer S. J. Pister. 1460-1469 [doi]
• A Fully Integrated 2.4GHz IEEE 802.15.4 Compliant Transceiver for ZigBee ApplicationsW. Kluge, F. Poegel, H. Roller, M. Lange, T. Ferchland, L. Dathe, D. Eggert. 1470-1479 [doi]
• A 10.8mA Single Chip Transceiver for 430MHz Narrowband Systems in 0.15µm CMOSG. Hayashi, A. Sawada, Takashi Morie, K. Matsuyama, R. Kim, S. Yoshida, Akinori Matsumoto, K. Hijikata, Kazuo Matsukawa, Y. Tamura, J. Ogawa, T. Takita. 1480-1489 [doi]
• A Fully Integrated Auto-Calibrated SuperRegenerative ReceiverJia-yi Chen, Michael P. Flynn, John P. Hayes. 1490-1499 [doi]
• Free-Running Ring Frequency SynthesizerD. J. Allen, A. L. Carley. 1502-1511 [doi]
• Clock Generation and Distribution of a Dual-Core Xeon Processor with 16MB L3 CacheS. Tam, J. Leung, R. Limaye, S. Choy, S. Vora, M. Adachi. 1512-1521 [doi]
• A 5GHz Duty-Cycle Correcting Clock Distribution Network for the POWER6 MicroprocessorM. G. R. Thomson, Phillip J. Restle, Norman K. James. 1522-1529 [doi]
• A Receiver with Start-up Initialization and Programmable Delays for Wireless Clock DistributionXiaoling Guo, Dong-Jun Yang, Ran Li 0001, K. K. O. 1530-1539 [doi]
• A 1.1ghz charge-recovery logicVisvesh S. Sathe 0001, Juang-Ying Chueh, M. Papaefthymio. 1540-1549 [doi]
• A 3.5GHz Rotary-Traveling-Wave-Oscillator Clocked Dynamic Logic Family in 0.25µm CMOSJ. Wood, T. Edwards, C. Ziesler. 1550-1557 [doi]
• Distributed Loss Compensation for Low-latency On-chip InterconnectsA. P. Jose, K. L. Shepard. 1558-1567 [doi]
• A 125µw, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applicationsTsu-Ming Liu, Ting-An Lin, Sheng-Zen Wang, Wen-Ping Lee, Kang-Cheng Hou, Jiun-Yan Yang, Chen-Yi Lee. 1576-1585 [doi]
• 124Ms/s pixel-pipelined motion-JPEG 2000 codec without tile memoryYu-wei Chang, Hung-Chi Fang, Chih-Chi Cheng, Chun-Chia Chen, Chung-Jr Lian, Shao-Yi Chien, Liang-Gee Chen. 1586-1595 [doi]
• A 160kgate 4.5kB SKRAM H.264 video decoder for HDTV applicationsC. C. Lin, J. I. Guo, H.-C. Chang, Y. C. Yang, J. W. Chen, M.-C. Tsai, J.-S. Wang. 1596-1605 [doi]
• A 120Mvertices/s multi-threaded VLIW vertex processor for mobile multimedia applicationsChang-Hyo Yu, Kyusik Chung, Donghyun Kim, Lee-Sup Kim. 1606-1615 [doi]
• A 40GOPS 250mW massively parallel processor based on matrix architectureMasami Nakajima, Hideyuki Noda, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saitoh, Toru Shimizu. 1616-1625 [doi]
• A 5mW MPEG4 SP encoder with 2D bandwidth-sharing motion estimation for mobile applicationsChia-Ping Lin, Po-Chih Tseng, Yao-Ting Chiu, Siou-Shen Lin, Chih-Chi Cheng, Hung-Chi Fang, Wei-Min Chao, Liang-Gee Chen. 1626-1635 [doi]
• 6.33mW MPEG audio decoding on a multimedia processorY. Ueda, H. Yamauchi, M. Mukuno, S. Furuichi, M. Fujisawa, F. Qiao, H. Yang. 1636-1645 [doi]
• Active circuits for ultra-high efficiency micropower generators using nickel-63 radioisotopeR. Duggirala, Hui Li, A. Lai. 1648-1655 [doi]
• Circuit design issues in multi-gate FET CMOS technologiesChristian Pacha, Klaus von Arnim, Thomas Schulz, Weize Xiong, M. Gostkowski, Gerhard Knoblinger, Andrew Marshall, T. Nirschl, J. Berthold, Christian Russ, Harald Gossner, Charvaka Duvvury, Paul Patruno, C. Rinn Cleavelin, Klaus Schruefer. 1656-1665 [doi]
• A low-power true random number generator using random telegraph noise of single oxide-trapsRalf Brederlow, R. Prakash, Christian Paulus, Roland Thewes. 1666-1675 [doi]
• A 1Tb/s 3W inductive-coupling transceiver for inter-chip clock and data linkNoriyuki Miura, Daisuke Mizoguchi, M. Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda. 1676-1685 [doi]
• Optical interconnect technologies for high-speed VLSI chips using silicon nano-photonicsKeishi Ohashi, Junichi Fujikata, Masafumi Nakada, Tsutomu Ishi, Kenichi Nishi, Hirohito Yamada, M. Fukaishi, Masayuki Mizuno, Koichi Nose, I. Ogura, Yutaka Urino, T. Baba. 1686-1695 [doi]
• An asynchronous array of simple processors for dsp applicationsZhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, Omar Sattari, Michael A. Lai, Jeremy W. Webb, Eric W. Work, Tinoosh Mohsenin, M. Singh, Bevan M. Baas. 1696-1705 [doi]
• System-in-silicon architecture and its application to H.264/AVC motion estimation for 1080HDTVK. Kumagai, Changqi Yang, H. Izumino, N. Narita, K. Shinjo, S. Iwashita, Y. Nakaoka, T. Kawamura, H. Komabashiri, T. Minato, A. Arnbo, Takahiro Suzuki, Zhenyu Liu 0001, Yang Song 0002, Satoshi Goto, Takeshi Ikenaga, Y. Mabuchi, K. Yoshida. 1706-1715 [doi]
• A chip-scale electrical soliton modelocked oscillatorD. S. Rickett, D. Ham. 1716-1725 [doi]
• 4GHz+ low-latency fixed-point and binary floating-point execution units for the POWER6 processorBrian W. Curran, Bradley D. McCredie, Leonid Sigal, Eric M. Schwarz, Bruce M. Fleischer, Yuen H. Chan, D. Webber, Vaden Vaden, A. Goyal. 1728-1734 [doi]
• A 240ps 64b carry-lookahead adder in 90nm CMOSSean Kao, Radu Zlatanovici, Borivoje Nikolic. 1735-1744 [doi]
• A 64b adder using self-calibrating differential output prediction logicKian Haur Chong, Larry McMurchie, Carl Sechen. 1745-1754 [doi]
• A leakage current replica keeper for dynamic circuitsYolin Lih, Nestoras Tzartzanis, William W. Walker. 1755-1764 [doi]
• An on-chip delay- and skew-insensitive multicycle communication schemePeter Caputa, Christer Svensson. 1765-1774 [doi]
• A 14: 1 dynamic MUX FF with select activity detectionM. Sumita, T. Wada. 1775-1784 [doi]
• An 8.8GHz 198mW 16x64b 1R/1W variationtolerant register file in 65nm CMOSS. Hsu, A. Agarwal, M. Anders, S. Mathew, R. Krishnamurthy, S. Borkar. 1785-1797 [doi]
• A multipath technique for canceling harmonics and sidebands in a wideband power upconverterRameswor Shrestha, Eisse Mensink, Eric A. M. Klumperink, Gerard J. M. Wienk, Bram Nauta. 1800-1809 [doi]
• A complex image rejection circuit with sign detection onlySupisa Lerstaveesin, Bang-Sup Song. 1810-1819 [doi]
• On-chip image rejection in a low-if cmos receiverM. Hajirostam, K. Martin. 1820-1829 [doi]
• Active 2nd-order intermodulation calibration for direct-conversion receiversMinghui Chen, Yue Wu, M. F. Chang. 1830-1839 [doi]
• A 2.2GHz sub-harmonic mixer for directconversion receivers in 0.13µm CMOSH. C. Jen, S. C. Rose, R. G. Meyer. 1840-1849 [doi]
• A Blocker-Vigilant Channel-Select Filter with Adaptive IIP3 and Power DissipationAtsushi Yoshizawa, Yannis P. Tsividis. 1850-1859 [doi]
• An IP2 Improvement Technique for Zero-IF Down-ConvertersHooman Darabi, Hea Joung Kim, Janice Chiu, Brima Ibrahim, Louie Serrano. 1860-1869 [doi]
• Low Flicker-Noise Quadrature Mixer TopologyRajasekhar Pullela, Tirdad Sowlati, Dmitriy Rozenblit. 1870-1879 [doi]
• A 750mV 15kHz 1/f Noise Corner 51dBm IIP2 Direct-Conversion Front-End for GSM in 90nm CMOSMassimo Brandolini, Marco Sosio, Francesco Svelto. 1882-1891 [doi]
• A 5.4mW GPS CMOS Quadrature Front-End Based on a Single-Stage LNA-Mixer-VCOAntonio Liscidini, Andrea Mazzanti, R. Tonietto, L. Vandi, Pietro Andreani, Rinaldo Castello. 1892-1901 [doi]
• A 20mw 3.24mm2 fully integrated gps radio for cell-phonesValentina Delia Torre, Matteo Conta, Ramesh Chokkalingam, Giuseppe Cusmai, Paolo Rossi, Francesco Svelto. 1902-1911 [doi]
• Wideband Image-Rejection Circuit for Low-IF ReceiversK. Maeda, W. Hioe, Y. Kimura, S. Tanaka. 1912-1921 [doi]
• A 1.8GHz Spur-Cancelled Fractional-N Frequency Synthesizer with LMS-Based DAC Gain CalibrationManoj Gupta, Bang-Sup Song. 1922-1931 [doi]
• An 800MHz to 5GHz Software-Defined Radio Receiver in 90nm CMOSRahim Bagheri, Ahmad Mirzaei, Saeed Chehrazi, Mohammad E. Heidari, MinJae Lee, Mohyee Mikhemar, M. Tang, Asad A. Abidi. 1932-1941 [doi]
• A Fully Integrated SoC for GSM/GPRS in 0.13µm CMOSPierre-Henri Bonnaud, Markus Hammes, A. Hanke, Jens Kissing, R. Koch, E. Labarre, C. Schwoerer. 1942-1951 [doi]
• A 1.9GHz Single-Chip CMOS PHS CellphoneSrenik Mehta, William W. Si, Hirad Samavati, Manolis Terrovitis, Michael P. Mack, Keith Onodera, S. Jen, Susan Luschas, Sunetra Hwang, Sunetra Mendis, David K. Su, Bruce A. Wooley. 1952-1961 [doi]
• A 1.7GHz 1.5W CMOS RF Doherty Power Amplifier for Wireless CommunicationsN. Wongkomet, L. Tee, P. R. Gray. 1962-1971 [doi]
• A 1.2V Dual-Mode GSM/WCDMA - Modulator in 65nm CMOSJ. Jarvinen, K. Halonen. 1972-1981 [doi]
• A 1/1.8-inch 6.4MPixel 60 frames/s CMOS Image Sensor with Seamless Mode ChangeS. Yoshihara, Masaru Kikuchi, Y. Ito, Yoshiaki Inada, Souichiro Kuramochi, Hayato Wakabayashi, Masafumi Okano, K. Koseki, H. Kuriyama, J. Inutsuka, A. Tajima, T. Nakajima, Y. Kudoh, F. Koga, Y. Kasagi, S. Watanabe, Tetsuo Nomoto. 1984-1993 [doi]
• 1/2-inch 7.2MPixel CMOS Image Sensor with 2.25µm Pixels Using 4-Shared Pixel Structure for Pixel-Level SummationYoung-Chan Kim, Yi Tae Kim, Sung Ho Choi, Hae Kyung Kong, Sung In Hwang, Ju Hyun Ko, Bum Suk Kim, Tetsuo Asaba, Su Hun Lim, June Soo Hahn, Joon-Hyuk Im, Tae-seok Oh, Duk Min Yi, Jong Moon Lee, Woon Phil Yang, Jung Chak Ahn, Eun Seung Jung, Yong-Hee Lee. 1994-2003 [doi]
• A 3MPixel Low-Noise Flexible Architecture CMOS Image SensorJungwook Yang, Keith Fife, Lane Brooks, Charles G. Sodini, A. Betts, P. Mudunuru, Hae-Seung Lee. 2004-2013 [doi]
• A CMOS Imager with Column-Level ADC Using Dynamic Column FPN ReductionMartijn F. Snoeij, Albert Theuwissen, Kofi A. A. Makinwa, Johan H. Huijsing. 2014-2023 [doi]
• High-Speed Digital Double Sampling with Analog CDS on Column Parallel ADC Architecture for Low-Noise Active Pixel SensorY. Nitta, Y. Muramatsu, K. Amano, T. Toyama, J. Yamamoto, K. Mishina, A. Suzuki, T. Taura, A. Kato, M. Kikuchi, Y. Yasui, H. Nomura, N. Fukushima. 2024-2031 [doi]
• A 14b 74MS/s CMOS AFE for True High-Definition CamcordersR. A. Kapusta, S. Hatanaka, S. J. Decker, Jianrong Chen, D. Foley, A. Wellinger, Murat Ozbas, D. F. Kelly, M. T. Sayuk, W. G. Schofield, K. Nakamura. 2032-2039 [doi]
• CMOS Image Sensor with integrated 4Gb/s Camera Link TransmitterA. Krymski, K. Tajima. 2040-2049 [doi]
• A 128 x128 33mW 30frames/s single-chip stereo imagerRalf M. Philipp, Ralph Etienne-Cummings. 2050-2059 [doi]
• A 128 X 128 120db 30mw asynchronous vision sensor that responds to relative intensity changePatrick Lichtsteiner, Christoph Posch, Tobias Delbrück. 2060-2069 [doi]
• A 5V AC-Powered CMOS Filter-Selectivity Booster for POTS/ADSL Splitter Size ReductionE. Sackinger, A. Tennen, D. Shulman, B. Wani, M. Rambaud, D. Lim, F. Larsen, G. S. Moschytz. 2072-2081 [doi]
• A DC-to-44-GHz 19dB Gain Amplifier in 90nm CMOS Using Capacitive Bandwidth EnhancementJ. R. M. Weiss, Marcel A. Kossel, Christian Menolfi, Thomas Morf, Martin L. Schmatz, Thomas Toifl, Heinz Jäckel. 2082-2091 [doi]
• A 10Gb/s CMOS AGC Amplifier with 35dB Dynamic Range for 10Gb EthernetChih-Fan Liao, Shen-Iuan Liu. 2092-2101 [doi]
• A 20Gb/s Bidirectional Transceiver Using a Resistor-Transconductor HybridY. Tomita, H. Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, T. Kuroda. 2102-2111 [doi]
• A 1ps-Resolution Jitter-Measurement Macro Using Interpolated Jitter OversamplingK. Nose, M. Kajita, M. Mizuno. 2112-2121 [doi]
• 1.83ps-Resolution CMOS Dynamic Arbitrary Timing Generator for >4GHz ATE ApplicationsToshiyuki Okayasu, Masakatsu Suda, Kazuhiro Yamamoto, Shusuke Kantake, Satoshi Sudou, Daisuke Watanabe. 2122-2131 [doi]
• A Clock Duty-Cycle Correction and Adjustment CircuitJames S. Humble, P. J. Zabinski, Barry K. Gilbert, Erik S. Daniel. 2132-2141 [doi]
• Performance Variations of a 66GHz Static CML Divider in 90nm CMOSJean-Olivier Plouchart, Jonghae Kim, V. Karam, Robert Trzcinski, J. Gross. 2142-2151 [doi]
• A 20gb/s 1: 4 DEMUX without inductors in 0.13µm CMOSByung-Guk Kim, Lee-Sup Kim, Sangjin Byun, Hyun-Kyu Yu. 2152-2159 [doi]
• 104Gb/s 2"-1 and 110Gb/s 2-1 PRBS Generator in InP HBT TechnologyT. Kjellberg, Joakim Hallin, T. Swahn. 2160-2169 [doi]
• TM 970MP MicroprocessorHendrik F. Hamann, Alan J. Weger, James A. Lacey, Erwin Cohen, C. Atherton. 2172-2179 [doi]
• A Linear Regulator with Fast Digital Control for Biasing Integrated DC-DC ConvertersPeter Hazucha, Sung Tae Moon, Gerhard Schrom, Fabrice Paillet, Donald S. Gardner, Saravanan Rajapandian, Tanay Karnik. 2180-2189 [doi]
• Increasing Microprocessor Speed by Massive Application of On-Die High-K MIM Decoupling CapacitorsH. Sanchez, B. Johnstone, D. Roberts, O. Mandhana, B. Melnick, M. Celik, M. Baker, J. Hayden, Byoung Min, J. Edgerton, B. White. 2190-2199 [doi]
• Hierarchical Power Distribution with 20 Power Domains in 90-nm Low-Power Multi-CPU ProcessorYusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, T. Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, N. Irie. 2200-2209 [doi]
• A Power Management Scheme Controlling 20 Power Domains for a Single-Chip Mobile ProcessorT. Hattori, T. lrita, M. Ito, Eiji Yamamoto, H. Kato, Go Sado, Y. Yamada, K. Nishiyama, Hiroshi Yagi, T. Koike, Yoshihiko Tsuchihashi, Motoki Higashida, Hiroyuki Asano, Izumi Hayashibara, Ken Tatezawa, Yasuhisa Shimazaki, Naozumi Morino, K. Hirose, Saneaki Tamaki, Shinichi Yoshioka, Reiko Tsuchihashi, N. Arai, T. Akiyama, K. Ohno. 2210-2219 [doi]
• A Signal-Integrity Self-Test Concept for Debugging Nanometer CMOS ICsV. Petrescu, M. Pelgrom, H. Veendrick, P. Pavithran, J. Wieling. 2220-2229 [doi]
• ESD Protection for Mixed-Voltage I/O in LowVoltage Thin-Oxide CMOSMing-Dou Ker, Wei-Jen Chang, Chang-Tzu Wang, Wen-Yi Chen. 2230-2237 [doi]
• A Circuit for Reducing Large Transient Current Effects on Processor Power GridsEskinder Hailu, David W. Boerstler, Kazuhiko Miki, Jieming Qi, M. Wang, Mack W. Riley. 2238-2245 [doi]
• Neurons to Silicon: Implantable Prosthesis ProcessorStephen O'Driscoll, Teresa H. Meng, Krishna V. Shenoy, Caleb Kemere. 2248-2257 [doi]
• A Low-Power Integrated Circuit for a Wireless 100-Electrode Neural Recording SystemReid R. Harrison, Paul T. Watkins, Ryan J. Kier, Robert O. Lovejoy, Daniel J. Black, Richard A. Normann, Florian Solzbacher. 2258-2267 [doi]
• A 360-Channel Speech Preprocessor that Emulates the Cochlear AmplifierBo Wen, Kwabena Boahen. 2268-2277 [doi]
• A 2Mb/s Wideband Pulse Transceiver with Direct-Coupled Interface for Human Body CommunicationsSeong-Jun Song, Namjun Cho, Sunyoung Kim, Jerald Yoo, Hoi-Jun Yoo. 2278-2287 [doi]
• CMOS Integrated DNA Chip for Quantitative DNA AnalysisN. Gemma, S. O'Uchi, H. Funaki, J. Okada, S. Hongo. 2288-2297 [doi]
• A Wireless Bio-MEMS Sensor for C-Reactive Protein Detection Based on NanomechanicsC.-H. Chen, R. Z. Hwang, L. S. Huang, S. Lin, H. C. Chen, Y. C. Yang, Y. T. Lin, S.-A. Yu, Y. H. Wang, N.-K. Chou, S.-S. Lu. 2298-2307 [doi]
• A 0.16pJ/Conversion-Step 2.5mW 1.25GS/s 4b ADC in a 90nm Digital CMOS ProcessGeert Van der Plas, Stefaan Decoutere, Stéphane Donnay. 2310 [doi]
• A 90nm CMOS 1.2v 6b 1GS/s two-step subranging ADCPedro M. Figueiredo, P. Cardoso, A. Lopes, C. Fachada, N. Hamanishi, K. Tanabe, João C. Vital. 2320-2329 [doi]
• A 4GS/s 4b Flash ADC in 0.18µm CMOSSunghyun Park, Yorgos Palaskas, Michael P. Flynn. 2330-2339 [doi]
• A 22GS/s 5b adc in 0.13µm SiGe BiCMOSPeter Schvan, Daniel Pollex, Shing-Chi Wang, Chris Falt, Naim Ben Hamida. 2340-2349 [doi]
• A 6b 600MS/s 5.3mW Asynchronous ADC in 0.13µm CMOSMike Shuo-Wei Chen, Robert W. Brodersen. 2350-2359 [doi]
• A 1GS/s 11b Time-Interleaved ADC in 0.13µm CMOSSandeep Gupta, M. Choi, Michael Inerfield, Jingbo Wang. 2360-2369 [doi]
• A Bandpass ΔΣ RF-DAC with Embedded FIR Reconstruction FilterShahin Mehdizad Taleie, Tino Copani, Bertan Bakkaloglu, Sayfe Kiaei. 2370-2379 [doi]
• A 0.36W 6b up to 20GS/s DAC for UWB Wave FormationDalius Baranauskas, Denis Zelenin. 2380-2389 [doi]
• A 14b 100MS/s DAC with Fully Segmented Dynamic Element MatchingKok Lim Chan, Ian Galton. 2390-2399 [doi]
• A PVT-Tolerant Low-1/f Noise Dual-Loop Hybrid PLL in 0.18µmHyung-Rok Lee, Ook Kim, Keewook Jung, J. Shin, Deog Kyoon Jeong. 2402-2411 [doi]
• A 0.5 to 2.5GHz PLL with Fully Differential Supply-Regulated TuningMerrick Brownlee, Pavan Kumar Hanumolu, Kartikeya Mayaram, Un-Ku Moon. 2412-2421 [doi]
• A PLL for a DVD-16 Write System with 63 Output Phases and 32ps ResolutionShiro Dosho, Shiro Sakiyama, Noriaki Takeda, Yusuke Tokunaga, Takashi Morie. 2422-2431 [doi]
• A Spur Suppression Technique for Phase-Locked Frequency SynthesizersTai-Cheng Lee, Wei-Liang Lee. 2432-2441 [doi]
• A 6.25GHz 1V LC-PLL in 0.13µm CMOSR. Gu, Ah-Lyan Yee, Yiqun Xie, Wai Lee. 2442-2451 [doi]
• A Reversible Poly-Phase Distributed VCONestoras Tzartzanis, William W. Walker. 2452-2461 [doi]
• A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOSGeorge von Büren, Christian Kromer, Frank Ellinger, Alex Huber, Martin L. Schmatz, Heinz Jäckel. 2462-2471 [doi]
• 70GHz CMOS Harmonic Injection-Locked DividerK. Yamamoto, M. Fujishima. 2472-2481 [doi]
• A 16-to-18GHz 0.18-m Epi-CMOS Divide-by-3 Injection-Locked Frequency DividerHui Wu, Lin Zhang. 2482-2491 [doi]
• A 0.18µm CMOS Dual-Band Direct-Conversion DVB-H ReceiverIason Vassiliou, Kostis Vavelidis, Stamatis Bouras, Spyros Kavadias, Yiannis Kokolakis, George Kamoulakos, Aristeidis Kyranas, Charalambos Kapnistis, Nikos Haralabidis. 2494-2503 [doi]
• A Multi-Band Multi-Mode CMOS DirectConversion DVB-H TunerYoung-Jin Kim, Jae-Wan Kim, V. N. Parkhomenko, Donghyun Baek, Jae-Heon Lee, Eun-yung Sung, Iiku Nam, Byeong-ha Park. 2504-2513 [doi]
• Dual-band Single-Ended-Input Direct-Conversion DVB-H ReceiverM. Womac, Armin Deiss, T. Davis, R. Spencer, Buddhika Abesingha, Phil Hisayasu. 2514-2523 [doi]
• A Dual-Channel Direct-Conversion CMOS Receiver for Mobile Multimedia BroadcastingV. Peluso, Yang Xu, P. Gazzerro, Yiwu Tang, Li Liu, Zhenbiao Li, Wei Xiong, Charles Persico. 2524-2533 [doi]
• A 100mW Dual-Band CMOS Mobile-TV Tuner IC for T-DMB/DAB and ISDB-TBonkee Kim, Tae-Wook Kim, Youngho Cho, Minsu Jeong, Seyeob Kim, Heeyong Yoo, Seong-Mo Moon, Tae-Ju Lee, Jin Kyu Lim, Boeun Kim. 2534-2543 [doi]
• A 1.8dB NF 112mW Single-Chip Diversity Tuner for 2.6GHz S-DMB ApplicationsMyung-woon Hwang, Sungho Beck, Sunki Min, Sanghoon Lee, Seungyup Yoo, Kyoohyun Lim, Hyosun Jung, Jeong-Cheol Lee, Seokyong Hong, ChangHee Lee, Kyunglok Kim, Hyunji Song, Gyu-Hyeong Cho, Sangwoo Han. 2544-2551 [doi]
• rms Phase-Noise Ring-Oscillator-Based Frequency Synthesizer for Low-IF Single-Chip DBS Satellite Tuner-Demodulator SoCA. Maxim, R. Poorfard, J. Kao. 2552-2561 [doi]
• A 5.6GHz 64kB Dual-Read Data Cache for the POWER6TM ProcessorJohn Davis, Don Plass, Paul Bunce, Yuen H. Chan, Antonio Pelella, Rajiv V. Joshi, A. Chen, William V. Huott, Thomas J. Knips, Pradip Patel, K. Lo, Eric Fluhr. 2564-2571 [doi]
• cc SRAM Building Block in 65nm CMOSMuhammad M. Khellah, Nam Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De. 2572-2581 [doi]
• A 72Mb Separate-I/O Synchronous SRAM Chip with 504Gb/s Data BandwidthChih Tseng, Jae-Hyeong Kim, S. Chen, Mu-Hsiang Huang, Chungji Lu, I. Hashiguchi, Y. Miyazima, M. Ichihashi, K. Maki, K. Nakashima, P. Chuang. 2582-2591 [doi]
• A 256kb Sub-threshold SRAM in 65nm CMOSBenton H. Calhoun, Anantha Chandrakasan. 2592-2601 [doi]
• Redefinition of Write Margin for Next-Generation SRAM and Write-Margin Monitoring CircuitK. Takeda, H. Ikeda, Y. Hagihara, M. Nomura, H. Kobatake. 2602-2611 [doi]
• Thyristor-Based Volatile Memory in Nano-Scale CMOSR. Roy, F. Nemati, K. Young, B. Bateman, R. Chopra, Seong-Ook Jung, Chiming Show, Hyun-jin Cho. 2612-2621 [doi]